uart0: UART.PL011 @ sysbus 0x10009000
    -> gic@5

uart1: UART.PL011 @ sysbus 0x1000A000
    -> gic@6

uart2: UART.PL011 @ sysbus 0x1000B000
    -> gic@7

uart3: UART.PL011 @ sysbus 0x1000C000
    -> gic@8

memory: Memory.MappedMemory @ {
        sysbus 0x80000000;
        sysbus 0xA0000000
    }
    size: 0x20000000

sram: Memory.MappedMemory @ sysbus 0x48000000
    size: 0x02000000

timer1: Timers.ARM_SP804_Timer @ sysbus 0x10011000
    -> gic@2

timer2: Timers.ARM_SP804_Timer @ sysbus 0x10012000
    -> gic@3

sysCtl: Miscellaneous.ArmSysCtl @ sysbus <0x10000000, +0x1000>
    procId: 0x0C000191

pl310: Cache.PL310 @ sysbus <0x1E00A000, +0x10000>

pl031: Timers.PL031 @ sysbus 0x10017000
    -> gic@4

usbEhci: USBDeprecated.ISP1761 @ sysbus <0x4F000000, +0xFFFF>
    -> gic@16

kmi0: Input.PL050 @ sysbus <0x10006000, +0x1000>
    -> gic@12

kmi1: Input.PL050 @ sysbus <0x10007000, +0x1000>
    -> gic@13

gic: IRQControllers.ARM_GenericInterruptController @ {
        sysbus new Bus.BusMultiRegistration { address: 0x1E001000; size: 0x1000; region: "distributor"};
        sysbus new Bus.BusMultiRegistration { address: 0x1E000100; size: 0x100; region: "cpuInterface"}
    }
    supportsTwoSecurityStates: false
    architectureVersion: .GICv1
    // GIC -> ARM CPU interrupt connections are generated automatically

cpu: CPU.ARMv7A @ sysbus
    cpuType: "cortex-a9"
    genericInterruptController: gic

sysbus:
    init:
        Tag <0x1C0A0000,0x1C0A0FFF> "UART1"
        Tag <0x1C0B0000,0x1C0B0FFF> "UART2"
        Tag <0x1C0C0000,0x1C0C0FFF> "UART3"
        Tag <0x40000000,0x43FFFFFF> "flash0"
        Tag <0x44000000,0x47FFFFFF> "flash1"
        Tag <0x1E000000,0x1E000FFF> "SCU_BASE"
        Tag <0x10001000,0x10002FFF> "SP810_sysctl"
        Tag <0x10004000,0x10004FFF> "PL041_audio"

