addrmap EFR32xG2_CMU_3 {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Ipversion";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ipversion @ 0x0;
    reg {
        name="Ctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ctrl @ 0x4;
    reg {
        name="Status";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Status @ 0x8;
    reg {
        name="Lock";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Lock @ 0x10;
    reg {
        name="Wdoglock";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Wdoglock @ 0x14;
    reg {
        name="If";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } If @ 0x20;
    reg {
        name="Ien";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ien @ 0x24;
    reg {
        name="Test";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Test @ 0x30;
    reg {
        name="Testhv";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Testhv @ 0x34;
    reg {
        name="Testclken";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Testclken @ 0x40;
    reg {
        name="Calcmd";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Calcmd @ 0x50;
    reg {
        name="Calctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Calctrl @ 0x54;
    reg {
        name="Calcnt";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Calcnt @ 0x58;
    reg {
        name="Clken0";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Clken0 @ 0x64;
    reg {
        name="Clken1";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Clken1 @ 0x68;
    reg {
        name="Sysclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Sysclkctrl @ 0x70;
    reg {
        name="Seclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Seclkctrl @ 0x74;
    reg {
        name="Traceclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Traceclkctrl @ 0x80;
    reg {
        name="Exportclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Exportclkctrl @ 0x90;
    reg {
        name="Dpllrefclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Dpllrefclkctrl @ 0x100;
    reg {
        name="Em01grpaclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Em01grpaclkctrl @ 0x120;
    reg {
        name="Em01grpcclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Em01grpcclkctrl @ 0x128;
    reg {
        name="Em23grpaclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Em23grpaclkctrl @ 0x140;
    reg {
        name="Em4grpaclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Em4grpaclkctrl @ 0x160;
    reg {
        name="Iadcclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Iadcclkctrl @ 0x180;
    reg {
        name="Wdog0clkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Wdog0clkctrl @ 0x200;
    reg {
        name="Wdog1clkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Wdog1clkctrl @ 0x208;
    reg {
        name="Eusart0clkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Eusart0clkctrl @ 0x220;
    reg {
        name="Synthclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Synthclkctrl @ 0x230;
    reg {
        name="Sysrtc0clkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Sysrtc0clkctrl @ 0x240;
    reg {
        name="Lcdclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Lcdclkctrl @ 0x250;
    reg {
        name="Vdac0clkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Vdac0clkctrl @ 0x260;
    reg {
        name="Pcnt0clkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Pcnt0clkctrl @ 0x270;
    reg {
        name="Radioclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Radioclkctrl @ 0x280;
    reg {
        name="Dapclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Dapclkctrl @ 0x284;
    reg {
        name="Lesensehfclkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Lesensehfclkctrl @ 0x290;
    reg {
        name="Vdac1clkctrl";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Vdac1clkctrl @ 0x294;
    reg {
        name="Rpuratd0_Drpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Rpuratd0_Drpu @ 0x298;
    reg {
        name="Rpuratd1_Drpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Rpuratd1_Drpu @ 0x29c;
    reg {
        name="Rpuratd2_Drpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Rpuratd2_Drpu @ 0x2a0;
    reg {
        name="Rpuratd3_Drpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Rpuratd3_Drpu @ 0x2a4;
    reg {
        name="Rpuratd4_Drpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Rpuratd4_Drpu @ 0x2a8;
    reg {
        name="Rpuratd5_Drpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Rpuratd5_Drpu @ 0x2ac;
    reg {
        name="Ipversion_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ipversion_SET @ 0x1000;
    reg {
        name="Ctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ctrl_SET @ 0x1004;
    reg {
        name="Status_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_SET @ 0x1008;
    reg {
        name="Lock_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_SET @ 0x1010;
    reg {
        name="Wdoglock_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdoglock_SET @ 0x1014;
    reg {
        name="If_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } If_SET @ 0x1020;
    reg {
        name="Ien_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ien_SET @ 0x1024;
    reg {
        name="Test_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Test_SET @ 0x1030;
    reg {
        name="Testhv_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Testhv_SET @ 0x1034;
    reg {
        name="Testclken_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Testclken_SET @ 0x1040;
    reg {
        name="Calcmd_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calcmd_SET @ 0x1050;
    reg {
        name="Calctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calctrl_SET @ 0x1054;
    reg {
        name="Calcnt_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calcnt_SET @ 0x1058;
    reg {
        name="Clken0_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Clken0_SET @ 0x1064;
    reg {
        name="Clken1_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Clken1_SET @ 0x1068;
    reg {
        name="Sysclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sysclkctrl_SET @ 0x1070;
    reg {
        name="Seclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seclkctrl_SET @ 0x1074;
    reg {
        name="Traceclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Traceclkctrl_SET @ 0x1080;
    reg {
        name="Exportclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Exportclkctrl_SET @ 0x1090;
    reg {
        name="Dpllrefclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dpllrefclkctrl_SET @ 0x1100;
    reg {
        name="Em01grpaclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em01grpaclkctrl_SET @ 0x1120;
    reg {
        name="Em01grpcclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em01grpcclkctrl_SET @ 0x1128;
    reg {
        name="Em23grpaclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em23grpaclkctrl_SET @ 0x1140;
    reg {
        name="Em4grpaclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em4grpaclkctrl_SET @ 0x1160;
    reg {
        name="Iadcclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iadcclkctrl_SET @ 0x1180;
    reg {
        name="Wdog0clkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdog0clkctrl_SET @ 0x1200;
    reg {
        name="Wdog1clkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdog1clkctrl_SET @ 0x1208;
    reg {
        name="Eusart0clkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Eusart0clkctrl_SET @ 0x1220;
    reg {
        name="Synthclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Synthclkctrl_SET @ 0x1230;
    reg {
        name="Sysrtc0clkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sysrtc0clkctrl_SET @ 0x1240;
    reg {
        name="Lcdclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lcdclkctrl_SET @ 0x1250;
    reg {
        name="Vdac0clkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Vdac0clkctrl_SET @ 0x1260;
    reg {
        name="Pcnt0clkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Pcnt0clkctrl_SET @ 0x1270;
    reg {
        name="Radioclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioclkctrl_SET @ 0x1280;
    reg {
        name="Dapclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dapclkctrl_SET @ 0x1284;
    reg {
        name="Lesensehfclkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lesensehfclkctrl_SET @ 0x1290;
    reg {
        name="Vdac1clkctrl_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Vdac1clkctrl_SET @ 0x1294;
    reg {
        name="Rpuratd0_Drpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd0_Drpu_SET @ 0x1298;
    reg {
        name="Rpuratd1_Drpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd1_Drpu_SET @ 0x129c;
    reg {
        name="Rpuratd2_Drpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd2_Drpu_SET @ 0x12a0;
    reg {
        name="Rpuratd3_Drpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd3_Drpu_SET @ 0x12a4;
    reg {
        name="Rpuratd4_Drpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd4_Drpu_SET @ 0x12a8;
    reg {
        name="Rpuratd5_Drpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd5_Drpu_SET @ 0x12ac;
    reg {
        name="Ipversion_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ipversion_CLR @ 0x2000;
    reg {
        name="Ctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ctrl_CLR @ 0x2004;
    reg {
        name="Status_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_CLR @ 0x2008;
    reg {
        name="Lock_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_CLR @ 0x2010;
    reg {
        name="Wdoglock_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdoglock_CLR @ 0x2014;
    reg {
        name="If_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } If_CLR @ 0x2020;
    reg {
        name="Ien_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ien_CLR @ 0x2024;
    reg {
        name="Test_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Test_CLR @ 0x2030;
    reg {
        name="Testhv_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Testhv_CLR @ 0x2034;
    reg {
        name="Testclken_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Testclken_CLR @ 0x2040;
    reg {
        name="Calcmd_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calcmd_CLR @ 0x2050;
    reg {
        name="Calctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calctrl_CLR @ 0x2054;
    reg {
        name="Calcnt_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calcnt_CLR @ 0x2058;
    reg {
        name="Clken0_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Clken0_CLR @ 0x2064;
    reg {
        name="Clken1_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Clken1_CLR @ 0x2068;
    reg {
        name="Sysclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sysclkctrl_CLR @ 0x2070;
    reg {
        name="Seclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seclkctrl_CLR @ 0x2074;
    reg {
        name="Traceclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Traceclkctrl_CLR @ 0x2080;
    reg {
        name="Exportclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Exportclkctrl_CLR @ 0x2090;
    reg {
        name="Dpllrefclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dpllrefclkctrl_CLR @ 0x2100;
    reg {
        name="Em01grpaclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em01grpaclkctrl_CLR @ 0x2120;
    reg {
        name="Em01grpcclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em01grpcclkctrl_CLR @ 0x2128;
    reg {
        name="Em23grpaclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em23grpaclkctrl_CLR @ 0x2140;
    reg {
        name="Em4grpaclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em4grpaclkctrl_CLR @ 0x2160;
    reg {
        name="Iadcclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iadcclkctrl_CLR @ 0x2180;
    reg {
        name="Wdog0clkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdog0clkctrl_CLR @ 0x2200;
    reg {
        name="Wdog1clkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdog1clkctrl_CLR @ 0x2208;
    reg {
        name="Eusart0clkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Eusart0clkctrl_CLR @ 0x2220;
    reg {
        name="Synthclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Synthclkctrl_CLR @ 0x2230;
    reg {
        name="Sysrtc0clkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sysrtc0clkctrl_CLR @ 0x2240;
    reg {
        name="Lcdclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lcdclkctrl_CLR @ 0x2250;
    reg {
        name="Vdac0clkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Vdac0clkctrl_CLR @ 0x2260;
    reg {
        name="Pcnt0clkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Pcnt0clkctrl_CLR @ 0x2270;
    reg {
        name="Radioclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioclkctrl_CLR @ 0x2280;
    reg {
        name="Dapclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dapclkctrl_CLR @ 0x2284;
    reg {
        name="Lesensehfclkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lesensehfclkctrl_CLR @ 0x2290;
    reg {
        name="Vdac1clkctrl_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Vdac1clkctrl_CLR @ 0x2294;
    reg {
        name="Rpuratd0_Drpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd0_Drpu_CLR @ 0x2298;
    reg {
        name="Rpuratd1_Drpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd1_Drpu_CLR @ 0x229c;
    reg {
        name="Rpuratd2_Drpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd2_Drpu_CLR @ 0x22a0;
    reg {
        name="Rpuratd3_Drpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd3_Drpu_CLR @ 0x22a4;
    reg {
        name="Rpuratd4_Drpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd4_Drpu_CLR @ 0x22a8;
    reg {
        name="Rpuratd5_Drpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd5_Drpu_CLR @ 0x22ac;
    reg {
        name="Ipversion_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ipversion_TGL @ 0x3000;
    reg {
        name="Ctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ctrl_TGL @ 0x3004;
    reg {
        name="Status_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_TGL @ 0x3008;
    reg {
        name="Lock_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_TGL @ 0x3010;
    reg {
        name="Wdoglock_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdoglock_TGL @ 0x3014;
    reg {
        name="If_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } If_TGL @ 0x3020;
    reg {
        name="Ien_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ien_TGL @ 0x3024;
    reg {
        name="Test_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Test_TGL @ 0x3030;
    reg {
        name="Testhv_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Testhv_TGL @ 0x3034;
    reg {
        name="Testclken_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Testclken_TGL @ 0x3040;
    reg {
        name="Calcmd_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calcmd_TGL @ 0x3050;
    reg {
        name="Calctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calctrl_TGL @ 0x3054;
    reg {
        name="Calcnt_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Calcnt_TGL @ 0x3058;
    reg {
        name="Clken0_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Clken0_TGL @ 0x3064;
    reg {
        name="Clken1_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Clken1_TGL @ 0x3068;
    reg {
        name="Sysclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sysclkctrl_TGL @ 0x3070;
    reg {
        name="Seclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seclkctrl_TGL @ 0x3074;
    reg {
        name="Traceclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Traceclkctrl_TGL @ 0x3080;
    reg {
        name="Exportclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Exportclkctrl_TGL @ 0x3090;
    reg {
        name="Dpllrefclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dpllrefclkctrl_TGL @ 0x3100;
    reg {
        name="Em01grpaclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em01grpaclkctrl_TGL @ 0x3120;
    reg {
        name="Em01grpcclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em01grpcclkctrl_TGL @ 0x3128;
    reg {
        name="Em23grpaclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em23grpaclkctrl_TGL @ 0x3140;
    reg {
        name="Em4grpaclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em4grpaclkctrl_TGL @ 0x3160;
    reg {
        name="Iadcclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iadcclkctrl_TGL @ 0x3180;
    reg {
        name="Wdog0clkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdog0clkctrl_TGL @ 0x3200;
    reg {
        name="Wdog1clkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Wdog1clkctrl_TGL @ 0x3208;
    reg {
        name="Eusart0clkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Eusart0clkctrl_TGL @ 0x3220;
    reg {
        name="Synthclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Synthclkctrl_TGL @ 0x3230;
    reg {
        name="Sysrtc0clkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sysrtc0clkctrl_TGL @ 0x3240;
    reg {
        name="Lcdclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lcdclkctrl_TGL @ 0x3250;
    reg {
        name="Vdac0clkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Vdac0clkctrl_TGL @ 0x3260;
    reg {
        name="Pcnt0clkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Pcnt0clkctrl_TGL @ 0x3270;
    reg {
        name="Radioclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioclkctrl_TGL @ 0x3280;
    reg {
        name="Dapclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dapclkctrl_TGL @ 0x3284;
    reg {
        name="Lesensehfclkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lesensehfclkctrl_TGL @ 0x3290;
    reg {
        name="Vdac1clkctrl_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Vdac1clkctrl_TGL @ 0x3294;
    reg {
        name="Rpuratd0_Drpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd0_Drpu_TGL @ 0x3298;
    reg {
        name="Rpuratd1_Drpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd1_Drpu_TGL @ 0x329c;
    reg {
        name="Rpuratd2_Drpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd2_Drpu_TGL @ 0x32a0;
    reg {
        name="Rpuratd3_Drpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd3_Drpu_TGL @ 0x32a4;
    reg {
        name="Rpuratd4_Drpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd4_Drpu_TGL @ 0x32a8;
    reg {
        name="Rpuratd5_Drpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rpuratd5_Drpu_TGL @ 0x32ac;
} Registers_addrmap;


};