addrmap LiteX_Framebuffer {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="UnderflowEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UnderflowEnable @ 0x0;
    reg {
        name="UnderflowUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UnderflowUpdate @ 0x4;
    reg {
        name="UnderflowCounter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UnderflowCounter @ 0x8;
    reg {
        name="InitiatorEnable";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_1[0:0];
    } InitiatorEnable @ 0x18;
    reg {
        name="InitiatorHres";
        regwidth=0x20;
            field {
                sw = rw;
            } h_res_idx[7:0];
    } InitiatorHres [2]@ 0x1c += 4;
    reg {
        name="InitiatorHsyncStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitiatorHsyncStart @ 0x24;
    reg {
        name="InitiatorHsyncEnd";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitiatorHsyncEnd @ 0x2c;
    reg {
        name="InitiatorHscan";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitiatorHscan @ 0x34;
    reg {
        name="InitiatorVres";
        regwidth=0x20;
            field {
                sw = rw;
            } v_res_idx[7:0];
    } InitiatorVres [2]@ 0x3c += 4;
    reg {
        name="InitiatorVsyncStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitiatorVsyncStart @ 0x44;
    reg {
        name="InitiatorVsyncEnd";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitiatorVsyncEnd @ 0x4c;
    reg {
        name="InitatorVscan";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitatorVscan @ 0x54;
    reg {
        name="InitiatorBase";
        regwidth=0x20;
            field {
                sw = rw;
            } base_idx[7:0];
    } InitiatorBase [4]@ 0x5c += 4;
    reg {
        name="InitiatorLenght";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitiatorLenght @ 0x6c;
    reg {
        name="DmaDelay";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaDelay @ 0x7c;
    reg {
        name="DriverClockingMMCMReset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriverClockingMMCMReset @ 0x8c;
    reg {
        name="DriverClockingMMCMRead";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriverClockingMMCMRead @ 0x90;
    reg {
        name="DriverClockingMMCMWrite";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriverClockingMMCMWrite @ 0x94;
    reg {
        name="DriverClockingMMCMDrdy";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_2[0:0];
    } DriverClockingMMCMDrdy @ 0x98;
    reg {
        name="DriverClockingMMCMAdr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriverClockingMMCMAdr @ 0x9c;
    reg {
        name="DriverClockingMMCMDatW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriverClockingMMCMDatW @ 0xa0;
    reg {
        name="DriverClockingMMCMDatR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriverClockingMMCMDatR @ 0xa8;
} Registers_addrmap;


};