addrmap S32K3XX_ModeEntryModule {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="ControlKey";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } CTL_KEY_Control_Key[15:0];
    } ControlKey @ 0x0;
    reg {
        name="ModeConfiguration";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEST_RST_Destructive_Reset_Request[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FUNC_RST_Functional_Reset_Request[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } STANDBY_Standby_Request[15:15];
    } ModeConfiguration @ 0x4;
    reg {
        name="ModeUpdate";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODE_UPD_Mode_Update[0:0];
    } ModeUpdate @ 0x8;
    reg {
        name="ModeStatus";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PREV_MODE_Previous_Mode[0:0];
    } ModeStatus @ 0xc;
    reg {
        name="MainCoreID";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CIDX_Core_Index[1:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PIDX_Partition_Index[12:8];
    } MainCoreID @ 0x10;
    reg {
        name="Partition0ProcessConfiguration";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } PCE_Partition_Clock_Enable[0:0];
    } Partition0ProcessConfiguration @ 0x100;
    reg {
        name="Partition0ProcessUpdate";
        regwidth=0x20;
            field {
                sw = wr;
                onread = rclr;
            } PCUD_Partition_Clock_Update[0:0];
    } Partition0ProcessUpdate @ 0x104;
    reg {
        name="Partition0Status";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } PCS_Partition_Clock_Status[0:0];
    } Partition0Status @ 0x108;
    reg {
        name="Partition0CoreLockstepControl";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LS2_Lockstep_2[2:2];
    } Partition0CoreLockstepControl @ 0x10c;
    reg {
        name="Partition0COFBSet0ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0COFBSet0ClockStatus @ 0x110;
    reg {
        name="Partition0COFBSet1ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0COFBSet1ClockStatus @ 0x114;
    reg {
        name="Partition0COFBSet0ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0COFBSet0ClockEnable @ 0x130;
    reg {
        name="Partition0COFBSet1ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0COFBSet1ClockEnable @ 0x134;
    reg {
        name="Partition0Core0ProcessConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core0ProcessConfiguration @ 0x140;
    reg {
        name="Partition0Core0ProcessUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core0ProcessUpdate @ 0x144;
    reg {
        name="Partition0Core0Status";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } CCS_Coreindex_Clock_Process_Status[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } WFI_WaitForInterruptStatus[31:31];
    } Partition0Core0Status @ 0x148;
    reg {
        name="Partition0Core0Address";
        regwidth=0x20;
            field {
                sw = rw;
            } ADDR_Coreindex_Boot_Address[31:2];
    } Partition0Core0Address @ 0x14c;
    reg {
        name="Partition0Core1ProcessConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core1ProcessConfiguration @ 0x160;
    reg {
        name="Partition0Core1ProcessUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core1ProcessUpdate @ 0x164;
    reg {
        name="Partition0Core1Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core1Status @ 0x168;
    reg {
        name="Partition0Core1Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core1Address @ 0x16c;
    reg {
        name="Partition0Core2Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core2Status @ 0x188;
    reg {
        name="Partition0Core2Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core2Address @ 0x18c;
    reg {
        name="Partition0Core3ProcessConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core3ProcessConfiguration @ 0x1a0;
    reg {
        name="Partition0Core3ProcessUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core3ProcessUpdate @ 0x1a4;
    reg {
        name="Partition0Core3Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core3Status @ 0x1a8;
    reg {
        name="Partition0Core3Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core3Address @ 0x1ac;
    reg {
        name="Partition0Core4ProcessConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core4ProcessConfiguration @ 0x1c0;
    reg {
        name="Partition0Core4ProcessUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core4ProcessUpdate @ 0x1c4;
    reg {
        name="Partition0Core4Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core4Status @ 0x1c8;
    reg {
        name="Partition0Core4Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core4Address @ 0x1cc;
    reg {
        name="Partition0Core5ProcessConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core5ProcessConfiguration @ 0x1e0;
    reg {
        name="Partition0Core5ProcessUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core5ProcessUpdate @ 0x1e4;
    reg {
        name="Partition0Core5Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core5Status @ 0x1e8;
    reg {
        name="Partition0Core5Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition0Core5Address @ 0x1ec;
    reg {
        name="Partition1ProcessConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1ProcessConfiguration @ 0x300;
    reg {
        name="Partition1ProcessUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1ProcessUpdate @ 0x304;
    reg {
        name="Partition1Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1Status @ 0x308;
    reg {
        name="Partition1COFBSet0ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1COFBSet0ClockStatus @ 0x310;
    reg {
        name="Partition1COFBSet1ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1COFBSet1ClockStatus @ 0x314;
    reg {
        name="Partition1COFBSet2ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1COFBSet2ClockStatus @ 0x318;
    reg {
        name="Partition1COFBSet3ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1COFBSet3ClockStatus @ 0x31c;
    reg {
        name="Partition1COFBSet0ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1COFBSet0ClockEnable @ 0x330;
    reg {
        name="Partition1COFBSet1ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1COFBSet1ClockEnable @ 0x334;
    reg {
        name="Partition1COFBSet2ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1COFBSet2ClockEnable @ 0x338;
    reg {
        name="Partition1COFBSet3ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition1COFBSet3ClockEnable @ 0x33c;
    reg {
        name="Partition2ProcessConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2ProcessConfiguration @ 0x500;
    reg {
        name="Partition2ProcessUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2ProcessUpdate @ 0x504;
    reg {
        name="Partition2Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2Status @ 0x508;
    reg {
        name="Partition2COFBSet0ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2COFBSet0ClockStatus @ 0x510;
    reg {
        name="Partition2COFBSet1ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2COFBSet1ClockStatus @ 0x514;
    reg {
        name="Partition2COFBSet2ClockStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2COFBSet2ClockStatus @ 0x518;
    reg {
        name="Partition2COFBSet0ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2COFBSet0ClockEnable @ 0x530;
    reg {
        name="Partition2COFBSet1ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2COFBSet1ClockEnable @ 0x534;
    reg {
        name="Partition2COFBSet2ClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Partition2COFBSet2ClockEnable @ 0x538;
} Registers_addrmap;


};