addrmap ARM_NetworkInterconnect {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Remap";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Remap @ 0x0;
    reg {
        name="Security_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Security_0 @ 0x8;
    reg {
        name="PeripheralID4";
        regwidth=0x20;
            field {
                sw = r;
                reset=8'b100;
            } JEP106_Continuation_code[7:0];
    } PeripheralID4 @ 0x1fd0;
    reg {
        name="PeripheralID5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PeripheralID5 @ 0x1fd4;
    reg {
        name="PeripheralID6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PeripheralID6 @ 0x1fd8;
    reg {
        name="PeripheralID7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PeripheralID7 @ 0x1fdc;
    reg {
        name="PeripheralID0";
        regwidth=0x20;
            field {
                sw = r;
            } Part_Number_7_0[7:0];
    } PeripheralID0 @ 0x1fe0;
    reg {
        name="PeripheralID1";
        regwidth=0x20;
            field {
                sw = r;
                reset=4'b1011;
            } JEP106_Identity[7:4];
            field {
                sw = r;
                reset=4'b100;
            } Part_Number_11_8[3:0];
    } PeripheralID1 @ 0x1fe4;
    reg {
        name="PeripheralID2";
        regwidth=0x20;
            field {
                sw = r;
                reset=4'b100;
            } Part_Revision[7:4];
            field {
                sw = r;
                reset=1'b1;
            } JEP106_Code_flag[3:3];
            field {
                sw = r;
                reset=3'b11;
            } JEP_Identity_6_4[2:0];
    } PeripheralID2 @ 0x1fe8;
    reg {
        name="PeripheralID3";
        regwidth=0x20;
            field {
                desc = "This field has reset value calculated at runtime.";
                sw = r;
            } User_Peripheral_ID[7:0];
    } PeripheralID3 @ 0x1fec;
    reg {
        name="ComponentID0";
        regwidth=0x20;
            field {
                sw = r;
                reset=8'b1101;
            } Preamble[7:0];
    } ComponentID0 @ 0x1ff0;
    reg {
        name="ComponentID1";
        regwidth=0x20;
            field {
                sw = r;
                reset=8'b11110000;
            } Generic_IP_component_class[7:0];
    } ComponentID1 @ 0x1ff4;
    reg {
        name="ComponentID2";
        regwidth=0x20;
            field {
                sw = r;
                reset=8'b101;
            } Preamble[7:0];
    } ComponentID2 @ 0x1ff8;
    reg {
        name="ComponentID3";
        regwidth=0x20;
            field {
                sw = r;
                reset=8'b10110001;
            } Preamble[7:0];
    } ComponentID3 @ 0x1ffc;
    reg {
        name="MasterBusMatrixFunctionalityModification_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MasterBusMatrixFunctionalityModification_0 @ 0x2008;
    reg {
        name="MasterSynchronizationMode_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MasterSynchronizationMode_0 @ 0x2020;
    reg {
        name="MasterBypassMerge_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MasterBypassMerge_0 @ 0x2024;
    reg {
        name="MasterLongBurstModification_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MasterLongBurstModification_0 @ 0x202c;
    reg {
        name="MasterWFIFOTidemark_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MasterWFIFOTidemark_0 @ 0x2040;
    reg {
        name="MasterAHBControl_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MasterAHBControl_0 @ 0x2044;
    reg {
        name="MasterFunctionalityModification_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MasterFunctionalityModification_0 @ 0x2108;
    reg {
        name="SlaveSynchronizationMode_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveSynchronizationMode_0 @ 0x42020;
    reg {
        name="SlaveBypassMerge_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveBypassMerge_0 @ 0x42024;
    reg {
        name="SlaveFunctionalityModificationAHB_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveFunctionalityModificationAHB_0 @ 0x42028;
    reg {
        name="SlaveLongBurst_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveLongBurst_0 @ 0x4202c;
    reg {
        name="SlaveWFIFOTidemark_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveWFIFOTidemark_0 @ 0x42040;
    reg {
        name="SlaveReadChannelQoS_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveReadChannelQoS_0 @ 0x42100;
    reg {
        name="SlaveWriteChanelQoS_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveWriteChanelQoS_0 @ 0x42104;
    reg {
        name="SlaveFunctionalityModification_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveFunctionalityModification_0 @ 0x42108;
    reg {
        name="InternalBusMatrixFunctionalityModification_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalBusMatrixFunctionalityModification_0 @ 0xc2008;
    reg {
        name="InternalSynchronizationMode_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalSynchronizationMode_0 @ 0xc2020;
    reg {
        name="InternalBypassMerge_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalBypassMerge_0 @ 0xc2024;
    reg {
        name="InternalLongBurst_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalLongBurst_0 @ 0xc202c;
    reg {
        name="InternalWFIFOTidemark_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalWFIFOTidemark_0 @ 0xc2040;
    reg {
        name="InternalFunctionalityModification_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalFunctionalityModification_0 @ 0xc2108;
} Registers_addrmap;


};