addrmap Zynq7000_SystemLevelControlRegisters {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="SecureConfigurationLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SecureConfigurationLock @ 0x0;
    reg {
        name="WriteProtectionLock";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } LockKey[15:0];
    } WriteProtectionLock @ 0x4;
    reg {
        name="WriteProtectionUnlock";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } UnlockKey[15:0];
    } WriteProtectionUnlock @ 0x8;
    reg {
        name="WriteProtectionStatus";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } WriteProtected[0:0];
    } WriteProtectionStatus @ 0xc;
    reg {
        name="ArmPLLControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_1[31:0];
    } ArmPLLControl @ 0x100;
    reg {
        name="DDRPLLControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_2[31:0];
    } DDRPLLControl @ 0x104;
    reg {
        name="IOPLLControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_3[31:0];
    } IOPLLControl @ 0x108;
    reg {
        name="PLLStatus";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_4[31:0];
    } PLLStatus @ 0x10c;
    reg {
        name="ArmPLLConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ArmPLLConfiguration @ 0x110;
    reg {
        name="DDRPLLConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRPLLConfiguration @ 0x114;
    reg {
        name="IOPLLConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IOPLLConfiguration @ 0x118;
    reg {
        name="CPUClockControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_5[31:0];
    } CPUClockControl @ 0x120;
    reg {
        name="DDRClockControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_6[31:0];
    } DDRClockControl @ 0x124;
    reg {
        name="DCIClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCIClockControl @ 0x128;
    reg {
        name="AMBAPeripheralClockControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_7[31:0];
    } AMBAPeripheralClockControl @ 0x12c;
    reg {
        name="USB0ULPIClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USB0ULPIClockControl @ 0x130;
    reg {
        name="USB1ULPIClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USB1ULPIClockControl @ 0x134;
    reg {
        name="GigE0RxClockAndRxSignalsSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GigE0RxClockAndRxSignalsSelect @ 0x138;
    reg {
        name="GigE1RxClockAndRxSignalsSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GigE1RxClockAndRxSignalsSelect @ 0x13c;
    reg {
        name="GigE0RefClockControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_8[31:0];
    } GigE0RefClockControl @ 0x140;
    reg {
        name="GigE1RefClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GigE1RefClockControl @ 0x144;
    reg {
        name="SMCRefClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SMCRefClockControl @ 0x148;
    reg {
        name="QuadSPIRefClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } QuadSPIRefClockControl @ 0x14c;
    reg {
        name="SDIORefClockControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_9[31:0];
    } SDIORefClockControl @ 0x150;
    reg {
        name="UARTRefClockControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_10[31:0];
    } UARTRefClockControl @ 0x154;
    reg {
        name="SPIRefClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SPIRefClockControl @ 0x158;
    reg {
        name="CANRefClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CANRefClockControl @ 0x15c;
    reg {
        name="CANMIOClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CANMIOClockControl @ 0x160;
    reg {
        name="SoCDebugClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SoCDebugClockControl @ 0x164;
    reg {
        name="PCAPClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCAPClockControl @ 0x168;
    reg {
        name="CentralInterconnectClockControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CentralInterconnectClockControl @ 0x16c;
    reg {
        name="PLClock0OutputControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock0OutputControl @ 0x170;
    reg {
        name="PLClock0ThrottleControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock0ThrottleControl @ 0x174;
    reg {
        name="PLClock0ThrottleCountControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock0ThrottleCountControl @ 0x178;
    reg {
        name="PLClock0ThrottleStatusRead";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock0ThrottleStatusRead @ 0x17c;
    reg {
        name="PLClock1OutputControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock1OutputControl @ 0x180;
    reg {
        name="PLClock1ThrottleControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock1ThrottleControl @ 0x184;
    reg {
        name="PLClock1ThrottleCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock1ThrottleCount @ 0x188;
    reg {
        name="PLClock1ThrottleStatusControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock1ThrottleStatusControl @ 0x18c;
    reg {
        name="PLClock2OutputControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock2OutputControl @ 0x190;
    reg {
        name="PLClock2ThrottleControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock2ThrottleControl @ 0x194;
    reg {
        name="PLClock2ThrottleCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock2ThrottleCount @ 0x198;
    reg {
        name="PLClock2ThrottleStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock2ThrottleStatus @ 0x19c;
    reg {
        name="PLClock3OutputControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock3OutputControl @ 0x1a0;
    reg {
        name="PLClock3ThrottleControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock3ThrottleControl @ 0x1a4;
    reg {
        name="PLClock3ThrottleCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock3ThrottleCount @ 0x1a8;
    reg {
        name="PLClock3ThrottleStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PLClock3ThrottleStatus @ 0x1ac;
    reg {
        name="CPUClockRatioModeSelect";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } No_name_11[31:0];
    } CPUClockRatioModeSelect @ 0x1c4;
    reg {
        name="PSSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PSSoftwareResetControl @ 0x200;
    reg {
        name="DDRSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRSoftwareResetControl @ 0x204;
    reg {
        name="CentralInterconnectResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CentralInterconnectResetControl @ 0x208;
    reg {
        name="DMACSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMACSoftwareResetControl @ 0x20c;
    reg {
        name="USBSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USBSoftwareResetControl @ 0x210;
    reg {
        name="GigabitEthernetSWResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GigabitEthernetSWResetControl @ 0x214;
    reg {
        name="SDIOSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SDIOSoftwareResetControl @ 0x218;
    reg {
        name="SPISoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SPISoftwareResetControl @ 0x21c;
    reg {
        name="CANSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CANSoftwareResetControl @ 0x220;
    reg {
        name="I2CSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2CSoftwareResetControl @ 0x224;
    reg {
        name="UARTSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UARTSoftwareResetControl @ 0x228;
    reg {
        name="GPIOSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOSoftwareResetControl @ 0x22c;
    reg {
        name="QuadSPISoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } QuadSPISoftwareResetControl @ 0x230;
    reg {
        name="SMCSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SMCSoftwareResetControl @ 0x234;
    reg {
        name="OCMSoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OCMSoftwareResetControl @ 0x238;
    reg {
        name="FPGASoftwareResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FPGASoftwareResetControl @ 0x240;
    reg {
        name="CPUResetAndClockControl";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CPUPeripheralSoftReset[8:8];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } CPU1ClockStop[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } CPU0ClockStop[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } CPU1Reset[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } CPU0Reset[0:0];
    } CPUResetAndClockControl @ 0x244;
    reg {
        name="WatchdogTimerResetControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WatchdogTimerResetControl @ 0x24c;
    reg {
        name="RebootStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RebootStatus @ 0x258;
    reg {
        name="Persistent";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Persistent @ 0x259;
    reg {
        name="BootModeStrappingPins";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BootModeStrappingPins @ 0x25c;
    reg {
        name="APUControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } APUControl @ 0x300;
    reg {
        name="SWDTClockSourceSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SWDTClockSourceSelect @ 0x304;
    reg {
        name="DMACTrustZoneConfig";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMACTrustZoneConfig @ 0x440;
    reg {
        name="DMACTrustZoneConfigForInterrupts";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMACTrustZoneConfigForInterrupts @ 0x444;
    reg {
        name="DMACTrustZoneConfigForPeripherals";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMACTrustZoneConfigForPeripherals @ 0x448;
    reg {
        name="PSIDCODE";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PSIDCODE @ 0x530;
    reg {
        name="DDRUrgentControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRUrgentControl @ 0x600;
    reg {
        name="DDRCalibrationStartTriggers";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRCalibrationStartTriggers @ 0x60c;
    reg {
        name="DDRRefreshStartTriggers";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRRefreshStartTriggers @ 0x614;
    reg {
        name="DDRCommandStoreStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRCommandStoreStatus @ 0x618;
    reg {
        name="DDRUrgentSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRUrgentSelect @ 0x61c;
    reg {
        name="DDRDFIStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRDFIStatus @ 0x620;
    reg {
        name="MIOPin0Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin0Control @ 0x700;
    reg {
        name="MIOPin1Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin1Control @ 0x704;
    reg {
        name="MIOPin2Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin2Control @ 0x708;
    reg {
        name="MIOPin3Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin3Control @ 0x70c;
    reg {
        name="MIOPin4Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin4Control @ 0x710;
    reg {
        name="MIOPin5Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin5Control @ 0x714;
    reg {
        name="MIOPin6Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin6Control @ 0x718;
    reg {
        name="MIOPin7Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin7Control @ 0x71c;
    reg {
        name="MIOPin8Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin8Control @ 0x720;
    reg {
        name="MIOPin9Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin9Control @ 0x724;
    reg {
        name="MIOPin10Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin10Control @ 0x728;
    reg {
        name="MIOPin11Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin11Control @ 0x72c;
    reg {
        name="MIOPin12Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin12Control @ 0x730;
    reg {
        name="MIOPin13Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin13Control @ 0x734;
    reg {
        name="MIOPin14Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin14Control @ 0x738;
    reg {
        name="MIOPin15Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin15Control @ 0x73c;
    reg {
        name="MIOPin16Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin16Control @ 0x740;
    reg {
        name="MIOPin17Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin17Control @ 0x744;
    reg {
        name="MIOPin18Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin18Control @ 0x748;
    reg {
        name="MIOPin19Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin19Control @ 0x74c;
    reg {
        name="MIOPin20Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin20Control @ 0x750;
    reg {
        name="MIOPin21Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin21Control @ 0x754;
    reg {
        name="MIOPin22Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin22Control @ 0x758;
    reg {
        name="MIOPin23Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin23Control @ 0x75c;
    reg {
        name="MIOPin24Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin24Control @ 0x760;
    reg {
        name="MIOPin25Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin25Control @ 0x764;
    reg {
        name="MIOPin26Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin26Control @ 0x768;
    reg {
        name="MIOPin27Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin27Control @ 0x76c;
    reg {
        name="MIOPin28Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin28Control @ 0x770;
    reg {
        name="MIOPin29Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin29Control @ 0x774;
    reg {
        name="MIOPin30Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin30Control @ 0x778;
    reg {
        name="MIOPin31Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin31Control @ 0x77c;
    reg {
        name="MIOPin32Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin32Control @ 0x780;
    reg {
        name="MIOPin33Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin33Control @ 0x784;
    reg {
        name="MIOPin34Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin34Control @ 0x788;
    reg {
        name="MIOPin35Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin35Control @ 0x78c;
    reg {
        name="MIOPin36Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin36Control @ 0x790;
    reg {
        name="MIOPin37Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin37Control @ 0x794;
    reg {
        name="MIOPin38Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin38Control @ 0x798;
    reg {
        name="MIOPin39Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin39Control @ 0x79c;
    reg {
        name="MIOPin40Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin40Control @ 0x7a0;
    reg {
        name="MIOPin41Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin41Control @ 0x7a4;
    reg {
        name="MIOPin42Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin42Control @ 0x7a8;
    reg {
        name="MIOPin43Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin43Control @ 0x7ac;
    reg {
        name="MIOPin44Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin44Control @ 0x7b0;
    reg {
        name="MIOPin45Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin45Control @ 0x7b4;
    reg {
        name="MIOPin46Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin46Control @ 0x7b8;
    reg {
        name="MIOPin47Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin47Control @ 0x7bc;
    reg {
        name="MIOPin48Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin48Control @ 0x7c0;
    reg {
        name="MIOPin49Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin49Control @ 0x7c4;
    reg {
        name="MIOPin50Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin50Control @ 0x7c8;
    reg {
        name="MIOPin51Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin51Control @ 0x7cc;
    reg {
        name="MIOPin52Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin52Control @ 0x7d0;
    reg {
        name="MIOPin53Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPin53Control @ 0x7d4;
    reg {
        name="LoopbackFunctionWithinMIO";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoopbackFunctionWithinMIO @ 0x804;
    reg {
        name="MIOPinTriStateEnables_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPinTriStateEnables_0 @ 0x80c;
    reg {
        name="MIOPinTriStateEnables_1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOPinTriStateEnables_1 @ 0x810;
    reg {
        name="SDIO0WPCDSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SDIO0WPCDSelect @ 0x830;
    reg {
        name="SDIO1WPCDSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SDIO1WPCDSelect @ 0x834;
    reg {
        name="LevelShiftersEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LevelShiftersEnable @ 0x900;
    reg {
        name="OCMAddressMapping";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OCMAddressMapping @ 0x910;
    reg {
        name="Reserved";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Reserved @ 0xa1c;
    reg {
        name="PSIOBufferControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PSIOBufferControl @ 0xb00;
    reg {
        name="MIOGPIOBCMOS1V8Config";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOGPIOBCMOS1V8Config @ 0xb04;
    reg {
        name="MIOGPIOBCMOS2V5Config";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOGPIOBCMOS2V5Config @ 0xb08;
    reg {
        name="MIOGPIOBCMOS3V3Config";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOGPIOBCMOS3V3Config @ 0xb0c;
    reg {
        name="MIOGPIOBHSTLConfig";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOGPIOBHSTLConfig @ 0xb14;
    reg {
        name="MIOGPIOBDriverBiasControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MIOGPIOBDriverBiasControl @ 0xb18;
    reg {
        name="DDRIOBConfigAddress_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBConfigAddress_0 @ 0xb40;
    reg {
        name="DDRIOBConfigAddress_1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBConfigAddress_1 @ 0xb44;
    reg {
        name="DDRIOBConfigForData_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBConfigForData_0 @ 0xb48;
    reg {
        name="DDRIOBConfigForData_1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBConfigForData_1 @ 0xb4c;
    reg {
        name="DDRIOBConfigForDQS_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBConfigForDQS_0 @ 0xb50;
    reg {
        name="DDRIOBConfigForDQS_1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBConfigForDQS_1 @ 0xb54;
    reg {
        name="DDRIOBConfigForClockOutput";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBConfigForClockOutput @ 0xb58;
    reg {
        name="DriveAndSlewControlsForAddressAndCommandPinsOfTheDDRInterface";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriveAndSlewControlsForAddressAndCommandPinsOfTheDDRInterface @ 0xb5c;
    reg {
        name="DriveAndSlewControlsForDQPinsOfTheDDRInterface";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriveAndSlewControlsForDQPinsOfTheDDRInterface @ 0xb60;
    reg {
        name="DriveAndSlewControlsForDQSPinsOfTheDDRInterface";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriveAndSlewControlsForDQSPinsOfTheDDRInterface @ 0xb64;
    reg {
        name="DriveAndSlewControlsForClockPinsOfTheDDRInterface";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DriveAndSlewControlsForClockPinsOfTheDDRInterface @ 0xb68;
    reg {
        name="DDRIOBBufferControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBBufferControl @ 0xb6c;
    reg {
        name="DDRIOBDCIConfig";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBDCIConfig @ 0xb70;
    reg {
        name="DDRIOBufferDCIStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DDRIOBufferDCIStatus @ 0xb74;
} Registers_addrmap;


};