addrmap EFR32xG2_SYSCFG_3 {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Ipversion";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ipversion @ 0x4;
    reg {
        name="If";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } If @ 0x8;
    reg {
        name="Ien";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ien @ 0xc;
    reg {
        name="Chiprevhw";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Chiprevhw @ 0x14;
    reg {
        name="Chiprev";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Chiprev @ 0x18;
    reg {
        name="Instanceid";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Instanceid @ 0x1c;
    reg {
        name="Cfgstcalib";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgstcalib @ 0x20;
    reg {
        name="Cfgsystic";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgsystic @ 0x24;
    reg {
        name="Fpgarevhw";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Fpgarevhw @ 0x2c;
    reg {
        name="Fpgaipothw";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Fpgaipothw @ 0x30;
    reg {
        name="Cfgahbintercnct";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgahbintercnct @ 0x34;
    reg {
        name="Sesysromrm_Rom";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Sesysromrm_Rom @ 0x100;
    reg {
        name="Sepkeromrm_Rom";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Sepkeromrm_Rom @ 0x104;
    reg {
        name="Sesysctrl_Rom";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Sesysctrl_Rom @ 0x108;
    reg {
        name="Sepkectrl_Rom";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Sepkectrl_Rom @ 0x10c;
    reg {
        name="Ctrl_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ctrl_Ram @ 0x200;
    reg {
        name="Dmem0retnctrl_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Dmem0retnctrl_Ram @ 0x208;
    reg {
        name="Ramrm_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ramrm_Ram @ 0x300;
    reg {
        name="Ramwm_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ramwm_Ram @ 0x304;
    reg {
        name="Ramra_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ramra_Ram @ 0x308;
    reg {
        name="Rambiasconf_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Rambiasconf_Ram @ 0x30c;
    reg {
        name="Ramlvtest_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Ramlvtest_Ram @ 0x310;
    reg {
        name="Radioramretnctrl_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Radioramretnctrl_Ram @ 0x400;
    reg {
        name="Radioramfeature_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Radioramfeature_Ram @ 0x404;
    reg {
        name="Radioeccctrl_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Radioeccctrl_Ram @ 0x408;
    reg {
        name="Seqrameccaddr_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Seqrameccaddr_Ram @ 0x410;
    reg {
        name="Frcrameccaddr_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Frcrameccaddr_Ram @ 0x414;
    reg {
        name="Icacheramretnctrl_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Icacheramretnctrl_Ram @ 0x418;
    reg {
        name="Dmem0portmapsel_Ram";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Dmem0portmapsel_Ram @ 0x41c;
    reg {
        name="Data0";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Data0 @ 0x600;
    reg {
        name="Data1";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Data1 @ 0x604;
    reg {
        name="Lockstatus";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Lockstatus @ 0x608;
    reg {
        name="Seswversion";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Seswversion @ 0x60c;
    reg {
        name="Cfgrpuratd0_Cfgdrpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgrpuratd0_Cfgdrpu @ 0x610;
    reg {
        name="Cfgrpuratd2_Cfgdrpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgrpuratd2_Cfgdrpu @ 0x618;
    reg {
        name="Cfgrpuratd4_Cfgdrpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgrpuratd4_Cfgdrpu @ 0x620;
    reg {
        name="Cfgrpuratd6_Cfgdrpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgrpuratd6_Cfgdrpu @ 0x628;
    reg {
        name="Cfgrpuratd8_Cfgdrpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgrpuratd8_Cfgdrpu @ 0x630;
    reg {
        name="Cfgrpuratd12_Cfgdrpu";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } Cfgrpuratd12_Cfgdrpu @ 0x640;
    reg {
        name="Ipversion_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ipversion_SET @ 0x1004;
    reg {
        name="If_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } If_SET @ 0x1008;
    reg {
        name="Ien_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ien_SET @ 0x100c;
    reg {
        name="Chiprevhw_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Chiprevhw_SET @ 0x1014;
    reg {
        name="Chiprev_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Chiprev_SET @ 0x1018;
    reg {
        name="Instanceid_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Instanceid_SET @ 0x101c;
    reg {
        name="Cfgstcalib_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgstcalib_SET @ 0x1020;
    reg {
        name="Cfgsystic_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgsystic_SET @ 0x1024;
    reg {
        name="Fpgarevhw_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Fpgarevhw_SET @ 0x102c;
    reg {
        name="Fpgaipothw_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Fpgaipothw_SET @ 0x1030;
    reg {
        name="Cfgahbintercnct_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgahbintercnct_SET @ 0x1034;
    reg {
        name="Sesysromrm_Rom_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sesysromrm_Rom_SET @ 0x1100;
    reg {
        name="Sepkeromrm_Rom_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sepkeromrm_Rom_SET @ 0x1104;
    reg {
        name="Sesysctrl_Rom_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sesysctrl_Rom_SET @ 0x1108;
    reg {
        name="Sepkectrl_Rom_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sepkectrl_Rom_SET @ 0x110c;
    reg {
        name="Ctrl_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ctrl_Ram_SET @ 0x1200;
    reg {
        name="Dmem0retnctrl_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dmem0retnctrl_Ram_SET @ 0x1208;
    reg {
        name="Ramrm_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramrm_Ram_SET @ 0x1300;
    reg {
        name="Ramwm_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramwm_Ram_SET @ 0x1304;
    reg {
        name="Ramra_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramra_Ram_SET @ 0x1308;
    reg {
        name="Rambiasconf_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rambiasconf_Ram_SET @ 0x130c;
    reg {
        name="Ramlvtest_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramlvtest_Ram_SET @ 0x1310;
    reg {
        name="Radioramretnctrl_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioramretnctrl_Ram_SET @ 0x1400;
    reg {
        name="Radioramfeature_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioramfeature_Ram_SET @ 0x1404;
    reg {
        name="Radioeccctrl_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioeccctrl_Ram_SET @ 0x1408;
    reg {
        name="Seqrameccaddr_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seqrameccaddr_Ram_SET @ 0x1410;
    reg {
        name="Frcrameccaddr_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Frcrameccaddr_Ram_SET @ 0x1414;
    reg {
        name="Icacheramretnctrl_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Icacheramretnctrl_Ram_SET @ 0x1418;
    reg {
        name="Dmem0portmapsel_Ram_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dmem0portmapsel_Ram_SET @ 0x141c;
    reg {
        name="Data0_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data0_SET @ 0x1600;
    reg {
        name="Data1_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data1_SET @ 0x1604;
    reg {
        name="Lockstatus_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lockstatus_SET @ 0x1608;
    reg {
        name="Seswversion_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seswversion_SET @ 0x160c;
    reg {
        name="Cfgrpuratd0_Cfgdrpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd0_Cfgdrpu_SET @ 0x1610;
    reg {
        name="Cfgrpuratd2_Cfgdrpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd2_Cfgdrpu_SET @ 0x1618;
    reg {
        name="Cfgrpuratd4_Cfgdrpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd4_Cfgdrpu_SET @ 0x1620;
    reg {
        name="Cfgrpuratd6_Cfgdrpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd6_Cfgdrpu_SET @ 0x1628;
    reg {
        name="Cfgrpuratd8_Cfgdrpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd8_Cfgdrpu_SET @ 0x1630;
    reg {
        name="Cfgrpuratd12_Cfgdrpu_SET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd12_Cfgdrpu_SET @ 0x1640;
    reg {
        name="Ipversion_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ipversion_CLR @ 0x2004;
    reg {
        name="If_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } If_CLR @ 0x2008;
    reg {
        name="Ien_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ien_CLR @ 0x200c;
    reg {
        name="Chiprevhw_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Chiprevhw_CLR @ 0x2014;
    reg {
        name="Chiprev_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Chiprev_CLR @ 0x2018;
    reg {
        name="Instanceid_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Instanceid_CLR @ 0x201c;
    reg {
        name="Cfgstcalib_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgstcalib_CLR @ 0x2020;
    reg {
        name="Cfgsystic_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgsystic_CLR @ 0x2024;
    reg {
        name="Fpgarevhw_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Fpgarevhw_CLR @ 0x202c;
    reg {
        name="Fpgaipothw_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Fpgaipothw_CLR @ 0x2030;
    reg {
        name="Cfgahbintercnct_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgahbintercnct_CLR @ 0x2034;
    reg {
        name="Sesysromrm_Rom_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sesysromrm_Rom_CLR @ 0x2100;
    reg {
        name="Sepkeromrm_Rom_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sepkeromrm_Rom_CLR @ 0x2104;
    reg {
        name="Sesysctrl_Rom_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sesysctrl_Rom_CLR @ 0x2108;
    reg {
        name="Sepkectrl_Rom_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sepkectrl_Rom_CLR @ 0x210c;
    reg {
        name="Ctrl_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ctrl_Ram_CLR @ 0x2200;
    reg {
        name="Dmem0retnctrl_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dmem0retnctrl_Ram_CLR @ 0x2208;
    reg {
        name="Ramrm_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramrm_Ram_CLR @ 0x2300;
    reg {
        name="Ramwm_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramwm_Ram_CLR @ 0x2304;
    reg {
        name="Ramra_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramra_Ram_CLR @ 0x2308;
    reg {
        name="Rambiasconf_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rambiasconf_Ram_CLR @ 0x230c;
    reg {
        name="Ramlvtest_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramlvtest_Ram_CLR @ 0x2310;
    reg {
        name="Radioramretnctrl_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioramretnctrl_Ram_CLR @ 0x2400;
    reg {
        name="Radioramfeature_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioramfeature_Ram_CLR @ 0x2404;
    reg {
        name="Radioeccctrl_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioeccctrl_Ram_CLR @ 0x2408;
    reg {
        name="Seqrameccaddr_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seqrameccaddr_Ram_CLR @ 0x2410;
    reg {
        name="Frcrameccaddr_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Frcrameccaddr_Ram_CLR @ 0x2414;
    reg {
        name="Icacheramretnctrl_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Icacheramretnctrl_Ram_CLR @ 0x2418;
    reg {
        name="Dmem0portmapsel_Ram_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dmem0portmapsel_Ram_CLR @ 0x241c;
    reg {
        name="Data0_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data0_CLR @ 0x2600;
    reg {
        name="Data1_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data1_CLR @ 0x2604;
    reg {
        name="Lockstatus_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lockstatus_CLR @ 0x2608;
    reg {
        name="Seswversion_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seswversion_CLR @ 0x260c;
    reg {
        name="Cfgrpuratd0_Cfgdrpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd0_Cfgdrpu_CLR @ 0x2610;
    reg {
        name="Cfgrpuratd2_Cfgdrpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd2_Cfgdrpu_CLR @ 0x2618;
    reg {
        name="Cfgrpuratd4_Cfgdrpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd4_Cfgdrpu_CLR @ 0x2620;
    reg {
        name="Cfgrpuratd6_Cfgdrpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd6_Cfgdrpu_CLR @ 0x2628;
    reg {
        name="Cfgrpuratd8_Cfgdrpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd8_Cfgdrpu_CLR @ 0x2630;
    reg {
        name="Cfgrpuratd12_Cfgdrpu_CLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd12_Cfgdrpu_CLR @ 0x2640;
    reg {
        name="Ipversion_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ipversion_TGL @ 0x3004;
    reg {
        name="If_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } If_TGL @ 0x3008;
    reg {
        name="Ien_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ien_TGL @ 0x300c;
    reg {
        name="Chiprevhw_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Chiprevhw_TGL @ 0x3014;
    reg {
        name="Chiprev_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Chiprev_TGL @ 0x3018;
    reg {
        name="Instanceid_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Instanceid_TGL @ 0x301c;
    reg {
        name="Cfgstcalib_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgstcalib_TGL @ 0x3020;
    reg {
        name="Cfgsystic_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgsystic_TGL @ 0x3024;
    reg {
        name="Fpgarevhw_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Fpgarevhw_TGL @ 0x302c;
    reg {
        name="Fpgaipothw_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Fpgaipothw_TGL @ 0x3030;
    reg {
        name="Cfgahbintercnct_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgahbintercnct_TGL @ 0x3034;
    reg {
        name="Sesysromrm_Rom_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sesysromrm_Rom_TGL @ 0x3100;
    reg {
        name="Sepkeromrm_Rom_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sepkeromrm_Rom_TGL @ 0x3104;
    reg {
        name="Sesysctrl_Rom_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sesysctrl_Rom_TGL @ 0x3108;
    reg {
        name="Sepkectrl_Rom_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Sepkectrl_Rom_TGL @ 0x310c;
    reg {
        name="Ctrl_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ctrl_Ram_TGL @ 0x3200;
    reg {
        name="Dmem0retnctrl_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dmem0retnctrl_Ram_TGL @ 0x3208;
    reg {
        name="Ramrm_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramrm_Ram_TGL @ 0x3300;
    reg {
        name="Ramwm_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramwm_Ram_TGL @ 0x3304;
    reg {
        name="Ramra_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramra_Ram_TGL @ 0x3308;
    reg {
        name="Rambiasconf_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rambiasconf_Ram_TGL @ 0x330c;
    reg {
        name="Ramlvtest_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Ramlvtest_Ram_TGL @ 0x3310;
    reg {
        name="Radioramretnctrl_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioramretnctrl_Ram_TGL @ 0x3400;
    reg {
        name="Radioramfeature_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioramfeature_Ram_TGL @ 0x3404;
    reg {
        name="Radioeccctrl_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Radioeccctrl_Ram_TGL @ 0x3408;
    reg {
        name="Seqrameccaddr_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seqrameccaddr_Ram_TGL @ 0x3410;
    reg {
        name="Frcrameccaddr_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Frcrameccaddr_Ram_TGL @ 0x3414;
    reg {
        name="Icacheramretnctrl_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Icacheramretnctrl_Ram_TGL @ 0x3418;
    reg {
        name="Dmem0portmapsel_Ram_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Dmem0portmapsel_Ram_TGL @ 0x341c;
    reg {
        name="Data0_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data0_TGL @ 0x3600;
    reg {
        name="Data1_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data1_TGL @ 0x3604;
    reg {
        name="Lockstatus_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lockstatus_TGL @ 0x3608;
    reg {
        name="Seswversion_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Seswversion_TGL @ 0x360c;
    reg {
        name="Cfgrpuratd0_Cfgdrpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd0_Cfgdrpu_TGL @ 0x3610;
    reg {
        name="Cfgrpuratd2_Cfgdrpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd2_Cfgdrpu_TGL @ 0x3618;
    reg {
        name="Cfgrpuratd4_Cfgdrpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd4_Cfgdrpu_TGL @ 0x3620;
    reg {
        name="Cfgrpuratd6_Cfgdrpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd6_Cfgdrpu_TGL @ 0x3628;
    reg {
        name="Cfgrpuratd8_Cfgdrpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd8_Cfgdrpu_TGL @ 0x3630;
    reg {
        name="Cfgrpuratd12_Cfgdrpu_TGL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Cfgrpuratd12_Cfgdrpu_TGL @ 0x3640;
} Registers_addrmap;


};