addrmap XilinxGPIOPS {

/* Some conversion errors detected, this might mean that the peripheral's registers structure in this file is incomplete.
 * Please refer to logs and comments in the file for more information.
 * 
 * Register "MaskableOutputData0Hi" overlaps another register at the same offset (0x4) and will be skipped, as it is illegal in SystemRDL.
 * Register "MaskableOutputData1Low" overlaps another register at the same offset (0x8) and will be skipped, as it is illegal in SystemRDL.
 * Register "MaskableOutputData1Hi" overlaps another register at the same offset (0xc) and will be skipped, as it is illegal in SystemRDL.
 * Register "MaskableOutputData2Low" overlaps another register at the same offset (0x10) and will be skipped, as it is illegal in SystemRDL.
 * Register "MaskableOutputData2Hi" overlaps another register at the same offset (0x14) and will be skipped, as it is illegal in SystemRDL.
 * Register "MaskableOutputData3Low" overlaps another register at the same offset (0x18) and will be skipped, as it is illegal in SystemRDL.
 * Register "MaskableOutputData3Hi" overlaps another register at the same offset (0x1c) and will be skipped, as it is illegal in SystemRDL.
 */

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="MaskableOutputData0Low";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MaskableOutputData0Low @ 0x0;
    reg {
        name="DirectionMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectionMode @ 0x4;
    /* Conversion error: Register "MaskableOutputData0Hi" overlaps another register at the same offset (0x4) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="MaskableOutputData0Hi";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } MaskableOutputData0Hi @ 0x4;
    */
    reg {
        name="OutputEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OutputEnable @ 0x8;
    /* Conversion error: Register "MaskableOutputData1Low" overlaps another register at the same offset (0x8) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="MaskableOutputData1Low";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } MaskableOutputData1Low @ 0x8;
    */
    reg {
        name="InterruptMaskStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptMaskStatus @ 0xc;
    /* Conversion error: Register "MaskableOutputData1Hi" overlaps another register at the same offset (0xc) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="MaskableOutputData1Hi";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } MaskableOutputData1Hi @ 0xc;
    */
    reg {
        name="InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable @ 0x10;
    /* Conversion error: Register "MaskableOutputData2Low" overlaps another register at the same offset (0x10) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="MaskableOutputData2Low";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } MaskableOutputData2Low @ 0x10;
    */
    reg {
        name="InterruptDisable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptDisable @ 0x14;
    /* Conversion error: Register "MaskableOutputData2Hi" overlaps another register at the same offset (0x14) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="MaskableOutputData2Hi";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } MaskableOutputData2Hi @ 0x14;
    */
    reg {
        name="InterruptPolarity";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptPolarity @ 0x18;
    /* Conversion error: Register "MaskableOutputData3Low" overlaps another register at the same offset (0x18) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="MaskableOutputData3Low";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } MaskableOutputData3Low @ 0x18;
    */
    reg {
        name="InterruptAnyEdgeSensitive";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptAnyEdgeSensitive @ 0x1c;
    /* Conversion error: Register "MaskableOutputData3Hi" overlaps another register at the same offset (0x1c) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="MaskableOutputData3Hi";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } MaskableOutputData3Hi @ 0x1c;
    */
    reg {
        name="OutputData0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OutputData0 @ 0x40;
    reg {
        name="OutputData1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OutputData1 @ 0x44;
    reg {
        name="OutputData2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OutputData2 @ 0x48;
    reg {
        name="OutputData3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OutputData3 @ 0x4c;
    reg {
        name="InputData0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InputData0 @ 0x60;
    reg {
        name="InputData1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InputData1 @ 0x64;
    reg {
        name="InputData2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InputData2 @ 0x68;
    reg {
        name="InputData3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InputData3 @ 0x6c;
} RegistersOffsets_addrmap;


};