addrmap CC2520 {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="FrameFiltering0";
        regwidth=0x8;
            field {
                sw = rw;
            } FCF_RESERVED_MASK[6:4];
            field {
                sw = rw;
                reset=2'b11;
            } MAX_FRAME_VERSION[3:2];
            field {
                sw = rw;
            } PAN_COORDINATOR[1:1];
            field {
                sw = rw;
                reset=1'b1;
            } FRAME_FILTER_EN[0:0];
    } FrameFiltering0 @ 0x0;
    reg {
        name="FrameFiltering1";
        regwidth=0x8;
            field {
                sw = rw;
            } ACCEPT_FT_4TO7_RESERVED[7:7];
            field {
                sw = rw;
                reset=1'b1;
            } ACCEPT_FT_3_MAC_CMD[6:6];
            field {
                sw = rw;
                reset=1'b1;
            } ACCEPT_FT_2_ACK[5:5];
            field {
                sw = rw;
                reset=1'b1;
            } ACCEPT_FT_1_DATA[4:4];
            field {
                sw = rw;
                reset=1'b1;
            } ACCEPT_FT_0_BEACON[3:3];
            field {
                sw = rw;
            } MODIFY_FT_FILTER[2:1];
    } FrameFiltering1 @ 0x1;
    reg {
        name="SourceMatching";
        regwidth=0x8;
            field {
                sw = rw;
                reset=1'b1;
            } PEND_DATAREQ_ONLY[2:2];
            field {
                sw = rw;
                reset=1'b1;
            } AUTOPEND[1:1];
            field {
                sw = rw;
                reset=1'b1;
            } SRC_MATCH_EN[0:0];
    } SourceMatching @ 0x2;
    reg {
        name="ShortAddressMatchingEnabled0";
        regwidth=0x8;
            field {
                sw = rw;
            } SHORT_ADDR_EN7_0[7:0];
    } ShortAddressMatchingEnabled0 @ 0x4;
    reg {
        name="ShortAddressMatchingEnabled1";
        regwidth=0x8;
            field {
                sw = rw;
            } SHORT_ADDR_EN15_8[7:0];
    } ShortAddressMatchingEnabled1 @ 0x5;
    reg {
        name="ShortAddressMatchingEnabled2";
        regwidth=0x8;
            field {
                sw = rw;
            } SHORT_ADDR_EN23_16[7:0];
    } ShortAddressMatchingEnabled2 @ 0x6;
    reg {
        name="ExtendedAddressMatchingEnabled0";
        regwidth=0x8;
            field {
                sw = rw;
            } EXT_ADDR_EN7_0[7:0];
    } ExtendedAddressMatchingEnabled0 @ 0x8;
    reg {
        name="ExtendedAddressMatchingEnabled1";
        regwidth=0x8;
            field {
                sw = rw;
            } EXT_ADDR_EN15_8[7:0];
    } ExtendedAddressMatchingEnabled1 @ 0x9;
    reg {
        name="ExtendedAddressMatchingEnabled2";
        regwidth=0x8;
            field {
                sw = rw;
            } EXT_ADDR_EN23_16[7:0];
    } ExtendedAddressMatchingEnabled2 @ 0xa;
    reg {
        name="FrameControl0";
        regwidth=0x8;
            field {
                sw = rw;
            } APPEND_DATA_MODE[7:7];
            field {
                sw = rw;
                reset=1'b1;
            } AUTOCRC[6:6];
            field {
                sw = rw;
            } AUTOACK[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ENERGY_SCAN[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RX_MODE[3:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TX_MODE[1:0];
    } FrameControl0 @ 0xc;
    reg {
        name="FrameControl1";
        regwidth=0x8;
            field {
                sw = rw;
            } PENDING_OR[2:2];
            field {
                sw = rw;
            } IGNORE_TX_UNDERF[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } SET_RXENMASK_ON_TX[0:0];
    } FrameControl1 @ 0xd;
    reg {
        name="RXENABLE0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RXENABLE0 @ 0xe;
    reg {
        name="RXENABLE1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RXENABLE1 @ 0xf;
    reg {
        name="PendingExceptionFlags0";
        regwidth=0x8;
            field {
                sw = rw;
                onwrite = wzc;
            } EXCFLAG0[7:0];
    } PendingExceptionFlags0 @ 0x10;
    reg {
        name="PendingExceptionFlags1";
        regwidth=0x8;
            field {
                sw = rw;
                onwrite = wzc;
            } EXCFLAG1[7:0];
    } PendingExceptionFlags1 @ 0x11;
    reg {
        name="PendingExceptionFlags2";
        regwidth=0x8;
            field {
                sw = rw;
                onwrite = wzc;
            } EXCFLAG2[7:0];
    } PendingExceptionFlags2 @ 0x12;
    reg {
        name="ExceptionMaskA0";
        regwidth=0x8;
            field {
                sw = rw;
            } EXCMASKA0[7:0];
    } ExceptionMaskA0 @ 0x14;
    reg {
        name="ExceptionMaskA1";
        regwidth=0x8;
            field {
                sw = rw;
            } EXCMASKA1[7:0];
    } ExceptionMaskA1 @ 0x15;
    reg {
        name="ExceptionMaskA2";
        regwidth=0x8;
            field {
                sw = rw;
            } EXCMASKA2[7:0];
    } ExceptionMaskA2 @ 0x16;
    reg {
        name="ExceptionMaskB0";
        regwidth=0x8;
            field {
                sw = rw;
            } EXCMASKB0[7:0];
    } ExceptionMaskB0 @ 0x18;
    reg {
        name="ExceptionMaskB1";
        regwidth=0x8;
            field {
                sw = rw;
            } EXCMASKB1[7:0];
    } ExceptionMaskB1 @ 0x19;
    reg {
        name="ExceptionMaskB2";
        regwidth=0x8;
            field {
                sw = rw;
            } EXCMASKB2[7:0];
    } ExceptionMaskB2 @ 0x1a;
    reg {
        name="EXCBINDX0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EXCBINDX0 @ 0x1c;
    reg {
        name="EXCBINDX1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EXCBINDX1 @ 0x1d;
    reg {
        name="EXCBINDY0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EXCBINDY0 @ 0x1e;
    reg {
        name="EXCBINDY1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EXCBINDY1 @ 0x1f;
    reg {
        name="GPIOCTRL0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOCTRL0 @ 0x20;
    reg {
        name="GPIOCTRL1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOCTRL1 @ 0x21;
    reg {
        name="GPIOCTRL2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOCTRL2 @ 0x22;
    reg {
        name="GPIOCTRL3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOCTRL3 @ 0x23;
    reg {
        name="GPIOCTRL4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOCTRL4 @ 0x24;
    reg {
        name="GPIOCTRL5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOCTRL5 @ 0x25;
    reg {
        name="GPIOPOLARITY";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOPOLARITY @ 0x26;
    reg {
        name="GPIOCTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOCTRL @ 0x28;
    reg {
        name="DPUCON";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DPUCON @ 0x2a;
    reg {
        name="DPUSTAT";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DPUSTAT @ 0x2c;
    reg {
        name="FrequencyControl";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
                reset=7'b1011;
            } FREQ[6:0];
    } FrequencyControl @ 0x2e;
    reg {
        name="FREQTUNE";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FREQTUNE @ 0x2f;
    reg {
        name="TxPower";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b110;
            } PA_POWER[7:0];
    } TxPower @ 0x30;
    reg {
        name="TXCTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TXCTRL @ 0x31;
    reg {
        name="FSMSTAT0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSMSTAT0 @ 0x32;
    reg {
        name="FSMSTAT1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSMSTAT1 @ 0x33;
    reg {
        name="FifoPControl";
        regwidth=0x8;
            field {
                sw = rw;
                reset=7'b1000000;
            } FIFOP_THR[6:0];
    } FifoPControl @ 0x34;
    reg {
        name="FSMCTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSMCTRL @ 0x35;
    reg {
        name="CCAThreshold";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b11100000;
            } CCA_THR[7:0];
    } CCAThreshold @ 0x36;
    reg {
        name="CCACTRL1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CCACTRL1 @ 0x37;
    reg {
        name="RSSI";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RSSI @ 0x38;
    reg {
        name="RSSIValidStatus";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RSSISTAT[0:0];
    } RSSIValidStatus @ 0x39;
    reg {
        name="RxFirstByte";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RXFIRST[7:0];
    } RxFirstByte @ 0x3c;
    reg {
        name="RxFifoCount";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RXFIFOCNT[7:0];
    } RxFifoCount @ 0x3e;
    reg {
        name="TxFifoCount";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } TXFIFOCNT[7:0];
    } TxFifoCount @ 0x3f;
    reg {
        name="ChipId";
        regwidth=0x8;
            field {
                sw = r;
                reset=8'b10000100;
            } CHIPID[7:0];
    } ChipId @ 0x40;
    reg {
        name="Version";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Version @ 0x42;
    reg {
        name="ExternalClock";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } EXTCLOCK_EN[5:5];
            field {
                sw = rw;
            } EXT_FREQ[4:0];
    } ExternalClock @ 0x44;
    reg {
        name="ModemControl0";
        regwidth=0x8;
            field {
                sw = rw;
                reset=2'b1;
            } DEM_NUM_ZEROS[7:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEMOD_AVG_MODE[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=4'b10;
            } PREAMBLE_LENGTH[4:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } TX_FILTER[0:0];
    } ModemControl0 @ 0x46;
    reg {
        name="ModemControl1";
        regwidth=0x8;
            field {
                sw = rw;
                reset=1'b1;
            } CORR_THR_SFD[5:5];
            field {
                sw = rw;
                reset=4'b1110;
            } CORR_THR[3:0];
    } ModemControl1 @ 0x47;
    reg {
        name="FREQEST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FREQEST @ 0x48;
    reg {
        name="RxModuleTuning";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b101001;
            } No_name_1[7:0];
    } RxModuleTuning @ 0x4a;
    reg {
        name="SynthesizerTuning";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b1010101;
            } No_name_2[7:0];
    } SynthesizerTuning @ 0x4c;
    reg {
        name="FSCAL0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSCAL0 @ 0x4e;
    reg {
        name="VCOTuning1";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b101001;
            } No_name_3[7:0];
    } VCOTuning1 @ 0x4f;
    reg {
        name="FSCAL2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSCAL2 @ 0x50;
    reg {
        name="FSCAL3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSCAL3 @ 0x51;
    reg {
        name="AGCCTRL0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AGCCTRL0 @ 0x52;
    reg {
        name="AGCTuning1";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b1110;
            } No_name_4[7:0];
    } AGCTuning1 @ 0x53;
    reg {
        name="AGCCTRL2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AGCCTRL2 @ 0x54;
    reg {
        name="AGCCTRL3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AGCCTRL3 @ 0x55;
    reg {
        name="ADCTest0";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b1100110;
            } No_name_5[7:0];
    } ADCTest0 @ 0x56;
    reg {
        name="ADCTest1";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b1010;
            } No_name_6[7:0];
    } ADCTest1 @ 0x57;
    reg {
        name="ADCTest2";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b101;
            } No_name_7[7:0];
    } ADCTest2 @ 0x58;
    reg {
        name="MDMTEST0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MDMTEST0 @ 0x5a;
    reg {
        name="MDMTEST1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MDMTEST1 @ 0x5b;
    reg {
        name="DACTEST0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DACTEST0 @ 0x5c;
    reg {
        name="DACTEST1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DACTEST1 @ 0x5d;
    reg {
        name="ATEST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATEST @ 0x5e;
    reg {
        name="DACTEST2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DACTEST2 @ 0x5f;
    reg {
        name="PTEST0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PTEST0 @ 0x60;
    reg {
        name="PTEST1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PTEST1 @ 0x61;
    reg {
        name="RESERVED";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED @ 0x62;
    reg {
        name="DPUBIST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DPUBIST @ 0x7a;
    reg {
        name="ACTBIST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ACTBIST @ 0x7c;
    reg {
        name="RAMBIST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RAMBIST @ 0x7e;
} Registers_addrmap;


};