addrmap MPFS_PCIe {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="SourceAddressLowAndParameters";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SourceAddressLowAndParameters @ 0x0;
    reg {
        name="SourceAddressHigh";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SourceAddressHigh @ 0x4;
    reg {
        name="DestinationAddressLow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DestinationAddressLow @ 0x8;
    reg {
        name="DestinationAddressHigh";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DestinationAddressHigh @ 0xc;
    reg {
        name="TranslationParametersLow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TranslationParametersLow @ 0x10;
    reg {
        name="Reserved";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Reserved @ 0x14;
    reg {
        name="TranslationMaskLow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TranslationMaskLow @ 0x18;
    reg {
        name="TranslationMaskHigh";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TranslationMaskHigh @ 0x1c;
} AddressTranslationRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="BRIDGE_VER";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BRIDGE_VER @ 0x0;
    reg {
        name="BRIDGE_BUS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BRIDGE_BUS @ 0x4;
    reg {
        name="BRIDGE_IMPL_IF";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BRIDGE_IMPL_IF @ 0x8;
    reg {
        name="PCIE_IF_CONF";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_IF_CONF @ 0x10;
    reg {
        name="PCIE_BASIC_CONF";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BASIC_CONF @ 0x14;
    reg {
        name="PCIE_BASIC_STATUS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BASIC_STATUS @ 0x18;
    reg {
        name="AXI_SLVL_CONF";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AXI_SLVL_CONF @ 0x24;
    reg {
        name="AXI_MST0_CONF";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AXI_MST0_CONF @ 0x30;
    reg {
        name="AXI_SLV0_CONF";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AXI_SLV0_CONF @ 0x34;
    reg {
        name="GEN_SETTINGS";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } ROOT_PORT_ENABLE[0:0];
    } GEN_SETTINGS @ 0x80;
    reg {
        name="PCIE_CFGCTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_CFGCTRL @ 0x84;
    reg {
        name="PCIE_PIPE_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PIPE_DW0 @ 0x88;
    reg {
        name="PCIE_PIPE_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PIPE_DW1 @ 0x8c;
    reg {
        name="PCIE_VC_CRED_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_VC_CRED_DW0 @ 0x90;
    reg {
        name="PCIE_VC_CRED_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_VC_CRED_DW1 @ 0x94;
    reg {
        name="PCIE_PCI_IDS_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_IDS_DW0 @ 0x98;
    reg {
        name="PCIE_PCI_IDS_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_IDS_DW1 @ 0x9c;
    reg {
        name="PCIE_PCI_IDS_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_IDS_DW2 @ 0xa0;
    reg {
        name="PCIE_PCI_LPM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_LPM @ 0xa4;
    reg {
        name="PCIE_PCI_IRQ_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_IRQ_DW0 @ 0xa8;
    reg {
        name="PCIE_PCI_IRQ_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_IRQ_DW1 @ 0xac;
    reg {
        name="PCIE_PCI_IRQ_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_IRQ_DW2 @ 0xb0;
    reg {
        name="PCIE_PCI_IOV_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_IOV_DW0 @ 0xb4;
    reg {
        name="PCIE_PCI_IOV_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PCI_IOV_DW1 @ 0xb8;
    reg {
        name="PCIE_PEX_DEV";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_DEV @ 0xc0;
    reg {
        name="PCIE_PEX_DEV2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_DEV2 @ 0xc4;
    reg {
        name="PCIE_PEX_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_LINK @ 0xc8;
    reg {
        name="PCIE_PEX_SLOT";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_SLOT @ 0xcc;
    reg {
        name="PCIE_PEX_ROOT_VC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_ROOT_VC @ 0xd0;
    reg {
        name="PCIE_PEX_SPC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_SPC @ 0xd4;
    reg {
        name="PCIE_PEX_SPC2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_SPC2 @ 0xd8;
    reg {
        name="PCIE_PEX_NFTS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_NFTS @ 0xdc;
    reg {
        name="PCIE_PEX_L1SS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_L1SS @ 0xe0;
    reg {
        name="PCIE_BAR_01_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_01_DW0 @ 0xe4;
    reg {
        name="PCIE_BAR_01_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_01_DW1 @ 0xe8;
    reg {
        name="PCIE_BAR_23_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_23_DW0 @ 0xec;
    reg {
        name="PCIE_BAR_23_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_23_DW1 @ 0xf0;
    reg {
        name="PCIE_BAR_45_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_45_DW0 @ 0xf4;
    reg {
        name="PCIE_BAR_45_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_45_DW1 @ 0xf8;
    reg {
        name="PCIE_BAR_WIN";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_WIN @ 0xfc;
    reg {
        name="PCIE_EQ_PRESET_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_EQ_PRESET_DW0 @ 0x100;
    reg {
        name="PCIE_EQ_PRESET_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_EQ_PRESET_DW1 @ 0x104;
    reg {
        name="PCIE_EQ_PRESET_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_EQ_PRESET_DW2 @ 0x108;
    reg {
        name="PCIE_EQ_PRESET_DW3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_EQ_PRESET_DW3 @ 0x10c;
    reg {
        name="PCIE_EQ_PRESET_DW4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_EQ_PRESET_DW4 @ 0x110;
    reg {
        name="PCIE_EQ_PRESET_DW5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_EQ_PRESET_DW5 @ 0x114;
    reg {
        name="PCIE_EQ_PRESET_DW6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_EQ_PRESET_DW6 @ 0x118;
    reg {
        name="PCIE_EQ_PRESET_DW7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_EQ_PRESET_DW7 @ 0x11c;
    reg {
        name="PCIE_SRIOV_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_SRIOV_DW0 @ 0x120;
    reg {
        name="PCIE_SRIOV_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_SRIOV_DW1 @ 0x124;
    reg {
        name="PCIE_SRIOV_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_SRIOV_DW2 @ 0x128;
    reg {
        name="PCIE_SRIOV_DW3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_SRIOV_DW3 @ 0x12c;
    reg {
        name="PCIE_SRIOV_DW4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_SRIOV_DW4 @ 0x130;
    reg {
        name="PCIE_SRIOV_DW5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_SRIOV_DW5 @ 0x134;
    reg {
        name="PCIE_SRIOV_DW6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_SRIOV_DW6 @ 0x138;
    reg {
        name="PCIE_SRIOV_DW7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_SRIOV_DW7 @ 0x13c;
    reg {
        name="PCIE_CFGNUM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_CFGNUM @ 0x140;
    reg {
        name="PM_CONF_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PM_CONF_DW0 @ 0x174;
    reg {
        name="PM_CONF_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PM_CONF_DW1 @ 0x178;
    reg {
        name="PM_CONF_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PM_CONF_DW2 @ 0x17c;
    reg {
        name="IMASK_LOCAL";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_DMA_END_ENGINE_0[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_DMA_END_ENGINE_1[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_DMA_ERROR_ENGINE_0[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_DMA_ERROR_ENGINE_1[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_A_ATR_EVT_POST_ERR[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_A_ATR_EVT_FETCH_ERR[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_A_ATR_EVT_DISCARD_ERR[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_A_ATR_EVT_DOORBELL[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_P_ATR_EVT_POST_ERR[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_P_ATR_EVT_FETCH_ERR[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_P_ATR_EVT_DISCARD_ERR[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_P_ATR_EVT_DOORBELL[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_PM_MSI_INT_INTA[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_PM_MSI_INT_INTB[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_PM_MSI_INT_INTC[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_PM_MSI_INT_INTD[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_PM_MSI_INT_MSI[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_PM_MSI_INT_AER_EVT[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_PM_MSI_INT_EVENTS[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IMASK_PM_MSI_INT_SYS_ERR[31:31];
    } IMASK_LOCAL @ 0x180;
    reg {
        name="ISTATUS_LOCAL";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_END_ENGINE_0[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_END_ENGINE_1[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_ERROR_ENGINE_0[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_ERROR_ENGINE_1[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } A_ATR_EVT_POST_ERR[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } A_ATR_EVT_FETCH_ERR[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } A_ATR_EVT_DISCARD_ERR[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } A_ATR_EVT_DOORBELL[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } P_ATR_EVT_POST_ERR[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } P_ATR_EVT_FETCH_ERR[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } P_ATR_EVT_DISCARD_ERR[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } P_ATR_EVT_DOORBELL[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PM_MSI_INT_INTA[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PM_MSI_INT_INTB[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PM_MSI_INT_INTC[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PM_MSI_INT_INTD[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PM_MSI_INT_MSI[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PM_MSI_INT_AER_EVT[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PM_MSI_INT_EVENTS[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PM_MSI_INT_SYS_ERR[31:31];
    } ISTATUS_LOCAL @ 0x184;
    reg {
        name="IMASK_HOST";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INT_MASK_HOST[31:0];
    } IMASK_HOST @ 0x188;
    reg {
        name="ISTATUS_HOST";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_END[7:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_ERROR[9:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } A_ATR_EVT[19:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } P_ATR_EVT[23:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INT_REQUEST[31:24];
    } ISTATUS_HOST @ 0x18c;
    reg {
        name="IMSI_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IMSI_ADDR @ 0x190;
    reg {
        name="ISTATUS_MSI";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_MSI @ 0x194;
    reg {
        name="ICMD_PM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ICMD_PM @ 0x198;
    reg {
        name="ISTATUS_PM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_PM @ 0x19c;
    reg {
        name="ATS_PRI_REPORT";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATS_PRI_REPORT @ 0x1a0;
    reg {
        name="LTR_VALUES";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LTR_VALUES @ 0x1a4;
    reg {
        name="ISTATUS_DMA0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_DMA0 @ 0x1b0;
    reg {
        name="ISTATUS_DMA1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_DMA1 @ 0x1b4;
    reg {
        name="ISTATUS_P_ADT_WIN0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_P_ADT_WIN0 @ 0x1d8;
    reg {
        name="ISTATUS_P_ADT_WIN1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_P_ADT_WIN1 @ 0x1dc;
    reg {
        name="ISTATUS_A_ADT_SLV0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_A_ADT_SLV0 @ 0x1e0;
    reg {
        name="ISTATUS_A_ADT_SLV1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_A_ADT_SLV1 @ 0x1e4;
    reg {
        name="ISTATUS_A_ADT_SLV2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_A_ADT_SLV2 @ 0x1e8;
    reg {
        name="ISTATUS_A_ADT_SLV3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ISTATUS_A_ADT_SLV3 @ 0x1ec;
    reg {
        name="ROUTING_RULES_R_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW0 @ 0x200;
    reg {
        name="ROUTING_RULES_R_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW1 @ 0x204;
    reg {
        name="ROUTING_RULES_R_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW2 @ 0x208;
    reg {
        name="ROUTING_RULES_R_DW3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW3 @ 0x20c;
    reg {
        name="ROUTING_RULES_R_DW4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW4 @ 0x210;
    reg {
        name="ROUTING_RULES_R_DW5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW5 @ 0x214;
    reg {
        name="ROUTING_RULES_R_DW6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW6 @ 0x218;
    reg {
        name="ROUTING_RULES_R_DW7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW7 @ 0x21c;
    reg {
        name="ROUTING_RULES_R_DW8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW8 @ 0x220;
    reg {
        name="ROUTING_RULES_R_DW9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW9 @ 0x224;
    reg {
        name="ROUTING_RULES_R_DW10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW10 @ 0x228;
    reg {
        name="ROUTING_RULES_R_DW11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW11 @ 0x22c;
    reg {
        name="ROUTING_RULES_R_DW12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW12 @ 0x230;
    reg {
        name="ROUTING_RULES_R_DW13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW13 @ 0x234;
    reg {
        name="ROUTING_RULES_R_DW14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW14 @ 0x238;
    reg {
        name="ROUTING_RULES_R_DW15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_R_DW15 @ 0x23c;
    reg {
        name="ROUTING_RULES_W_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW0 @ 0x240;
    reg {
        name="ROUTING_RULES_W_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW1 @ 0x244;
    reg {
        name="ROUTING_RULES_W_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW2 @ 0x248;
    reg {
        name="ROUTING_RULES_W_DW3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW3 @ 0x24c;
    reg {
        name="ROUTING_RULES_W_DW4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW4 @ 0x250;
    reg {
        name="ROUTING_RULES_W_DW5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW5 @ 0x254;
    reg {
        name="ROUTING_RULES_W_DW6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW6 @ 0x258;
    reg {
        name="ROUTING_RULES_W_DW7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW7 @ 0x25c;
    reg {
        name="ROUTING_RULES_W_DW8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW8 @ 0x260;
    reg {
        name="ROUTING_RULES_W_DW9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW9 @ 0x264;
    reg {
        name="ROUTING_RULES_W_DW10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW10 @ 0x268;
    reg {
        name="ROUTING_RULES_W_DW11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW11 @ 0x26c;
    reg {
        name="ROUTING_RULES_W_DW12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW12 @ 0x270;
    reg {
        name="ROUTING_RULES_W_DW13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW13 @ 0x274;
    reg {
        name="ROUTING_RULES_W_DW14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW14 @ 0x278;
    reg {
        name="ROUTING_RULES_W_DW15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ROUTING_RULES_W_DW15 @ 0x27c;
    reg {
        name="ARBITRATION_RULES_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW0 @ 0x280;
    reg {
        name="ARBITRATION_RULES_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW1 @ 0x284;
    reg {
        name="ARBITRATION_RULES_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW2 @ 0x288;
    reg {
        name="ARBITRATION_RULES_DW3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW3 @ 0x28c;
    reg {
        name="ARBITRATION_RULES_DW4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW4 @ 0x290;
    reg {
        name="ARBITRATION_RULES_DW5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW5 @ 0x294;
    reg {
        name="ARBITRATION_RULES_DW6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW6 @ 0x298;
    reg {
        name="ARBITRATION_RULES_DW7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW7 @ 0x29c;
    reg {
        name="ARBITRATION_RULES_DW8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW8 @ 0x2a0;
    reg {
        name="ARBITRATION_RULES_DW9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW9 @ 0x2a4;
    reg {
        name="ARBITRATION_RULES_DW10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW10 @ 0x2a8;
    reg {
        name="ARBITRATION_RULES_DW11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW11 @ 0x2ac;
    reg {
        name="ARBITRATION_RULES_DW12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW12 @ 0x2b0;
    reg {
        name="ARBITRATION_RULES_DW13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW13 @ 0x2b4;
    reg {
        name="ARBITRATION_RULES_DW14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW14 @ 0x2b8;
    reg {
        name="ARBITRATION_RULES_DW15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARBITRATION_RULES_DW15 @ 0x2bc;
    reg {
        name="PRIORITY_RULES_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW0 @ 0x2c0;
    reg {
        name="PRIORITY_RULES_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW1 @ 0x2c4;
    reg {
        name="PRIORITY_RULES_DW2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW2 @ 0x2c8;
    reg {
        name="PRIORITY_RULES_DW3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW3 @ 0x2cc;
    reg {
        name="PRIORITY_RULES_DW4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW4 @ 0x2d0;
    reg {
        name="PRIORITY_RULES_DW5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW5 @ 0x2d4;
    reg {
        name="PRIORITY_RULES_DW6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW6 @ 0x2d8;
    reg {
        name="PRIORITY_RULES_DW7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW7 @ 0x2dc;
    reg {
        name="PRIORITY_RULES_DW8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW8 @ 0x2e0;
    reg {
        name="PRIORITY_RULES_DW9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW9 @ 0x2e4;
    reg {
        name="PRIORITY_RULES_DW10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW10 @ 0x2e8;
    reg {
        name="PRIORITY_RULES_DW11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW11 @ 0x2ec;
    reg {
        name="PRIORITY_RULES_DW12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW12 @ 0x2f0;
    reg {
        name="PRIORITY_RULES_DW13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW13 @ 0x2f4;
    reg {
        name="PRIORITY_RULES_DW14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW14 @ 0x2f8;
    reg {
        name="PRIORITY_RULES_DW15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRIORITY_RULES_DW15 @ 0x2fc;
    reg {
        name="P2A_TC_QOS_CONV";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } P2A_TC_QOS_CONV @ 0x3c0;
    reg {
        name="P2A_ATTR_CACHE_CONV";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } P2A_ATTR_CACHE_CONV @ 0x3c4;
    reg {
        name="P2A_NC_BASE_ADDR_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } P2A_NC_BASE_ADDR_DW0 @ 0x3c8;
    reg {
        name="P2A_NC_BASE_ADDR_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } P2A_NC_BASE_ADDR_DW1 @ 0x3cc;
    reg {
        name="DMA0_SRC_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_SRC_PARAM @ 0x400;
    reg {
        name="DMA0_DESTPARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_DESTPARAM @ 0x404;
    reg {
        name="DMA0_SRCADDR_LDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_SRCADDR_LDW @ 0x408;
    reg {
        name="DMA0_SRCADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_SRCADDR_UDW @ 0x40c;
    reg {
        name="DMA0_DESTADDR_LDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_DESTADDR_LDW @ 0x410;
    reg {
        name="DMA0_DESTADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_DESTADDR_UDW @ 0x414;
    reg {
        name="DMA0_LENGTH";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_LENGTH @ 0x418;
    reg {
        name="DMA0_CONTROL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_CONTROL @ 0x41c;
    reg {
        name="DMA0_STATUS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_STATUS @ 0x420;
    reg {
        name="DMA0_PRC_LENGTH";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_PRC_LENGTH @ 0x424;
    reg {
        name="DMA0_SHARE_ACCESS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA0_SHARE_ACCESS @ 0x428;
    reg {
        name="DMA1_SRC_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_SRC_PARAM @ 0x440;
    reg {
        name="DMA1_DESTPARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_DESTPARAM @ 0x444;
    reg {
        name="DMA1_SRCADDR_LDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_SRCADDR_LDW @ 0x448;
    reg {
        name="DMA1_SRCADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_SRCADDR_UDW @ 0x44c;
    reg {
        name="DMA1_DESTADDR_LDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_DESTADDR_LDW @ 0x450;
    reg {
        name="DMA1_DESTADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_DESTADDR_UDW @ 0x454;
    reg {
        name="DMA1_LENGTH";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_LENGTH @ 0x458;
    reg {
        name="DMA1_CONTROL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_CONTROL @ 0x45c;
    reg {
        name="DMA1_STATUS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_STATUS @ 0x460;
    reg {
        name="DMA1_PRC_LENGTH";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_PRC_LENGTH @ 0x464;
    reg {
        name="DMA1_SHARE_ACCESS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMA1_SHARE_ACCESS @ 0x468;
    reg {
        name="ATR0_PCIE_WIN0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN0_SRCADDR_PARAM @ 0x600;
    reg {
        name="ATR0_PCIE_WIN0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN0_SRC_ADDR @ 0x604;
    reg {
        name="ATR0_PCIE_WIN0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN0_TRSL_ADDR_LSB @ 0x608;
    reg {
        name="ATR0_PCIE_WIN0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN0_TRSL_ADDR_UDW @ 0x60c;
    reg {
        name="ATR0_PCIE_WIN0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN0_TRSL_PARAM @ 0x610;
    reg {
        name="ATR0_PCIE_WIN0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN0_TRSL_MASK_DW0 @ 0x618;
    reg {
        name="ATR0_PCIE_WIN0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN0_TRSL_MASK_DW1 @ 0x61c;
    reg {
        name="ATR1_PCIE_WIN0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN0_SRCADDR_PARAM @ 0x620;
    reg {
        name="ATR1_PCIE_WIN0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN0_SRC_ADDR @ 0x624;
    reg {
        name="ATR1_PCIE_WIN0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN0_TRSL_ADDR_LSB @ 0x628;
    reg {
        name="ATR1_PCIE_WIN0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN0_TRSL_ADDR_UDW @ 0x62c;
    reg {
        name="ATR1_PCIE_WIN0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN0_TRSL_PARAM @ 0x630;
    reg {
        name="ATR1_PCIE_WIN0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN0_TRSL_MASK_DW0 @ 0x638;
    reg {
        name="ATR1_PCIE_WIN0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN0_TRSL_MASK_DW1 @ 0x63c;
    reg {
        name="ATR2_PCIE_WIN0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN0_SRCADDR_PARAM @ 0x640;
    reg {
        name="ATR2_PCIE_WIN0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN0_SRC_ADDR @ 0x644;
    reg {
        name="ATR2_PCIE_WIN0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN0_TRSL_ADDR_LSB @ 0x648;
    reg {
        name="ATR2_PCIE_WIN0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN0_TRSL_ADDR_UDW @ 0x64c;
    reg {
        name="ATR2_PCIE_WIN0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN0_TRSL_PARAM @ 0x650;
    reg {
        name="ATR2_PCIE_WIN0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN0_TRSL_MASK_DW0 @ 0x658;
    reg {
        name="ATR2_PCIE_WIN0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN0_TRSL_MASK_DW1 @ 0x65c;
    reg {
        name="ATR3_PCIE_WIN0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN0_SRCADDR_PARAM @ 0x660;
    reg {
        name="ATR3_PCIE_WIN0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN0_SRC_ADDR @ 0x664;
    reg {
        name="ATR3_PCIE_WIN0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN0_TRSL_ADDR_LSB @ 0x668;
    reg {
        name="ATR3_PCIE_WIN0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN0_TRSL_ADDR_UDW @ 0x66c;
    reg {
        name="ATR3_PCIE_WIN0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN0_TRSL_PARAM @ 0x670;
    reg {
        name="ATR3_PCIE_WIN0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN0_TRSL_MASK_DW0 @ 0x678;
    reg {
        name="ATR3_PCIE_WIN0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN0_TRSL_MASK_DW1 @ 0x67c;
    reg {
        name="ATR4_PCIE_WIN0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN0_SRCADDR_PARAM @ 0x680;
    reg {
        name="ATR4_PCIE_WIN0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN0_SRC_ADDR @ 0x684;
    reg {
        name="ATR4_PCIE_WIN0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN0_TRSL_ADDR_LSB @ 0x688;
    reg {
        name="ATR4_PCIE_WIN0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN0_TRSL_ADDR_UDW @ 0x68c;
    reg {
        name="ATR4_PCIE_WIN0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN0_TRSL_PARAM @ 0x690;
    reg {
        name="ATR4_PCIE_WIN0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN0_TRSL_MASK_DW0 @ 0x698;
    reg {
        name="ATR4_PCIE_WIN0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN0_TRSL_MASK_DW1 @ 0x69c;
    reg {
        name="ATR5_PCIE_WIN0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN0_SRCADDR_PARAM @ 0x6a0;
    reg {
        name="ATR5_PCIE_WIN0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN0_SRC_ADDR @ 0x6a4;
    reg {
        name="ATR5_PCIE_WIN0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN0_TRSL_ADDR_LSB @ 0x6a8;
    reg {
        name="ATR5_PCIE_WIN0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN0_TRSL_ADDR_UDW @ 0x6ac;
    reg {
        name="ATR5_PCIE_WIN0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN0_TRSL_PARAM @ 0x6b0;
    reg {
        name="ATR5_PCIE_WIN0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN0_TRSL_MASK_DW0 @ 0x6b8;
    reg {
        name="ATR5_PCIE_WIN0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN0_TRSL_MASK_DW1 @ 0x6bc;
    reg {
        name="ATR6_PCIE_WIN0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN0_SRCADDR_PARAM @ 0x6c0;
    reg {
        name="ATR6_PCIE_WIN0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN0_SRC_ADDR @ 0x6c4;
    reg {
        name="ATR6_PCIE_WIN0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN0_TRSL_ADDR_LSB @ 0x6c8;
    reg {
        name="ATR6_PCIE_WIN0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN0_TRSL_ADDR_UDW @ 0x6cc;
    reg {
        name="ATR6_PCIE_WIN0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN0_TRSL_PARAM @ 0x6d0;
    reg {
        name="ATR6_PCIE_WIN0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN0_TRSL_MASK_DW0 @ 0x6d8;
    reg {
        name="ATR6_PCIE_WIN0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN0_TRSL_MASK_DW1 @ 0x6dc;
    reg {
        name="ATR7_PCIE_WIN0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN0_SRCADDR_PARAM @ 0x6e0;
    reg {
        name="ATR7_PCIE_WIN0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN0_SRC_ADDR @ 0x6e4;
    reg {
        name="ATR7_PCIE_WIN0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN0_TRSL_ADDR_LSB @ 0x6e8;
    reg {
        name="ATR7_PCIE_WIN0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN0_TRSL_ADDR_UDW @ 0x6ec;
    reg {
        name="ATR7_PCIE_WIN0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN0_TRSL_PARAM @ 0x6f0;
    reg {
        name="ATR7_PCIE_WIN0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN0_TRSL_MASK_DW0 @ 0x6f8;
    reg {
        name="ATR7_PCIE_WIN0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN0_TRSL_MASK_DW1 @ 0x6fc;
    reg {
        name="ATR0_PCIE_WIN1_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN1_SRCADDR_PARAM @ 0x700;
    reg {
        name="ATR0_PCIE_WIN1_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN1_SRC_ADDR @ 0x704;
    reg {
        name="ATR0_PCIE_WIN1_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN1_TRSL_ADDR_LSB @ 0x708;
    reg {
        name="ATR0_PCIE_WIN1_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN1_TRSL_ADDR_UDW @ 0x70c;
    reg {
        name="ATR0_PCIE_WIN1_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN1_TRSL_PARAM @ 0x710;
    reg {
        name="ATR0_PCIE_WIN1_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN1_TRSL_MASK_DW0 @ 0x718;
    reg {
        name="ATR0_PCIE_WIN1_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_PCIE_WIN1_TRSL_MASK_DW1 @ 0x71c;
    reg {
        name="ATR1_PCIE_WIN1_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN1_SRCADDR_PARAM @ 0x720;
    reg {
        name="ATR1_PCIE_WIN1_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN1_SRC_ADDR @ 0x724;
    reg {
        name="ATR1_PCIE_WIN1_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN1_TRSL_ADDR_LSB @ 0x728;
    reg {
        name="ATR1_PCIE_WIN1_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN1_TRSL_ADDR_UDW @ 0x72c;
    reg {
        name="ATR1_PCIE_WIN1_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN1_TRSL_PARAM @ 0x730;
    reg {
        name="ATR1_PCIE_WIN1_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN1_TRSL_MASK_DW0 @ 0x738;
    reg {
        name="ATR1_PCIE_WIN1_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_PCIE_WIN1_TRSL_MASK_DW1 @ 0x73c;
    reg {
        name="ATR2_PCIE_WIN1_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN1_SRCADDR_PARAM @ 0x740;
    reg {
        name="ATR2_PCIE_WIN1_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN1_SRC_ADDR @ 0x744;
    reg {
        name="ATR2_PCIE_WIN1_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN1_TRSL_ADDR_LSB @ 0x748;
    reg {
        name="ATR2_PCIE_WIN1_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN1_TRSL_ADDR_UDW @ 0x74c;
    reg {
        name="ATR2_PCIE_WIN1_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN1_TRSL_PARAM @ 0x750;
    reg {
        name="ATR2_PCIE_WIN1_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN1_TRSL_MASK_DW0 @ 0x758;
    reg {
        name="ATR2_PCIE_WIN1_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_PCIE_WIN1_TRSL_MASK_DW1 @ 0x75c;
    reg {
        name="ATR3_PCIE_WIN1_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN1_SRCADDR_PARAM @ 0x760;
    reg {
        name="ATR3_PCIE_WIN1_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN1_SRC_ADDR @ 0x764;
    reg {
        name="ATR3_PCIE_WIN1_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN1_TRSL_ADDR_LSB @ 0x768;
    reg {
        name="ATR3_PCIE_WIN1_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN1_TRSL_ADDR_UDW @ 0x76c;
    reg {
        name="ATR3_PCIE_WIN1_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN1_TRSL_PARAM @ 0x770;
    reg {
        name="ATR3_PCIE_WIN1_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN1_TRSL_MASK_DW0 @ 0x778;
    reg {
        name="ATR3_PCIE_WIN1_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_PCIE_WIN1_TRSL_MASK_DW1 @ 0x77c;
    reg {
        name="ATR4_PCIE_WIN1_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN1_SRCADDR_PARAM @ 0x780;
    reg {
        name="ATR4_PCIE_WIN1_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN1_SRC_ADDR @ 0x784;
    reg {
        name="ATR4_PCIE_WIN1_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN1_TRSL_ADDR_LSB @ 0x788;
    reg {
        name="ATR4_PCIE_WIN1_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN1_TRSL_ADDR_UDW @ 0x78c;
    reg {
        name="ATR4_PCIE_WIN1_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN1_TRSL_PARAM @ 0x790;
    reg {
        name="ATR4_PCIE_WIN1_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN1_TRSL_MASK_DW0 @ 0x798;
    reg {
        name="ATR4_PCIE_WIN1_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_PCIE_WIN1_TRSL_MASK_DW1 @ 0x79c;
    reg {
        name="ATR5_PCIE_WIN1_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN1_SRCADDR_PARAM @ 0x7a0;
    reg {
        name="ATR5_PCIE_WIN1_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN1_SRC_ADDR @ 0x7a4;
    reg {
        name="ATR5_PCIE_WIN1_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN1_TRSL_ADDR_LSB @ 0x7a8;
    reg {
        name="ATR5_PCIE_WIN1_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN1_TRSL_ADDR_UDW @ 0x7ac;
    reg {
        name="ATR5_PCIE_WIN1_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN1_TRSL_PARAM @ 0x7b0;
    reg {
        name="ATR5_PCIE_WIN1_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN1_TRSL_MASK_DW0 @ 0x7b8;
    reg {
        name="ATR5_PCIE_WIN1_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_PCIE_WIN1_TRSL_MASK_DW1 @ 0x7bc;
    reg {
        name="ATR6_PCIE_WIN1_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN1_SRCADDR_PARAM @ 0x7c0;
    reg {
        name="ATR6_PCIE_WIN1_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN1_SRC_ADDR @ 0x7c4;
    reg {
        name="ATR6_PCIE_WIN1_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN1_TRSL_ADDR_LSB @ 0x7c8;
    reg {
        name="ATR6_PCIE_WIN1_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN1_TRSL_ADDR_UDW @ 0x7cc;
    reg {
        name="ATR6_PCIE_WIN1_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN1_TRSL_PARAM @ 0x7d0;
    reg {
        name="ATR6_PCIE_WIN1_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN1_TRSL_MASK_DW0 @ 0x7d8;
    reg {
        name="ATR6_PCIE_WIN1_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_PCIE_WIN1_TRSL_MASK_DW1 @ 0x7dc;
    reg {
        name="ATR7_PCIE_WIN1_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN1_SRCADDR_PARAM @ 0x7e0;
    reg {
        name="ATR7_PCIE_WIN1_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN1_SRC_ADDR @ 0x7e4;
    reg {
        name="ATR7_PCIE_WIN1_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN1_TRSL_ADDR_LSB @ 0x7e8;
    reg {
        name="ATR7_PCIE_WIN1_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN1_TRSL_ADDR_UDW @ 0x7ec;
    reg {
        name="ATR7_PCIE_WIN1_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN1_TRSL_PARAM @ 0x7f0;
    reg {
        name="ATR7_PCIE_WIN1_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN1_TRSL_MASK_DW0 @ 0x7f8;
    reg {
        name="ATR7_PCIE_WIN1_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_PCIE_WIN1_TRSL_MASK_DW1 @ 0x7fc;
    reg {
        name="ATR0_AXI4_SLV0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_AXI4_SLV0_SRCADDR_PARAM @ 0x800;
    reg {
        name="ATR0_AXI4_SLV0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_AXI4_SLV0_SRC_ADDR @ 0x804;
    reg {
        name="ATR0_AXI4_SLV0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_AXI4_SLV0_TRSL_ADDR_LSB @ 0x808;
    reg {
        name="ATR0_AXI4_SLV0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_AXI4_SLV0_TRSL_ADDR_UDW @ 0x80c;
    reg {
        name="ATR0_AXI4_SLV0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_AXI4_SLV0_TRSL_PARAM @ 0x810;
    reg {
        name="ATR0_AXI4_SLV0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_AXI4_SLV0_TRSL_MASK_DW0 @ 0x818;
    reg {
        name="ATR0_AXI4_SLV0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR0_AXI4_SLV0_TRSL_MASK_DW1 @ 0x81c;
    reg {
        name="ATR1_AXI4_SLV0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_AXI4_SLV0_SRCADDR_PARAM @ 0x820;
    reg {
        name="ATR1_AXI4_SLV0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_AXI4_SLV0_SRC_ADDR @ 0x824;
    reg {
        name="ATR1_AXI4_SLV0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_AXI4_SLV0_TRSL_ADDR_LSB @ 0x828;
    reg {
        name="ATR1_AXI4_SLV0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_AXI4_SLV0_TRSL_ADDR_UDW @ 0x82c;
    reg {
        name="ATR1_AXI4_SLV0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_AXI4_SLV0_TRSL_PARAM @ 0x830;
    reg {
        name="ATR1_AXI4_SLV0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_AXI4_SLV0_TRSL_MASK_DW0 @ 0x838;
    reg {
        name="ATR1_AXI4_SLV0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR1_AXI4_SLV0_TRSL_MASK_DW1 @ 0x83c;
    reg {
        name="ATR2_AXI4_SLV0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_AXI4_SLV0_SRCADDR_PARAM @ 0x840;
    reg {
        name="ATR2_AXI4_SLV0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_AXI4_SLV0_SRC_ADDR @ 0x844;
    reg {
        name="ATR2_AXI4_SLV0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_AXI4_SLV0_TRSL_ADDR_LSB @ 0x848;
    reg {
        name="ATR2_AXI4_SLV0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_AXI4_SLV0_TRSL_ADDR_UDW @ 0x84c;
    reg {
        name="ATR2_AXI4_SLV0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_AXI4_SLV0_TRSL_PARAM @ 0x850;
    reg {
        name="ATR2_AXI4_SLV0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_AXI4_SLV0_TRSL_MASK_DW0 @ 0x858;
    reg {
        name="ATR2_AXI4_SLV0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR2_AXI4_SLV0_TRSL_MASK_DW1 @ 0x85c;
    reg {
        name="ATR3_AXI4_SLV0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_AXI4_SLV0_SRCADDR_PARAM @ 0x860;
    reg {
        name="ATR3_AXI4_SLV0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_AXI4_SLV0_SRC_ADDR @ 0x864;
    reg {
        name="ATR3_AXI4_SLV0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_AXI4_SLV0_TRSL_ADDR_LSB @ 0x868;
    reg {
        name="ATR3_AXI4_SLV0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_AXI4_SLV0_TRSL_ADDR_UDW @ 0x86c;
    reg {
        name="ATR3_AXI4_SLV0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_AXI4_SLV0_TRSL_PARAM @ 0x870;
    reg {
        name="ATR3_AXI4_SLV0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_AXI4_SLV0_TRSL_MASK_DW0 @ 0x878;
    reg {
        name="ATR3_AXI4_SLV0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR3_AXI4_SLV0_TRSL_MASK_DW1 @ 0x87c;
    reg {
        name="ATR4_AXI4_SLV0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_AXI4_SLV0_SRCADDR_PARAM @ 0x880;
    reg {
        name="ATR4_AXI4_SLV0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_AXI4_SLV0_SRC_ADDR @ 0x884;
    reg {
        name="ATR4_AXI4_SLV0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_AXI4_SLV0_TRSL_ADDR_LSB @ 0x888;
    reg {
        name="ATR4_AXI4_SLV0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_AXI4_SLV0_TRSL_ADDR_UDW @ 0x88c;
    reg {
        name="ATR4_AXI4_SLV0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_AXI4_SLV0_TRSL_PARAM @ 0x890;
    reg {
        name="ATR4_AXI4_SLV0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_AXI4_SLV0_TRSL_MASK_DW0 @ 0x898;
    reg {
        name="ATR4_AXI4_SLV0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR4_AXI4_SLV0_TRSL_MASK_DW1 @ 0x89c;
    reg {
        name="ATR5_AXI4_SLV0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_AXI4_SLV0_SRCADDR_PARAM @ 0x8a0;
    reg {
        name="ATR5_AXI4_SLV0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_AXI4_SLV0_SRC_ADDR @ 0x8a4;
    reg {
        name="ATR5_AXI4_SLV0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_AXI4_SLV0_TRSL_ADDR_LSB @ 0x8a8;
    reg {
        name="ATR5_AXI4_SLV0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_AXI4_SLV0_TRSL_ADDR_UDW @ 0x8ac;
    reg {
        name="ATR5_AXI4_SLV0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_AXI4_SLV0_TRSL_PARAM @ 0x8b0;
    reg {
        name="ATR5_AXI4_SLV0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_AXI4_SLV0_TRSL_MASK_DW0 @ 0x8b8;
    reg {
        name="ATR5_AXI4_SLV0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR5_AXI4_SLV0_TRSL_MASK_DW1 @ 0x8bc;
    reg {
        name="ATR6_AXI4_SLV0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_AXI4_SLV0_SRCADDR_PARAM @ 0x8c0;
    reg {
        name="ATR6_AXI4_SLV0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_AXI4_SLV0_SRC_ADDR @ 0x8c4;
    reg {
        name="ATR6_AXI4_SLV0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_AXI4_SLV0_TRSL_ADDR_LSB @ 0x8c8;
    reg {
        name="ATR6_AXI4_SLV0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_AXI4_SLV0_TRSL_ADDR_UDW @ 0x8cc;
    reg {
        name="ATR6_AXI4_SLV0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_AXI4_SLV0_TRSL_PARAM @ 0x8d0;
    reg {
        name="ATR6_AXI4_SLV0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_AXI4_SLV0_TRSL_MASK_DW0 @ 0x8d8;
    reg {
        name="ATR6_AXI4_SLV0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR6_AXI4_SLV0_TRSL_MASK_DW1 @ 0x8dc;
    reg {
        name="ATR7_AXI4_SLV0_SRCADDR_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_AXI4_SLV0_SRCADDR_PARAM @ 0x8e0;
    reg {
        name="ATR7_AXI4_SLV0_SRC_ADDR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_AXI4_SLV0_SRC_ADDR @ 0x8e4;
    reg {
        name="ATR7_AXI4_SLV0_TRSL_ADDR_LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_AXI4_SLV0_TRSL_ADDR_LSB @ 0x8e8;
    reg {
        name="ATR7_AXI4_SLV0_TRSL_ADDR_UDW";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_AXI4_SLV0_TRSL_ADDR_UDW @ 0x8ec;
    reg {
        name="ATR7_AXI4_SLV0_TRSL_PARAM";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_AXI4_SLV0_TRSL_PARAM @ 0x8f0;
    reg {
        name="ATR7_AXI4_SLV0_TRSL_MASK_DW0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_AXI4_SLV0_TRSL_MASK_DW0 @ 0x8f8;
    reg {
        name="ATR7_AXI4_SLV0_TRSL_MASK_DW1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ATR7_AXI4_SLV0_TRSL_MASK_DW1 @ 0x8fc;
    reg {
        name="SEC_ERROR_EVENT_CNT";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SEC_ERROR_EVENT_CNT @ 0x2020;
    reg {
        name="DED_ERROR_EVENT_CNT";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DED_ERROR_EVENT_CNT @ 0x2024;
    reg {
        name="SEC_ERROR_INT";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TX_RAM_SEC_ERR_INT[3:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RX_RAM_SEC_ERR_INT[7:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PCIE2AXI_RAM_SEC_ERR_INT[11:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } AXI2PCIE_RAM_SEC_ERR_INT[15:12];
    } SEC_ERROR_INT @ 0x2028;
    reg {
        name="SEC_ERROR_INT_MASK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SEC_ERROR_INT_MASK @ 0x202c;
    reg {
        name="DED_ERROR_INT";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TX_RAM_DED_ERR_INT[3:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RX_RAM_DED_ERR_INT[7:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PCIE2AXI_RAM_DED_ERR_INT[11:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } AXI2PCIE_RAM_DED_ERR_INT[15:12];
    } DED_ERROR_INT @ 0x2030;
    reg {
        name="DED_ERROR_INT_MASK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DED_ERROR_INT_MASK @ 0x2034;
    reg {
        name="ECC_CONTROL";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TX_RAM_INJ_ERR[3:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RX_RAM_INJ_ERR[7:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PCIe2AXI_RAM_INJ_ERR[11:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } AXI2PCIe_RAM_INJ_ERR[15:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TX_RAM_ECC_BYPASS[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RX_RAM_ECC_BYPASS[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PCIe2AXI_RAM_ECC_BYPASS[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } AXI2PCIe_RAM_ECC_BYPASS[27:27];
    } ECC_CONTROL @ 0x2038;
    reg {
        name="ECC_ERR_LOC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ECC_ERR_LOC @ 0x203c;
    reg {
        name="RAM_MARGIN_1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RAM_MARGIN_1 @ 0x2040;
    reg {
        name="RAM_MARGIN_2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RAM_MARGIN_2 @ 0x2044;
    reg {
        name="RAM_POWER_CONTROL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RAM_POWER_CONTROL @ 0x2048;
    reg {
        name="DEBUG_SEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DEBUG_SEL @ 0x2050;
    reg {
        name="LTSSM_STATE";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LTSSM_STATE @ 0x205c;
    reg {
        name="PHY_COMMON_INTERFACE";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PHY_COMMON_INTERFACE @ 0x2060;
    reg {
        name="PL_TX_LANEIF_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PL_TX_LANEIF_0 @ 0x2064;
    reg {
        name="PL_RX_LANEIF_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PL_RX_LANEIF_0 @ 0x2068;
    reg {
        name="PL_WAKECLKREQ";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PL_WAKECLKREQ @ 0x206c;
    reg {
        name="PCICONF_PCI_IDS_OVERRIDE";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCICONF_PCI_IDS_OVERRIDE @ 0x2080;
    reg {
        name="PCICONF_PCI_IDS_31_0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCICONF_PCI_IDS_31_0 @ 0x2084;
    reg {
        name="PCICONF_PCI_IDS_63_32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCICONF_PCI_IDS_63_32 @ 0x2088;
    reg {
        name="PCICONF_PCI_IDS_95_64";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCICONF_PCI_IDS_95_64 @ 0x208c;
    reg {
        name="PCIE_PEX_DEV_LINK_SPC2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_PEX_DEV_LINK_SPC2 @ 0x20a0;
    reg {
        name="PCIE_AXI_MASTER_ATR_CFG0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_AXI_MASTER_ATR_CFG0 @ 0x2100;
    reg {
        name="PCIE_AXI_MASTER_ATR_CFG1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_AXI_MASTER_ATR_CFG1 @ 0x2104;
    reg {
        name="PCIE_AXI_MASTER_ATR_CFG2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_AXI_MASTER_ATR_CFG2 @ 0x2108;
    reg {
        name="AXI_SLAVE_PCIE_ATR_CFG0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AXI_SLAVE_PCIE_ATR_CFG0 @ 0x2120;
    reg {
        name="AXI_SLAVE_PCIE_ATR_CFG1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AXI_SLAVE_PCIE_ATR_CFG1 @ 0x2124;
    reg {
        name="AXI_SLAVE_PCIE_ATR_CFG2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AXI_SLAVE_PCIE_ATR_CFG2 @ 0x2128;
    reg {
        name="PCIE_BAR_01";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_01 @ 0x2140;
    reg {
        name="PCIE_BAR_23";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_23 @ 0x2144;
    reg {
        name="PCIE_BAR_45";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCIE_BAR_45 @ 0x2148;
    reg {
        name="PCIE_EVENT_INT";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } L2_EXIT_INT[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HOTRST_EXIT_INT[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DLUP_EXIT_INT[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } L2_EXIT_INT_MASK[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HOTRST_EXIT_INT_MASK[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DLUP_EXIT_INT_MASK[18:18];
    } PCIE_EVENT_INT @ 0x214c;
} Registers_addrmap;


};