addrmap EFR32xG22_LDMA {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IPVERSION";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IPVERSION @ 0x0;
    reg {
        name="EN";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EN @ 0x4;
    reg {
        name="CTRL";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } NUMFIXED[28:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CORERST[31:31];
    } CTRL @ 0x8;
    reg {
        name="STATUS";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ANYBUSY[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ANYREQ[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CHGRANT[7:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CHERROR[12:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FIFOLEVEL[20:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CHNUM[28:24];
    } STATUS @ 0xc;
    reg {
        name="SYNCSWSET";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSWSET @ 0x10;
    reg {
        name="SYNCSWCLR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSWCLR @ 0x14;
    reg {
        name="SYNCHWEN";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCHWEN @ 0x18;
    reg {
        name="SYNCHWSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCHWSEL @ 0x1c;
    reg {
        name="SYNCSTATUS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSTATUS @ 0x20;
    reg {
        name="CHEN";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } CHEN[7:0];
    } CHEN @ 0x24;
    reg {
        name="CHDIS";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } CHDIS[7:0];
    } CHDIS @ 0x28;
    reg {
        name="CHSTATUS";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } CHSTATUS[7:0];
    } CHSTATUS @ 0x2c;
    reg {
        name="CHBUSY";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } CHBUSY[7:0];
    } CHBUSY @ 0x30;
    reg {
        name="CHDONE";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } CHDONE[7:0];
    } CHDONE @ 0x34;
    reg {
        name="DBGHALT";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DBGHALT[7:0];
    } DBGHALT @ 0x38;
    reg {
        name="SWREQ";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } SWREQ[7:0];
    } SWREQ @ 0x3c;
    reg {
        name="REQDIS";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } REQDIS[7:0];
    } REQDIS @ 0x40;
    reg {
        name="REQPEND";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } REQPEND[7:0];
    } REQPEND @ 0x44;
    reg {
        name="LINKLOAD";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } LINKLOAD[7:0];
    } LINKLOAD @ 0x48;
    reg {
        name="REQCLEAR";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } REQCLEAR[7:0];
    } REQCLEAR @ 0x4c;
    reg {
        name="IF";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } IF[7:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ERROR[31:31];
    } IF @ 0x50;
    reg {
        name="IEN";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } IEN[7:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ERROR[31:31];
    } IEN @ 0x54;
    reg {
        name="CH0_CFG";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_CFG @ 0x5c;
    reg {
        name="CH0_LOOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_LOOP @ 0x60;
    reg {
        name="CH0_CTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_CTRL @ 0x64;
    reg {
        name="CH0_SRC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_SRC @ 0x68;
    reg {
        name="CH0_DST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_DST @ 0x6c;
    reg {
        name="CH0_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_LINK @ 0x70;
    reg {
        name="CH1_CFG";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_CFG @ 0x8c;
    reg {
        name="CH1_LOOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_LOOP @ 0x90;
    reg {
        name="CH1_CTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_CTRL @ 0x94;
    reg {
        name="CH1_SRC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_SRC @ 0x98;
    reg {
        name="CH1_DST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_DST @ 0x9c;
    reg {
        name="CH1_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_LINK @ 0xa0;
    reg {
        name="CH2_CFG";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_CFG @ 0xbc;
    reg {
        name="CH2_LOOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_LOOP @ 0xc0;
    reg {
        name="CH2_CTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_CTRL @ 0xc4;
    reg {
        name="CH2_SRC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_SRC @ 0xc8;
    reg {
        name="CH2_DST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_DST @ 0xcc;
    reg {
        name="CH2_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_LINK @ 0xd0;
    reg {
        name="CH3_CFG";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_CFG @ 0xec;
    reg {
        name="CH3_LOOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_LOOP @ 0xf0;
    reg {
        name="CH3_CTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_CTRL @ 0xf4;
    reg {
        name="CH3_SRC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_SRC @ 0xf8;
    reg {
        name="CH3_DST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_DST @ 0xfc;
    reg {
        name="CH3_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_LINK @ 0x100;
    reg {
        name="CH4_CFG";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_CFG @ 0x11c;
    reg {
        name="CH4_LOOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_LOOP @ 0x120;
    reg {
        name="CH4_CTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_CTRL @ 0x124;
    reg {
        name="CH4_SRC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_SRC @ 0x128;
    reg {
        name="CH4_DST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_DST @ 0x12c;
    reg {
        name="CH4_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_LINK @ 0x130;
    reg {
        name="CH5_CFG";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_CFG @ 0x14c;
    reg {
        name="CH5_LOOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_LOOP @ 0x150;
    reg {
        name="CH5_CTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_CTRL @ 0x154;
    reg {
        name="CH5_SRC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_SRC @ 0x158;
    reg {
        name="CH5_DST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_DST @ 0x15c;
    reg {
        name="CH5_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_LINK @ 0x160;
    reg {
        name="CH6_CFG";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_CFG @ 0x17c;
    reg {
        name="CH6_LOOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_LOOP @ 0x180;
    reg {
        name="CH6_CTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_CTRL @ 0x184;
    reg {
        name="CH6_SRC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_SRC @ 0x188;
    reg {
        name="CH6_DST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_DST @ 0x18c;
    reg {
        name="CH6_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_LINK @ 0x190;
    reg {
        name="CH7_CFG";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_CFG @ 0x1ac;
    reg {
        name="CH7_LOOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_LOOP @ 0x1b0;
    reg {
        name="CH7_CTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_CTRL @ 0x1b4;
    reg {
        name="CH7_SRC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_SRC @ 0x1b8;
    reg {
        name="CH7_DST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_DST @ 0x1bc;
    reg {
        name="CH7_LINK";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_LINK @ 0x1c0;
    reg {
        name="IPVERSION_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IPVERSION_Set @ 0x1000;
    reg {
        name="EN_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EN_Set @ 0x1004;
    reg {
        name="CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CTRL_Set @ 0x1008;
    reg {
        name="STATUS_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } STATUS_Set @ 0x100c;
    reg {
        name="SYNCSWSET_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSWSET_Set @ 0x1010;
    reg {
        name="SYNCSWCLR_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSWCLR_Set @ 0x1014;
    reg {
        name="SYNCHWEN_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCHWEN_Set @ 0x1018;
    reg {
        name="SYNCHWSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCHWSEL_Set @ 0x101c;
    reg {
        name="SYNCSTATUS_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSTATUS_Set @ 0x1020;
    reg {
        name="CHEN_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHEN_Set @ 0x1024;
    reg {
        name="CHDIS_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHDIS_Set @ 0x1028;
    reg {
        name="CHSTATUS_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHSTATUS_Set @ 0x102c;
    reg {
        name="CHBUSY_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHBUSY_Set @ 0x1030;
    reg {
        name="CHDONE_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHDONE_Set @ 0x1034;
    reg {
        name="DBGHALT_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DBGHALT_Set @ 0x1038;
    reg {
        name="SWREQ_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SWREQ_Set @ 0x103c;
    reg {
        name="REQDIS_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQDIS_Set @ 0x1040;
    reg {
        name="REQPEND_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQPEND_Set @ 0x1044;
    reg {
        name="LINKLOAD_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LINKLOAD_Set @ 0x1048;
    reg {
        name="REQCLEAR_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQCLEAR_Set @ 0x104c;
    reg {
        name="IF_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IF_Set @ 0x1050;
    reg {
        name="IEN_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IEN_Set @ 0x1054;
    reg {
        name="CH0_CFG_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_CFG_Set @ 0x105c;
    reg {
        name="CH0_LOOP_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_LOOP_Set @ 0x1060;
    reg {
        name="CH0_CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_CTRL_Set @ 0x1064;
    reg {
        name="CH0_SRC_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_SRC_Set @ 0x1068;
    reg {
        name="CH0_DST_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_DST_Set @ 0x106c;
    reg {
        name="CH0_LINK_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_LINK_Set @ 0x1070;
    reg {
        name="CH1_CFG_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_CFG_Set @ 0x108c;
    reg {
        name="CH1_LOOP_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_LOOP_Set @ 0x1090;
    reg {
        name="CH1_CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_CTRL_Set @ 0x1094;
    reg {
        name="CH1_SRC_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_SRC_Set @ 0x1098;
    reg {
        name="CH1_DST_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_DST_Set @ 0x109c;
    reg {
        name="CH1_LINK_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_LINK_Set @ 0x10a0;
    reg {
        name="CH2_CFG_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_CFG_Set @ 0x10bc;
    reg {
        name="CH2_LOOP_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_LOOP_Set @ 0x10c0;
    reg {
        name="CH2_CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_CTRL_Set @ 0x10c4;
    reg {
        name="CH2_SRC_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_SRC_Set @ 0x10c8;
    reg {
        name="CH2_DST_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_DST_Set @ 0x10cc;
    reg {
        name="CH2_LINK_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_LINK_Set @ 0x10d0;
    reg {
        name="CH3_CFG_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_CFG_Set @ 0x10ec;
    reg {
        name="CH3_LOOP_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_LOOP_Set @ 0x10f0;
    reg {
        name="CH3_CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_CTRL_Set @ 0x10f4;
    reg {
        name="CH3_SRC_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_SRC_Set @ 0x10f8;
    reg {
        name="CH3_DST_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_DST_Set @ 0x10fc;
    reg {
        name="CH3_LINK_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_LINK_Set @ 0x1100;
    reg {
        name="CH4_CFG_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_CFG_Set @ 0x111c;
    reg {
        name="CH4_LOOP_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_LOOP_Set @ 0x1120;
    reg {
        name="CH4_CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_CTRL_Set @ 0x1124;
    reg {
        name="CH4_SRC_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_SRC_Set @ 0x1128;
    reg {
        name="CH4_DST_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_DST_Set @ 0x112c;
    reg {
        name="CH4_LINK_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_LINK_Set @ 0x1130;
    reg {
        name="CH5_CFG_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_CFG_Set @ 0x114c;
    reg {
        name="CH5_LOOP_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_LOOP_Set @ 0x1150;
    reg {
        name="CH5_CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_CTRL_Set @ 0x1154;
    reg {
        name="CH5_SRC_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_SRC_Set @ 0x1158;
    reg {
        name="CH5_DST_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_DST_Set @ 0x115c;
    reg {
        name="CH5_LINK_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_LINK_Set @ 0x1160;
    reg {
        name="CH6_CFG_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_CFG_Set @ 0x117c;
    reg {
        name="CH6_LOOP_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_LOOP_Set @ 0x1180;
    reg {
        name="CH6_CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_CTRL_Set @ 0x1184;
    reg {
        name="CH6_SRC_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_SRC_Set @ 0x1188;
    reg {
        name="CH6_DST_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_DST_Set @ 0x118c;
    reg {
        name="CH6_LINK_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_LINK_Set @ 0x1190;
    reg {
        name="CH7_CFG_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_CFG_Set @ 0x11ac;
    reg {
        name="CH7_LOOP_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_LOOP_Set @ 0x11b0;
    reg {
        name="CH7_CTRL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_CTRL_Set @ 0x11b4;
    reg {
        name="CH7_SRC_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_SRC_Set @ 0x11b8;
    reg {
        name="CH7_DST_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_DST_Set @ 0x11bc;
    reg {
        name="CH7_LINK_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_LINK_Set @ 0x11c0;
    reg {
        name="IPVERSION_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IPVERSION_Clr @ 0x2000;
    reg {
        name="EN_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EN_Clr @ 0x2004;
    reg {
        name="CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CTRL_Clr @ 0x2008;
    reg {
        name="STATUS_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } STATUS_Clr @ 0x200c;
    reg {
        name="SYNCSWSET_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSWSET_Clr @ 0x2010;
    reg {
        name="SYNCSWCLR_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSWCLR_Clr @ 0x2014;
    reg {
        name="SYNCHWEN_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCHWEN_Clr @ 0x2018;
    reg {
        name="SYNCHWSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCHWSEL_Clr @ 0x201c;
    reg {
        name="SYNCSTATUS_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSTATUS_Clr @ 0x2020;
    reg {
        name="CHEN_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHEN_Clr @ 0x2024;
    reg {
        name="CHDIS_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHDIS_Clr @ 0x2028;
    reg {
        name="CHSTATUS_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHSTATUS_Clr @ 0x202c;
    reg {
        name="CHBUSY_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHBUSY_Clr @ 0x2030;
    reg {
        name="CHDONE_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHDONE_Clr @ 0x2034;
    reg {
        name="DBGHALT_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DBGHALT_Clr @ 0x2038;
    reg {
        name="SWREQ_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SWREQ_Clr @ 0x203c;
    reg {
        name="REQDIS_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQDIS_Clr @ 0x2040;
    reg {
        name="REQPEND_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQPEND_Clr @ 0x2044;
    reg {
        name="LINKLOAD_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LINKLOAD_Clr @ 0x2048;
    reg {
        name="REQCLEAR_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQCLEAR_Clr @ 0x204c;
    reg {
        name="IF_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IF_Clr @ 0x2050;
    reg {
        name="IEN_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IEN_Clr @ 0x2054;
    reg {
        name="CH0_CFG_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_CFG_Clr @ 0x205c;
    reg {
        name="CH0_LOOP_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_LOOP_Clr @ 0x2060;
    reg {
        name="CH0_CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_CTRL_Clr @ 0x2064;
    reg {
        name="CH0_SRC_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_SRC_Clr @ 0x2068;
    reg {
        name="CH0_DST_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_DST_Clr @ 0x206c;
    reg {
        name="CH0_LINK_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_LINK_Clr @ 0x2070;
    reg {
        name="CH1_CFG_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_CFG_Clr @ 0x208c;
    reg {
        name="CH1_LOOP_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_LOOP_Clr @ 0x2090;
    reg {
        name="CH1_CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_CTRL_Clr @ 0x2094;
    reg {
        name="CH1_SRC_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_SRC_Clr @ 0x2098;
    reg {
        name="CH1_DST_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_DST_Clr @ 0x209c;
    reg {
        name="CH1_LINK_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_LINK_Clr @ 0x20a0;
    reg {
        name="CH2_CFG_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_CFG_Clr @ 0x20bc;
    reg {
        name="CH2_LOOP_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_LOOP_Clr @ 0x20c0;
    reg {
        name="CH2_CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_CTRL_Clr @ 0x20c4;
    reg {
        name="CH2_SRC_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_SRC_Clr @ 0x20c8;
    reg {
        name="CH2_DST_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_DST_Clr @ 0x20cc;
    reg {
        name="CH2_LINK_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_LINK_Clr @ 0x20d0;
    reg {
        name="CH3_CFG_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_CFG_Clr @ 0x20ec;
    reg {
        name="CH3_LOOP_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_LOOP_Clr @ 0x20f0;
    reg {
        name="CH3_CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_CTRL_Clr @ 0x20f4;
    reg {
        name="CH3_SRC_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_SRC_Clr @ 0x20f8;
    reg {
        name="CH3_DST_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_DST_Clr @ 0x20fc;
    reg {
        name="CH3_LINK_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_LINK_Clr @ 0x2100;
    reg {
        name="CH4_CFG_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_CFG_Clr @ 0x211c;
    reg {
        name="CH4_LOOP_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_LOOP_Clr @ 0x2120;
    reg {
        name="CH4_CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_CTRL_Clr @ 0x2124;
    reg {
        name="CH4_SRC_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_SRC_Clr @ 0x2128;
    reg {
        name="CH4_DST_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_DST_Clr @ 0x212c;
    reg {
        name="CH4_LINK_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_LINK_Clr @ 0x2130;
    reg {
        name="CH5_CFG_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_CFG_Clr @ 0x214c;
    reg {
        name="CH5_LOOP_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_LOOP_Clr @ 0x2150;
    reg {
        name="CH5_CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_CTRL_Clr @ 0x2154;
    reg {
        name="CH5_SRC_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_SRC_Clr @ 0x2158;
    reg {
        name="CH5_DST_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_DST_Clr @ 0x215c;
    reg {
        name="CH5_LINK_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_LINK_Clr @ 0x2160;
    reg {
        name="CH6_CFG_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_CFG_Clr @ 0x217c;
    reg {
        name="CH6_LOOP_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_LOOP_Clr @ 0x2180;
    reg {
        name="CH6_CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_CTRL_Clr @ 0x2184;
    reg {
        name="CH6_SRC_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_SRC_Clr @ 0x2188;
    reg {
        name="CH6_DST_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_DST_Clr @ 0x218c;
    reg {
        name="CH6_LINK_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_LINK_Clr @ 0x2190;
    reg {
        name="CH7_CFG_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_CFG_Clr @ 0x21ac;
    reg {
        name="CH7_LOOP_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_LOOP_Clr @ 0x21b0;
    reg {
        name="CH7_CTRL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_CTRL_Clr @ 0x21b4;
    reg {
        name="CH7_SRC_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_SRC_Clr @ 0x21b8;
    reg {
        name="CH7_DST_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_DST_Clr @ 0x21bc;
    reg {
        name="CH7_LINK_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_LINK_Clr @ 0x21c0;
    reg {
        name="IPVERSION_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IPVERSION_Tgl @ 0x3000;
    reg {
        name="EN_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EN_Tgl @ 0x3004;
    reg {
        name="CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CTRL_Tgl @ 0x3008;
    reg {
        name="STATUS_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } STATUS_Tgl @ 0x300c;
    reg {
        name="SYNCSWSET_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSWSET_Tgl @ 0x3010;
    reg {
        name="SYNCSWCLR_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSWCLR_Tgl @ 0x3014;
    reg {
        name="SYNCHWEN_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCHWEN_Tgl @ 0x3018;
    reg {
        name="SYNCHWSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCHWSEL_Tgl @ 0x301c;
    reg {
        name="SYNCSTATUS_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SYNCSTATUS_Tgl @ 0x3020;
    reg {
        name="CHEN_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHEN_Tgl @ 0x3024;
    reg {
        name="CHDIS_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHDIS_Tgl @ 0x3028;
    reg {
        name="CHSTATUS_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHSTATUS_Tgl @ 0x302c;
    reg {
        name="CHBUSY_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHBUSY_Tgl @ 0x3030;
    reg {
        name="CHDONE_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CHDONE_Tgl @ 0x3034;
    reg {
        name="DBGHALT_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DBGHALT_Tgl @ 0x3038;
    reg {
        name="SWREQ_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SWREQ_Tgl @ 0x303c;
    reg {
        name="REQDIS_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQDIS_Tgl @ 0x3040;
    reg {
        name="REQPEND_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQPEND_Tgl @ 0x3044;
    reg {
        name="LINKLOAD_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LINKLOAD_Tgl @ 0x3048;
    reg {
        name="REQCLEAR_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } REQCLEAR_Tgl @ 0x304c;
    reg {
        name="IF_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IF_Tgl @ 0x3050;
    reg {
        name="IEN_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IEN_Tgl @ 0x3054;
    reg {
        name="CH0_CFG_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_CFG_Tgl @ 0x305c;
    reg {
        name="CH0_LOOP_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_LOOP_Tgl @ 0x3060;
    reg {
        name="CH0_CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_CTRL_Tgl @ 0x3064;
    reg {
        name="CH0_SRC_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_SRC_Tgl @ 0x3068;
    reg {
        name="CH0_DST_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_DST_Tgl @ 0x306c;
    reg {
        name="CH0_LINK_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH0_LINK_Tgl @ 0x3070;
    reg {
        name="CH1_CFG_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_CFG_Tgl @ 0x308c;
    reg {
        name="CH1_LOOP_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_LOOP_Tgl @ 0x3090;
    reg {
        name="CH1_CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_CTRL_Tgl @ 0x3094;
    reg {
        name="CH1_SRC_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_SRC_Tgl @ 0x3098;
    reg {
        name="CH1_DST_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_DST_Tgl @ 0x309c;
    reg {
        name="CH1_LINK_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH1_LINK_Tgl @ 0x30a0;
    reg {
        name="CH2_CFG_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_CFG_Tgl @ 0x30bc;
    reg {
        name="CH2_LOOP_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_LOOP_Tgl @ 0x30c0;
    reg {
        name="CH2_CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_CTRL_Tgl @ 0x30c4;
    reg {
        name="CH2_SRC_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_SRC_Tgl @ 0x30c8;
    reg {
        name="CH2_DST_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_DST_Tgl @ 0x30cc;
    reg {
        name="CH2_LINK_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH2_LINK_Tgl @ 0x30d0;
    reg {
        name="CH3_CFG_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_CFG_Tgl @ 0x30ec;
    reg {
        name="CH3_LOOP_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_LOOP_Tgl @ 0x30f0;
    reg {
        name="CH3_CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_CTRL_Tgl @ 0x30f4;
    reg {
        name="CH3_SRC_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_SRC_Tgl @ 0x30f8;
    reg {
        name="CH3_DST_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_DST_Tgl @ 0x30fc;
    reg {
        name="CH3_LINK_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH3_LINK_Tgl @ 0x3100;
    reg {
        name="CH4_CFG_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_CFG_Tgl @ 0x311c;
    reg {
        name="CH4_LOOP_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_LOOP_Tgl @ 0x3120;
    reg {
        name="CH4_CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_CTRL_Tgl @ 0x3124;
    reg {
        name="CH4_SRC_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_SRC_Tgl @ 0x3128;
    reg {
        name="CH4_DST_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_DST_Tgl @ 0x312c;
    reg {
        name="CH4_LINK_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH4_LINK_Tgl @ 0x3130;
    reg {
        name="CH5_CFG_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_CFG_Tgl @ 0x314c;
    reg {
        name="CH5_LOOP_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_LOOP_Tgl @ 0x3150;
    reg {
        name="CH5_CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_CTRL_Tgl @ 0x3154;
    reg {
        name="CH5_SRC_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_SRC_Tgl @ 0x3158;
    reg {
        name="CH5_DST_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_DST_Tgl @ 0x315c;
    reg {
        name="CH5_LINK_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH5_LINK_Tgl @ 0x3160;
    reg {
        name="CH6_CFG_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_CFG_Tgl @ 0x317c;
    reg {
        name="CH6_LOOP_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_LOOP_Tgl @ 0x3180;
    reg {
        name="CH6_CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_CTRL_Tgl @ 0x3184;
    reg {
        name="CH6_SRC_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_SRC_Tgl @ 0x3188;
    reg {
        name="CH6_DST_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_DST_Tgl @ 0x318c;
    reg {
        name="CH6_LINK_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH6_LINK_Tgl @ 0x3190;
    reg {
        name="CH7_CFG_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_CFG_Tgl @ 0x31ac;
    reg {
        name="CH7_LOOP_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_LOOP_Tgl @ 0x31b0;
    reg {
        name="CH7_CTRL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_CTRL_Tgl @ 0x31b4;
    reg {
        name="CH7_SRC_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_SRC_Tgl @ 0x31b8;
    reg {
        name="CH7_DST_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_DST_Tgl @ 0x31bc;
    reg {
        name="CH7_LINK_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CH7_LINK_Tgl @ 0x31c0;
} LdmaRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="XBAR_CH0_REQSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH0_REQSEL @ 0x0;
    reg {
        name="XBAR_CH1_REQSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH1_REQSEL @ 0x4;
    reg {
        name="XBAR_CH2_REQSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH2_REQSEL @ 0x8;
    reg {
        name="XBAR_CH3_REQSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH3_REQSEL @ 0xc;
    reg {
        name="XBAR_CH4_REQSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH4_REQSEL @ 0x10;
    reg {
        name="XBAR_CH5_REQSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH5_REQSEL @ 0x14;
    reg {
        name="XBAR_CH6_REQSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH6_REQSEL @ 0x18;
    reg {
        name="XBAR_CH7_REQSEL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH7_REQSEL @ 0x1c;
    reg {
        name="XBAR_CH0_REQSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH0_REQSEL_Set @ 0x1000;
    reg {
        name="XBAR_CH1_REQSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH1_REQSEL_Set @ 0x1004;
    reg {
        name="XBAR_CH2_REQSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH2_REQSEL_Set @ 0x1008;
    reg {
        name="XBAR_CH3_REQSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH3_REQSEL_Set @ 0x100c;
    reg {
        name="XBAR_CH4_REQSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH4_REQSEL_Set @ 0x1010;
    reg {
        name="XBAR_CH5_REQSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH5_REQSEL_Set @ 0x1014;
    reg {
        name="XBAR_CH6_REQSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH6_REQSEL_Set @ 0x1018;
    reg {
        name="XBAR_CH7_REQSEL_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH7_REQSEL_Set @ 0x101c;
    reg {
        name="XBAR_CH0_REQSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH0_REQSEL_Clr @ 0x2000;
    reg {
        name="XBAR_CH1_REQSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH1_REQSEL_Clr @ 0x2004;
    reg {
        name="XBAR_CH2_REQSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH2_REQSEL_Clr @ 0x2008;
    reg {
        name="XBAR_CH3_REQSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH3_REQSEL_Clr @ 0x200c;
    reg {
        name="XBAR_CH4_REQSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH4_REQSEL_Clr @ 0x2010;
    reg {
        name="XBAR_CH5_REQSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH5_REQSEL_Clr @ 0x2014;
    reg {
        name="XBAR_CH6_REQSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH6_REQSEL_Clr @ 0x2018;
    reg {
        name="XBAR_CH7_REQSEL_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH7_REQSEL_Clr @ 0x201c;
    reg {
        name="XBAR_CH0_REQSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH0_REQSEL_Tgl @ 0x3000;
    reg {
        name="XBAR_CH1_REQSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH1_REQSEL_Tgl @ 0x3004;
    reg {
        name="XBAR_CH2_REQSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH2_REQSEL_Tgl @ 0x3008;
    reg {
        name="XBAR_CH3_REQSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH3_REQSEL_Tgl @ 0x300c;
    reg {
        name="XBAR_CH4_REQSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH4_REQSEL_Tgl @ 0x3010;
    reg {
        name="XBAR_CH5_REQSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH5_REQSEL_Tgl @ 0x3014;
    reg {
        name="XBAR_CH6_REQSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH6_REQSEL_Tgl @ 0x3018;
    reg {
        name="XBAR_CH7_REQSEL_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XBAR_CH7_REQSEL_Tgl @ 0x301c;
} LdmaXbarRegisters_addrmap;


};