addrmap MPFS_USB {

/* Some conversion errors detected, this might mean that the peripheral's registers structure in this file is incomplete.
 * Please refer to logs and comments in the file for more information.
 * 
 * Register "EndpointNReceiveFifoCount" overlaps another register at the same offset (0x18) and will be skipped, as it is illegal in SystemRDL.
 * Register "TX_TYPE_REG" overlaps another register at the same offset (0x1a) and will be skipped, as it is illegal in SystemRDL.
 * Register "TX_INTERVAL_REG" overlaps another register at the same offset (0x1b) and will be skipped, as it is illegal in SystemRDL.
 * Register "FIFO_SIZE_REG" overlaps another register at the same offset (0x1f) and will be skipped, as it is illegal in SystemRDL.
 * Field "ClrDataTog" overlaps another field at the same offset (0x6) and will be skipped, as it is illegal in SystemRDL.
 * Field "RxStall" overlaps another field at the same offset (0x5) and will be skipped, as it is illegal in SystemRDL.
 * Field "FlushFIFO" overlaps another field at the same offset (0x3) and will be skipped, as it is illegal in SystemRDL.
 * Field "FIFONotEmpty" overlaps another field at the same offset (0x1) and will be skipped, as it is illegal in SystemRDL.
 * Field "TxPktRdy_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Register "TX_CSRL_REG" overlaps another register at the same offset (0x12) and will be skipped, as it is illegal in SystemRDL.
 * Register "TX_CSRH_REG" overlaps another register at the same offset (0x13) and will be skipped, as it is illegal in SystemRDL.
 * Register "TX_CSRL_REG" overlaps another register at the same offset (0x12) and will be skipped, as it is illegal in SystemRDL.
 * Register "TX_CSRH_REG" overlaps another register at the same offset (0x13) and will be skipped, as it is illegal in SystemRDL.
 */

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="FunctionAddress";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FADDR_REG @ 0x0;
    reg {
        name="Power";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } HS_Mode[4:4];
    } POWER_REG @ 0x1;
    reg {
        name="TransmitInterruptsStatus";
        regwidth=0x10;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[15:0];
    } TX_IRQ_REG @ 0x2;
    reg {
        name="ReceiveInterruptsStatus";
        regwidth=0x10;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[15:0];
    } RX_IRQ_REG @ 0x4;
    reg {
        name="TransmitInterruptsEnable";
        regwidth=0x10;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[15:0];
    } TX_IRQ_EN_REG @ 0x6;
    reg {
        name="ReceiveInterrptsEnable";
        regwidth=0x10;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[15:0];
    } RX_IRQ_EN_REG @ 0x8;
    reg {
        name="UsbInterruptsStatus";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USB_IRQ_REG @ 0xa;
    reg {
        name="UsbInterruptsEnable";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USB_IRQ_EN_REG @ 0xb;
    reg {
        name="Frame";
        regwidth=0x10;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[15:0];
    } FRAME_REG @ 0xc;
    reg {
        name="Index";
        regwidth=0x8;
            field {
                sw = rw;
            } Selected_Endpoint[3:0];
    } INDEX_REG @ 0xe;
    reg {
        name="TestMode";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TEST_MODE_REG @ 0xf;
    reg {
        name="TransmitMaximumPacketSize";
        regwidth=0x10;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[15:0];
    } TX_MAX_P_REG @ 0x10;
    reg {
        name="ReceiveMaximumPacketSize";
        regwidth=0x10;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[15:0];
    } RX_MAX_P_REG @ 0x14;
    reg {
        name="Endpoint0FifoCount";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } COUNT0_REG @ 0x18;
    /* Conversion error: Register "EndpointNReceiveFifoCount" overlaps another register at the same offset (0x18) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="EndpointNReceiveFifoCount";
        regwidth=0x10;

    } EndpointNReceiveFifoCount @ 0x18;
    */
    reg {
        name="Endpoint0Type";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TYPE0_REG @ 0x1a;
    /* Conversion error: Register "TX_TYPE_REG" overlaps another register at the same offset (0x1a) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="EndpointNTransmitType";
        regwidth=0x8;

    } TX_TYPE_REG @ 0x1a;
    */
    reg {
        name="Endpoint0NAKLimit";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } NAK_LIMIT0_REG @ 0x1b;
    /* Conversion error: Register "TX_INTERVAL_REG" overlaps another register at the same offset (0x1b) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="EndpointNTransmitInterval";
        regwidth=0x8;

    } TX_INTERVAL_REG @ 0x1b;
    */
    reg {
        name="EndpointNReceiveType";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RX_TYPE_REG @ 0x1c;
    reg {
        name="EndpointNReceiveInterval";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RX_INTERVAL_REG @ 0x1d;
    reg {
        name="Endpoint0ConfigData";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CONFIG_DATA_REG @ 0x1f;
    /* Conversion error: Register "FIFO_SIZE_REG" overlaps another register at the same offset (0x1f) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="EndpointNFifoSize";
        regwidth=0x8;

    } FIFO_SIZE_REG @ 0x1f;
    */
    reg {
        name="Endpoint0Fifo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0Fifo @ 0x20;
    reg {
        name="Endpoint1Fifo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1Fifo @ 0x24;
    reg {
        name="Endpoint2Fifo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2Fifo @ 0x28;
    reg {
        name="Endpoint3Fifo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3Fifo @ 0x2c;
    reg {
        name="Endpoint4Fifo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4Fifo @ 0x30;
    reg {
        name="DeviceControl";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
                reset=1'b1;
            } B_Device[7:7];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } FSDev[6:6];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } VBus[4:3];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } Host_Mode[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } Session[0:0];
    } DEV_CTRL_REG @ 0x60;
    reg {
        name="Misc";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Misc @ 0x61;
    reg {
        name="TransmitFifoSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitFifoSize @ 0x62;
    reg {
        name="ReceiveFifoSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveFifoSize @ 0x63;
    reg {
        name="TransmitFifoAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitFifoAddress @ 0x64;
    reg {
        name="ReceiveFifoAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveFifoAddress @ 0x66;
    reg {
        name="VbusControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VbusControl @ 0x68;
    reg {
        name="HwVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HwVersion @ 0x6c;
    reg {
        name="UlpiVbysControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UlpiVbysControl @ 0x70;
    reg {
        name="UlpiCarKitControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UlpiCarKitControl @ 0x71;
    reg {
        name="UlpiInterruptMask";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UlpiInterruptMask @ 0x72;
    reg {
        name="UlpiInterruptSources";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UlpiInterruptSources @ 0x73;
    reg {
        name="UlpiData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UlpiData @ 0x74;
    reg {
        name="UlpiAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UlpiAddress @ 0x75;
    reg {
        name="UlpiControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UlpiControl @ 0x76;
    reg {
        name="UlpiRawData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UlpiRawData @ 0x77;
    reg {
        name="EndpointInfo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EndpointInfo @ 0x78;
    reg {
        name="RamInfo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RamInfo @ 0x79;
    reg {
        name="LinkInfo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinkInfo @ 0x7a;
    reg {
        name="VbusPulseLength";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VbusPulseLength @ 0x7b;
    reg {
        name="HighSpeedEOF1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighSpeedEOF1 @ 0x7c;
    reg {
        name="FullSpeedEOF1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FullSpeedEOF1 @ 0x7d;
    reg {
        name="LowSpeedEOF1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowSpeedEOF1 @ 0x7e;
    reg {
        name="SoftReset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SoftReset @ 0x7f;
    reg {
        name="Endpoint0TransmitFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0TransmitFunctionAddress @ 0x80;
    reg {
        name="Endpoint0TransmitHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0TransmitHubAddress @ 0x82;
    reg {
        name="Endpoint0TransmitHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0TransmitHubPort @ 0x83;
    reg {
        name="Endpoint0ReceiveFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0ReceiveFunctionAddress @ 0x84;
    reg {
        name="Endpoint1TransmitFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1TransmitFunctionAddress @ 0x88;
    reg {
        name="Endpoint1TransmitHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1TransmitHubAddress @ 0x8a;
    reg {
        name="Endpoint1TransmitHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1TransmitHubPort @ 0x8b;
    reg {
        name="Endpoint1ReceiveHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1ReceiveHubAddress @ 0x8e;
    reg {
        name="Endpoint1ReceiveHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1ReceiveHubPort @ 0x8f;
    reg {
        name="Endpoint2TransmitFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2TransmitFunctionAddress @ 0x90;
    reg {
        name="Endpoint2TransmitHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2TransmitHubAddress @ 0x92;
    reg {
        name="Endpoint2TransmitHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2TransmitHubPort @ 0x93;
    reg {
        name="Endpoint2ReceiveFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2ReceiveFunctionAddress @ 0x94;
    reg {
        name="Endpoint2ReceiveHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2ReceiveHubAddress @ 0x96;
    reg {
        name="Endpoint2ReceiveHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2ReceiveHubPort @ 0x97;
    reg {
        name="Endpoint3TransmitFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3TransmitFunctionAddress @ 0x98;
    reg {
        name="Endpoint3TransmitHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3TransmitHubAddress @ 0x9a;
    reg {
        name="Endpoint3TransmitHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3TransmitHubPort @ 0x9b;
    reg {
        name="Endpoint3ReceiveFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3ReceiveFunctionAddress @ 0x9c;
    reg {
        name="Endpoint3ReceiveHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3ReceiveHubAddress @ 0x9e;
    reg {
        name="Endpoint3ReceiveHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3ReceiveHubPort @ 0x9f;
    reg {
        name="Endpoint4TransmitFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4TransmitFunctionAddress @ 0xa0;
    reg {
        name="Endpoint4TransmitHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4TransmitHubAddress @ 0xa2;
    reg {
        name="Endpoint4TransmitHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4TransmitHubPort @ 0xa3;
    reg {
        name="Endpoint4ReceiveFunctionAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4ReceiveFunctionAddress @ 0xa4;
    reg {
        name="Endpoint4ReceiveHubAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4ReceiveHubAddress @ 0xa6;
    reg {
        name="Endpoint4ReceiveHubPort";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4ReceiveHubPort @ 0xa7;
    reg {
        name="Endpoint0TransmitMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0TransmitMaximumPacketSize @ 0x100;
    reg {
        name="Endpoint0TransmitControlStatus";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x10;
        `ifdef VARIANT0
            field {
                sw = rw;
            } RxPktRdy[0:0];
            field {
                sw = rw;
            } TxPktRdy[1:1];
            field {
                sw = rw;
            } SetupPkt[3:3];
            field {
                sw = rw;
            } ReqPkt[5:5];
            field {
                sw = rw;
            } StatusPkt[6:6];
        `elsif VARIANT5
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } NAK_Timeout_IncompTx[7:7];
            /* Conversion error: Field "ClrDataTog" overlaps another field at the same offset (0x6) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ClrDataTog[6:6];
            */
            /* Conversion error: Field "RxStall" overlaps another field at the same offset (0x5) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RxStall[5:5];
            */
            field {
                sw = rw;
                onwrite = woset;
            } SetupPkt_[4:4];
            /* Conversion error: Field "FlushFIFO" overlaps another field at the same offset (0x3) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FlushFIFO[3:3];
            */
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Error[2:2];
            /* Conversion error: Field "FIFONotEmpty" overlaps another field at the same offset (0x1) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } FIFONotEmpty[1:1];
            */
            /* Conversion error: Field "TxPktRdy_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
                onwrite = woset;
            } TxPktRdy_[0:0];
            */
        `endif

    } EPendpointId_TX_CSR_REG @ 0x102;
    reg {
        name="Endpoint0ReceiveMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0ReceiveMaximumPacketSize @ 0x104;
    reg {
        name="Endpoint0ReceiveControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0ReceiveControlStatus @ 0x106;
    reg {
        name="Endpoint0ReceivePacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0ReceivePacketSize @ 0x108;
    reg {
        name="Endpoint0TransmitType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0TransmitType @ 0x10a;
    reg {
        name="Endpoint0TransmitPollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0TransmitPollingInterval @ 0x10b;
    reg {
        name="Endpoint0ReceiveType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0ReceiveType @ 0x10c;
    reg {
        name="Endpoint0ReceivePollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0ReceivePollingInterval @ 0x10d;
    reg {
        name="Endpoint0FifoSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint0FifoSize @ 0x10e;
    reg {
        name="Endpoint1TransmitMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1TransmitMaximumPacketSize @ 0x110;
    reg {
        name="Endpoint1TransmitControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1TransmitControlStatus @ 0x112;
    reg {
        name="Endpoint1ReceiveMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1ReceiveMaximumPacketSize @ 0x114;
    reg {
        name="Endpoint1ReceiveControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1ReceiveControlStatus @ 0x116;
    reg {
        name="Endpoint1ReceivePacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1ReceivePacketSize @ 0x118;
    reg {
        name="Endpoint1TransmitType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1TransmitType @ 0x11a;
    reg {
        name="Endpoint1TransmitPollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1TransmitPollingInterval @ 0x11b;
    reg {
        name="Endpoint1ReceiveType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1ReceiveType @ 0x11c;
    reg {
        name="Endpoint1ReceivePollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1ReceivePollingInterval @ 0x11d;
    reg {
        name="Endpoint1FifoSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint1FifoSize @ 0x11e;
    reg {
        name="Endpoint2TransmitMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2TransmitMaximumPacketSize @ 0x120;
    reg {
        name="Endpoint2TransmitControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2TransmitControlStatus @ 0x122;
    reg {
        name="Endpoint2ReceiveMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2ReceiveMaximumPacketSize @ 0x124;
    reg {
        name="Endpoint2ReceiveControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2ReceiveControlStatus @ 0x126;
    reg {
        name="Endpoint2ReceivePacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2ReceivePacketSize @ 0x128;
    reg {
        name="Endpoint2TransmitType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2TransmitType @ 0x12a;
    reg {
        name="Endpoint2TransmitPollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2TransmitPollingInterval @ 0x12b;
    reg {
        name="Endpoint2ReceiveType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2ReceiveType @ 0x12c;
    reg {
        name="Endpoint2ReceivePollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2ReceivePollingInterval @ 0x12d;
    reg {
        name="Endpoint2FifoSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint2FifoSize @ 0x12e;
    reg {
        name="Endpoint3TransmitMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3TransmitMaximumPacketSize @ 0x130;
    reg {
        name="Endpoint3TransmitControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3TransmitControlStatus @ 0x132;
    reg {
        name="Endpoint3ReceiveMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3ReceiveMaximumPacketSize @ 0x134;
    reg {
        name="Endpoint3ReceiveControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3ReceiveControlStatus @ 0x136;
    reg {
        name="Endpoint3ReceivePacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3ReceivePacketSize @ 0x138;
    reg {
        name="Endpoint3TransmitType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3TransmitType @ 0x13a;
    reg {
        name="Endpoint3TransmitPollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3TransmitPollingInterval @ 0x13b;
    reg {
        name="Endpoint3ReceiveType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3ReceiveType @ 0x13c;
    reg {
        name="Endpoint3ReceivePollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3ReceivePollingInterval @ 0x13d;
    reg {
        name="Endpoint3FifoSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint3FifoSize @ 0x13e;
    reg {
        name="Endpoint4TransmitMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4TransmitMaximumPacketSize @ 0x140;
    reg {
        name="Endpoint4TransmitControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4TransmitControlStatus @ 0x142;
    reg {
        name="Endpoint4ReceiveMaximumPacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4ReceiveMaximumPacketSize @ 0x144;
    reg {
        name="Endpoint4ReceiveControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4ReceiveControlStatus @ 0x146;
    reg {
        name="Endpoint4ReceivePacketSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4ReceivePacketSize @ 0x148;
    reg {
        name="Endpoint4TransmitType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4TransmitType @ 0x14a;
    reg {
        name="Endpoint4TransmitPollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4TransmitPollingInterval @ 0x14b;
    reg {
        name="Endpoint4ReceiveType";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4ReceiveType @ 0x14c;
    reg {
        name="Endpoint4ReceivePollingInterval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4ReceivePollingInterval @ 0x14d;
    reg {
        name="Endpoint4FifoSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Endpoint4FifoSize @ 0x14e;
    reg {
        name="DmaInterrupt";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaInterrupt @ 0x200;
    reg {
        name="DmaChannel1Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel1Control @ 0x204;
    reg {
        name="DmaChannel1Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel1Address @ 0x208;
    reg {
        name="DmaChannel1Count";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel1Count @ 0x20c;
    reg {
        name="DmaChannel2Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel2Control @ 0x214;
    reg {
        name="DmaChannel2Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel2Address @ 0x218;
    reg {
        name="DmaChannel2Count";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel2Count @ 0x21c;
    reg {
        name="DmaChannel3Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel3Control @ 0x224;
    reg {
        name="DmaChannel3Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel3Address @ 0x228;
    reg {
        name="DmaChannel3Count";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel3Count @ 0x22c;
    reg {
        name="DmaChannel4Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel4Control @ 0x234;
    reg {
        name="DmaChannel4Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel4Address @ 0x238;
    reg {
        name="DmaChannel4Count";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DmaChannel4Count @ 0x23c;
} Registers_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Endpoint0ControlStatusLow";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CSR0L_REG @ 0x12;
    /* Conversion error: Register "TX_CSRL_REG" overlaps another register at the same offset (0x12) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="EndpointNTransmitControlStatusLow";
        regwidth=0x8;

    } TX_CSRL_REG @ 0x12;
    */
    reg {
        name="Endpoint0ControlStatusHigh";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CSR0H_REG @ 0x13;
    /* Conversion error: Register "TX_CSRH_REG" overlaps another register at the same offset (0x13) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="EndpointNTransmitControlStatusHigh";
        regwidth=0x8;

    } TX_CSRH_REG @ 0x13;
    */
    reg {
        name="ReceiveControlStatusLow";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RX_CSRL_REG @ 0x16;
    reg {
        name="ReceiveControlStatusHigh";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RX_CSRH_REG @ 0x17;
} HostRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Endpoint0ControlStatusLow";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CSR0L_REG @ 0x12;
    /* Conversion error: Register "TX_CSRL_REG" overlaps another register at the same offset (0x12) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="EndpointNTransmitControlStatusLow";
        regwidth=0x8;

    } TX_CSRL_REG @ 0x12;
    */
    reg {
        name="Endpoint0ControlStatusHigh";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CSR0H_REG @ 0x13;
    /* Conversion error: Register "TX_CSRH_REG" overlaps another register at the same offset (0x13) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="EndpointNTransmitControlStatusHigh";
        regwidth=0x8;

    } TX_CSRH_REG @ 0x13;
    */
    reg {
        name="ReceiveControlStatusLow";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RX_CSRL_REG @ 0x16;
    reg {
        name="ReceiveControlStatusHigh";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RX_CSRH_REG @ 0x17;
} DeviceRegisters_addrmap;


};