addrmap S32K3XX_EMAC {

/* Some conversion errors detected, this might mean that the peripheral's registers structure in this file is incomplete.
 * Please refer to logs and comments in the file for more information.
 * 
 * Register "VLANTagControl" overlaps another register at the same offset (0x50) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANTagFilter0" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANTagFilter1" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANTagFilter2" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANTagFilter3" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANTagFilter4" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANInclusion0" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANInclusion1" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANInclusion2" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANInclusion3" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANInclusion4" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANInclusion5" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANInclusion6" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
 * Register "VLANInclusion7" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
 */

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Configuration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Configuration @ 0x0;
    reg {
        name="ExtendedConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExtendedConfiguration @ 0x4;
    reg {
        name="PacketFilter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketFilter @ 0x8;
    reg {
        name="WatchdogTimeout";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WatchdogTimeout @ 0xc;
    reg {
        name="HashTable0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HashTable0 @ 0x10;
    reg {
        name="HashTable1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HashTable1 @ 0x14;
    reg {
        name="VLANTag";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VLANTag @ 0x50;
    /* Conversion error: Register "VLANTagControl" overlaps another register at the same offset (0x50) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANTagControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANTagControl @ 0x50;
    */
    reg {
        name="VLANTagData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VLANTagData @ 0x54;
    /* Conversion error: Register "VLANTagFilter0" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANTagFilter0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANTagFilter0 @ 0x54;
    */
    /* Conversion error: Register "VLANTagFilter1" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANTagFilter1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANTagFilter1 @ 0x54;
    */
    /* Conversion error: Register "VLANTagFilter2" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANTagFilter2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANTagFilter2 @ 0x54;
    */
    /* Conversion error: Register "VLANTagFilter3" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANTagFilter3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANTagFilter3 @ 0x54;
    */
    /* Conversion error: Register "VLANTagFilter4" overlaps another register at the same offset (0x54) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANTagFilter4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANTagFilter4 @ 0x54;
    */
    reg {
        name="VLANHashTable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VLANHashTable @ 0x58;
    reg {
        name="VLANInclusion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VLANInclusion @ 0x60;
    /* Conversion error: Register "VLANInclusion0" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANInclusion0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANInclusion0 @ 0x60;
    */
    /* Conversion error: Register "VLANInclusion1" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANInclusion1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANInclusion1 @ 0x60;
    */
    /* Conversion error: Register "VLANInclusion2" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANInclusion2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANInclusion2 @ 0x60;
    */
    /* Conversion error: Register "VLANInclusion3" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANInclusion3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANInclusion3 @ 0x60;
    */
    /* Conversion error: Register "VLANInclusion4" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANInclusion4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANInclusion4 @ 0x60;
    */
    /* Conversion error: Register "VLANInclusion5" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANInclusion5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANInclusion5 @ 0x60;
    */
    /* Conversion error: Register "VLANInclusion6" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANInclusion6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANInclusion6 @ 0x60;
    */
    /* Conversion error: Register "VLANInclusion7" overlaps another register at the same offset (0x60) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="VLANInclusion7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } VLANInclusion7 @ 0x60;
    */
    reg {
        name="InnerVLANInclusion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InnerVLANInclusion @ 0x64;
    reg {
        name="Queue0TransmitFlowControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Queue0TransmitFlowControl @ 0x70;
    reg {
        name="ReceiveFlowControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveFlowControl @ 0x90;
    reg {
        name="ReceiveQueueControl4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveQueueControl4 @ 0x94;
    reg {
        name="ReceiveQueueControl0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveQueueControl0 @ 0xa0;
    reg {
        name="ReceiveQueueControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveQueueControl1 @ 0xa4;
    reg {
        name="ReceiveQueueControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveQueueControl2 @ 0xa8;
    reg {
        name="InterruptStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptStatus @ 0xb0;
    reg {
        name="InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable @ 0xb4;
    reg {
        name="ReceiveTransmitStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveTransmitStatus @ 0xb8;
    reg {
        name="PHYInterfaceControlAndStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PHYInterfaceControlAndStatus @ 0xf8;
    reg {
        name="Version";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Version @ 0x110;
    reg {
        name="Debug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Debug @ 0x114;
    reg {
        name="HardwareFeature0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HardwareFeature0 @ 0x11c;
    reg {
        name="HardwareFeature1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HardwareFeature1 @ 0x120;
    reg {
        name="HardwareFeature2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HardwareFeature2 @ 0x124;
    reg {
        name="HardwareFeature3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HardwareFeature3 @ 0x128;
    reg {
        name="FSMErrorsInterruptStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSMErrorsInterruptStatus @ 0x140;
    reg {
        name="FSMControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSMControl @ 0x148;
    reg {
        name="FSMTimeouts";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FSMTimeouts @ 0x14c;
    reg {
        name="MDIOAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MDIOAddress @ 0x200;
    reg {
        name="ARPAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ARPAddress @ 0x210;
    reg {
        name="CSRSoftwareControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CSRSoftwareControl @ 0x230;
    reg {
        name="FramePreeptionControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FramePreeptionControl @ 0x234;
    reg {
        name="ExtendedConfiguration1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExtendedConfiguration1 @ 0x238;
    reg {
        name="PresentationTimeNanoseconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PresentationTimeNanoseconds @ 0x240;
    reg {
        name="PresentationTimeUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PresentationTimeUpdate @ 0x244;
    reg {
        name="Address0High";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Address0High @ 0x300;
    reg {
        name="Address0Low";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Address0Low @ 0x304;
    reg {
        name="Address1High";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Address1High @ 0x308;
    reg {
        name="Address1Low";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Address1Low @ 0x30c;
    reg {
        name="Address2High";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Address2High @ 0x310;
    reg {
        name="Address2Low";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Address2Low @ 0x314;
    reg {
        name="MMCControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCControl @ 0x700;
    reg {
        name="MMCReceiveInterrupt";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCReceiveInterrupt @ 0x704;
    reg {
        name="MMCTransmitInterrupt";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCTransmitInterrupt @ 0x708;
    reg {
        name="MMCReceiveInterruptMask";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCReceiveInterruptMask @ 0x70c;
    reg {
        name="MMCTransmitInterruptMask";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCTransmitInterruptMask @ 0x710;
    reg {
        name="TransmitOctetCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitOctetCount @ 0x714;
    reg {
        name="TransmitPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitPacketCount @ 0x718;
    reg {
        name="TransmitBroadcastPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitBroadcastPacketGoodCount @ 0x71c;
    reg {
        name="TransmitMulticastPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitMulticastPacketGoodCount @ 0x720;
    reg {
        name="Transmit64OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Transmit64OctetPacketCount @ 0x724;
    reg {
        name="Transmit64To127OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Transmit64To127OctetPacketCount @ 0x728;
    reg {
        name="Transmit128To255OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Transmit128To255OctetPacketCount @ 0x72c;
    reg {
        name="Transmit256To511OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Transmit256To511OctetPacketCount @ 0x730;
    reg {
        name="Transmit512To1023OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Transmit512To1023OctetPacketCount @ 0x734;
    reg {
        name="Transmit1024ToMaxOctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Transmit1024ToMaxOctetPacketCount @ 0x738;
    reg {
        name="TransmitUnicastPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitUnicastPacketCount @ 0x73c;
    reg {
        name="TransmitMulticastPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitMulticastPacketCount @ 0x740;
    reg {
        name="TransmitBroadcastPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitBroadcastPacketCount @ 0x744;
    reg {
        name="TransmitUnderflowErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitUnderflowErrorPacketCount @ 0x748;
    reg {
        name="TransmitSingleCollisionPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitSingleCollisionPacketGoodCount @ 0x74c;
    reg {
        name="TransmitMultipleCollisionPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitMultipleCollisionPacketGoodCount @ 0x750;
    reg {
        name="TransmitDeferredPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitDeferredPacketCount @ 0x754;
    reg {
        name="TransmitLateCollisionPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitLateCollisionPacketCount @ 0x758;
    reg {
        name="TransmitExcessiveCollisionPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitExcessiveCollisionPacketCount @ 0x75c;
    reg {
        name="TransmitCarrierErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitCarrierErrorPacketCount @ 0x760;
    reg {
        name="TransmitOctetGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitOctetGoodCount @ 0x764;
    reg {
        name="TransmitPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitPacketGoodCount @ 0x768;
    reg {
        name="TransmitExcessiveDeferralErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitExcessiveDeferralErrorPacketCount @ 0x76c;
    reg {
        name="TransmitPausePacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitPausePacketCount @ 0x770;
    reg {
        name="TransmitVLANPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitVLANPacketGoodCount @ 0x774;
    reg {
        name="TransmitGreaterThanMaxSizePacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitGreaterThanMaxSizePacketGoodCount @ 0x778;
    reg {
        name="ReceivePacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivePacketCount @ 0x780;
    reg {
        name="ReceiveOctetCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveOctetCount @ 0x784;
    reg {
        name="ReceiveOctetGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveOctetGoodCount @ 0x788;
    reg {
        name="ReceiveBroadcastPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveBroadcastPacketGoodCount @ 0x78c;
    reg {
        name="ReceiveMulticastPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveMulticastPacketGoodCount @ 0x790;
    reg {
        name="ReceiveCRCErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveCRCErrorPacketCount @ 0x794;
    reg {
        name="ReceiveAlignmentErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveAlignmentErrorPacketCount @ 0x798;
    reg {
        name="ReceiveRuntErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveRuntErrorPacketCount @ 0x79c;
    reg {
        name="ReceiveJabberErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveJabberErrorPacketCount @ 0x7a0;
    reg {
        name="ReceiveUndersizeErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveUndersizeErrorPacketCount @ 0x7a4;
    reg {
        name="ReceiveOversizeErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveOversizeErrorPacketCount @ 0x7a8;
    reg {
        name="Receive64To127OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Receive64To127OctetPacketCount @ 0x7b0;
    reg {
        name="Receive128To255OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Receive128To255OctetPacketCount @ 0x7b4;
    reg {
        name="Receive256To511OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Receive256To511OctetPacketCount @ 0x7b8;
    reg {
        name="Receive512To1023OctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Receive512To1023OctetPacketCount @ 0x7bc;
    reg {
        name="Receive1024ToMaxOctetPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Receive1024ToMaxOctetPacketCount @ 0x7c0;
    reg {
        name="ReceiveUnicastPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveUnicastPacketGoodCount @ 0x7c4;
    reg {
        name="ReceiveLengthErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveLengthErrorPacketCount @ 0x7c8;
    reg {
        name="ReceiveOutOfRangeTypePacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveOutOfRangeTypePacketCount @ 0x7cc;
    reg {
        name="ReceivePausePacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivePausePacketCount @ 0x7d0;
    reg {
        name="ReceiveFIFOOverflowPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveFIFOOverflowPacketCount @ 0x7d4;
    reg {
        name="ReceiveVLANPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveVLANPacketCount @ 0x7d8;
    reg {
        name="ReceiveWatchdogErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveWatchdogErrorPacketCount @ 0x7dc;
    reg {
        name="ReceiveReceiveErrorPacketCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveReceiveErrorPacketCount @ 0x7e0;
    reg {
        name="ReceiveControlPacketGoodCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveControlPacketGoodCount @ 0x7e4;
    reg {
        name="MMCFramePreemptionTransmitInterrupt";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCFramePreemptionTransmitInterrupt @ 0x8a0;
    reg {
        name="MMCFramePreemptionTransmitInterruptMask";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCFramePreemptionTransmitInterruptMask @ 0x8a4;
    reg {
        name="MMCFramePreemptionTransmitFragmentCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCFramePreemptionTransmitFragmentCount @ 0x8a8;
    reg {
        name="MMCTransmitHoldRequestCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCTransmitHoldRequestCount @ 0x8ac;
    reg {
        name="MMCFramePreemptionReceiveInterrupt";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCFramePreemptionReceiveInterrupt @ 0x8c0;
    reg {
        name="MMCFramePreemptionReceiveInterruptMask";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCFramePreemptionReceiveInterruptMask @ 0x8c4;
    reg {
        name="MMCReceivePacketAssemblyErrorCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCReceivePacketAssemblyErrorCount @ 0x8c8;
    reg {
        name="MMCReceivePacketSMDErrorCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCReceivePacketSMDErrorCount @ 0x8cc;
    reg {
        name="MMCReceivePacketAssemblyOkCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCReceivePacketAssemblyOkCount @ 0x8d0;
    reg {
        name="MMCFramePreemptionReceiveFragmentCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMCFramePreemptionReceiveFragmentCount @ 0x8d4;
    reg {
        name="Layer3Layer4Control0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Layer4Control0 @ 0x900;
    reg {
        name="Layer4Address0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer4Address0 @ 0x904;
    reg {
        name="Layer3Address0Register0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address0Register0 @ 0x910;
    reg {
        name="Layer3Address1Register0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address1Register0 @ 0x914;
    reg {
        name="Layer3Address2Register0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address2Register0 @ 0x918;
    reg {
        name="Layer3Address3Register0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address3Register0 @ 0x91c;
    reg {
        name="Layer3Layer4Control1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Layer4Control1 @ 0x930;
    reg {
        name="Layer4Address1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer4Address1 @ 0x934;
    reg {
        name="Layer3Address0Register1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address0Register1 @ 0x940;
    reg {
        name="Layer3Address1Register1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address1Register1 @ 0x944;
    reg {
        name="Layer3Address2Register1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address2Register1 @ 0x948;
    reg {
        name="Layer3Address3Register1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address3Register1 @ 0x94c;
    reg {
        name="Layer3Layer4Control2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Layer4Control2 @ 0x960;
    reg {
        name="Layer4Address2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer4Address2 @ 0x964;
    reg {
        name="Layer3Address0Register2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address0Register2 @ 0x970;
    reg {
        name="Layer3Address1Register2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address1Register2 @ 0x974;
    reg {
        name="Layer3Address2Register2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address2Register2 @ 0x978;
    reg {
        name="Layer3Address3Register2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address3Register2 @ 0x97c;
    reg {
        name="Layer3Layer4Control3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Layer4Control3 @ 0x990;
    reg {
        name="Layer4Address3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer4Address3 @ 0x994;
    reg {
        name="Layer3Address0Register3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address0Register3 @ 0x9a0;
    reg {
        name="Layer3Address1Register3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address1Register3 @ 0x9a4;
    reg {
        name="Layer3Address2Register3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address2Register3 @ 0x9a8;
    reg {
        name="Layer3Address3Register3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Layer3Address3Register3 @ 0x9ac;
    reg {
        name="TimestampControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampControl @ 0xb00;
    reg {
        name="SubSecondIncrement";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SubSecondIncrement @ 0xb04;
    reg {
        name="SystemTimeSeconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTimeSeconds @ 0xb08;
    reg {
        name="SystemTimeNanoseconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTimeNanoseconds @ 0xb0c;
    reg {
        name="SystemTimeSecondsUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTimeSecondsUpdate @ 0xb10;
    reg {
        name="SystemTimeNanosecondsUpdate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTimeNanosecondsUpdate @ 0xb14;
    reg {
        name="TimestampAddend";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampAddend @ 0xb18;
    reg {
        name="SystemTimeHigherWordSeconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTimeHigherWordSeconds @ 0xb1c;
    reg {
        name="TimestampStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampStatus @ 0xb20;
    reg {
        name="TransmitTimestampStatusNanoseconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitTimestampStatusNanoseconds @ 0xb30;
    reg {
        name="TransmitTimestampStatusSeconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitTimestampStatusSeconds @ 0xb34;
    reg {
        name="TimestampIngressAsymmetryCorrection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampIngressAsymmetryCorrection @ 0xb50;
    reg {
        name="TimestampEgressAsymmetryCorrection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampEgressAsymmetryCorrection @ 0xb54;
    reg {
        name="TimestampIngressCorrectionNanosecond";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampIngressCorrectionNanosecond @ 0xb58;
    reg {
        name="TimestampEgressCorrectionNanosecond";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampEgressCorrectionNanosecond @ 0xb5c;
    reg {
        name="TimestampIngressCorrectionSubnanosecond";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampIngressCorrectionSubnanosecond @ 0xb60;
    reg {
        name="TimestampEgressCorrectionSubnanosecond";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampEgressCorrectionSubnanosecond @ 0xb64;
    reg {
        name="TimestampIngressLatency";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampIngressLatency @ 0xb68;
    reg {
        name="TimestampEgressLatency";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimestampEgressLatency @ 0xb6c;
    reg {
        name="PPSControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPSControl @ 0xb70;
    reg {
        name="PPS0TargetTimeSeconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS0TargetTimeSeconds @ 0xb80;
    reg {
        name="PPS0TargetTimeNanoseconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS0TargetTimeNanoseconds @ 0xb84;
    reg {
        name="PPS0Interval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS0Interval @ 0xb88;
    reg {
        name="PPS0Width";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS0Width @ 0xb8c;
    reg {
        name="PPS1TargetTimeSeconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS1TargetTimeSeconds @ 0xb90;
    reg {
        name="PPS1TargetTimeNanoseconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS1TargetTimeNanoseconds @ 0xb94;
    reg {
        name="PPS1Interval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS1Interval @ 0xb98;
    reg {
        name="PPS1Width";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS1Width @ 0xb9c;
    reg {
        name="PPS2TargetTimeSeconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS2TargetTimeSeconds @ 0xba0;
    reg {
        name="PPS2TargetTimeNanoseconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS2TargetTimeNanoseconds @ 0xba4;
    reg {
        name="PPS2Interval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS2Interval @ 0xba8;
    reg {
        name="PPS2Width";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS2Width @ 0xbac;
    reg {
        name="PPS3TargetTimeSeconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS3TargetTimeSeconds @ 0xbb0;
    reg {
        name="PPS3TargetTimeNanoseconds";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS3TargetTimeNanoseconds @ 0xbb4;
    reg {
        name="PPS3Interval";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS3Interval @ 0xbb8;
    reg {
        name="PPS3Width";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPS3Width @ 0xbbc;
    reg {
        name="MTLOperationMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLOperationMode @ 0xc00;
    reg {
        name="MTLDebugControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLDebugControl @ 0xc08;
    reg {
        name="MTLDebugStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLDebugStatus @ 0xc0c;
    reg {
        name="MTLFIFODebugData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLFIFODebugData @ 0xc10;
    reg {
        name="MTLInterruptStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLInterruptStatus @ 0xc20;
    reg {
        name="MTLReceiveQueueDMAMap0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueueDMAMap0 @ 0xc30;
    reg {
        name="MTLTimeBasedSchedulingControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTimeBasedSchedulingControl @ 0xc40;
    reg {
        name="MTLEnhancementsToScheduledTransmissionControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLEnhancementsToScheduledTransmissionControl @ 0xc50;
    reg {
        name="MTLEnhancementsToScheduledTransmissionExtendedControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLEnhancementsToScheduledTransmissionExtendedControl @ 0xc54;
    reg {
        name="MTLEnhancementsToScheduledTransmissionStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLEnhancementsToScheduledTransmissionStatus @ 0xc58;
    reg {
        name="MTLEnhancementsToScheduledTransmissionSchedulingError";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLEnhancementsToScheduledTransmissionSchedulingError @ 0xc60;
    reg {
        name="MTLEnhancementsToScheduledTransmissionFrameSizeError";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLEnhancementsToScheduledTransmissionFrameSizeError @ 0xc64;
    reg {
        name="MTLEnhancementsToScheduledTransmissionInterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLEnhancementsToScheduledTransmissionInterruptEnable @ 0xc70;
    reg {
        name="MTLEnhancementsToScheduledTransmissionGateControlList";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLEnhancementsToScheduledTransmissionGateControlList @ 0xc80;
    reg {
        name="MTLEnhancementsToScheduledTransmissionGateControlData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLEnhancementsToScheduledTransmissionGateControlData @ 0xc84;
    reg {
        name="MTLFramePreemptionControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLFramePreemptionControlStatus @ 0xc90;
    reg {
        name="MTLFramePreemptionAdvanceTime";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLFramePreemptionAdvanceTime @ 0xc94;
    reg {
        name="MTLReceiveParserControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveParserControlStatus @ 0xca0;
    reg {
        name="MTLReceiveParserInterruptControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveParserInterruptControlStatus @ 0xca4;
    reg {
        name="MTLReceiveParserDropCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveParserDropCount @ 0xca8;
    reg {
        name="MTLReceiveParserErrorCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveParserErrorCount @ 0xcac;
    reg {
        name="MTLReceiveParserIndirectAccessControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveParserIndirectAccessControlStatus @ 0xcb0;
    reg {
        name="MTLReceiveParserIndirectAccessData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveParserIndirectAccessData @ 0xcb4;
    reg {
        name="MTLReceiveParserBypassCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveParserBypassCount @ 0xcb8;
    reg {
        name="MTLErrorCorrectionControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLErrorCorrectionControl @ 0xcc0;
    reg {
        name="MTLSafetyInterruptStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLSafetyInterruptStatus @ 0xcc4;
    reg {
        name="MTLErrorCorrectionInterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLErrorCorrectionInterruptEnable @ 0xcc8;
    reg {
        name="MTLErrorCorrectionInterruptStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLErrorCorrectionInterruptStatus @ 0xccc;
    reg {
        name="MTLErrorCorrectionErrorStatusCapture";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLErrorCorrectionErrorStatusCapture @ 0xcd0;
    reg {
        name="MTLErrorCorrectionErrorAddressStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLErrorCorrectionErrorAddressStatus @ 0xcd4;
    reg {
        name="MTLErrorCorrectionErrorCountStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLErrorCorrectionErrorCountStatus @ 0xcd8;
    reg {
        name="MTLDataParityProtectionControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLDataParityProtectionControl @ 0xce0;
    reg {
        name="MTLTransmitQueue0OperationMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue0OperationMode @ 0xd00;
    reg {
        name="MTLTransmitQueue0Underflow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue0Underflow @ 0xd04;
    reg {
        name="MTLTransmitQueue0Debug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue0Debug @ 0xd08;
    reg {
        name="MTLTransmitQueue0ETSStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue0ETSStatus @ 0xd14;
    reg {
        name="MTLTransmitQueue0QuantumWeight";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue0QuantumWeight @ 0xd18;
    reg {
        name="MTLQueue0InterruptControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLQueue0InterruptControlStatus @ 0xd2c;
    reg {
        name="MTLReceiveQueue0OperationMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueue0OperationMode @ 0xd30;
    reg {
        name="MTLReceiveQueue0MissedPacketOverflowCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueue0MissedPacketOverflowCount @ 0xd34;
    reg {
        name="MTLReceiveQueue0Debug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueue0Debug @ 0xd38;
    reg {
        name="MTLReceiveQueue0Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueue0Control @ 0xd3c;
    reg {
        name="MTLTransmitQueue1OperationMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1OperationMode @ 0xd40;
    reg {
        name="MTLTransmitQueue1Underflow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1Underflow @ 0xd44;
    reg {
        name="MTLTransmitQueue1Debug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1Debug @ 0xd48;
    reg {
        name="MTLTransmitQueue1ETSControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1ETSControl @ 0xd50;
    reg {
        name="MTLTransmitQueue1ETSStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1ETSStatus @ 0xd54;
    reg {
        name="MTLTransmitQueue1QuantumWeight";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1QuantumWeight @ 0xd58;
    reg {
        name="MTLTransmitQueue1SendSlopeCredit";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1SendSlopeCredit @ 0xd5c;
    reg {
        name="MTLTransmitQueue1HighCredit";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1HighCredit @ 0xd60;
    reg {
        name="MTLTransmitQueue1LowCredit";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLTransmitQueue1LowCredit @ 0xd64;
    reg {
        name="MTLQueue1InterruptControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLQueue1InterruptControlStatus @ 0xd6c;
    reg {
        name="MTLReceiveQueue1OperationMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueue1OperationMode @ 0xd70;
    reg {
        name="MTLReceiveQueue1MissedPacketOverflowCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueue1MissedPacketOverflowCount @ 0xd74;
    reg {
        name="MTLReceiveQueue1Debug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueue1Debug @ 0xd78;
    reg {
        name="MTLReceiveQueue1Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MTLReceiveQueue1Control @ 0xd7c;
    reg {
        name="DMAMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAMode @ 0x1000;
    reg {
        name="DMASystemBusMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMASystemBusMode @ 0x1004;
    reg {
        name="DMAInterruptStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAInterruptStatus @ 0x1008;
    reg {
        name="DMADebugStatus0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMADebugStatus0 @ 0x100c;
    reg {
        name="DMATBSControl0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMATBSControl0 @ 0x1050;
    reg {
        name="DMASafetyInterruptStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMASafetyInterruptStatus @ 0x1080;
    reg {
        name="DMAChannel0Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0Control @ 0x1100;
    reg {
        name="DMAChannel0TransmitControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0TransmitControl @ 0x1104;
    reg {
        name="DMAChannel0ReceiveControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0ReceiveControl @ 0x1108;
    reg {
        name="DMAChannel0TransmitDescriptorListAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0TransmitDescriptorListAddress @ 0x1114;
    reg {
        name="DMAChannel0ReceiveDescriptorListAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0ReceiveDescriptorListAddress @ 0x111c;
    reg {
        name="DMAChannel0TransmitDescriptorTailPointer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0TransmitDescriptorTailPointer @ 0x1120;
    reg {
        name="DMAChannel0ReceiveDescriptorTailPointer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0ReceiveDescriptorTailPointer @ 0x1128;
    reg {
        name="DMAChannel0TransmitDescriptorRingLength";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0TransmitDescriptorRingLength @ 0x112c;
    reg {
        name="DMAChannel0ReceiveDescriptorRingLength";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0ReceiveDescriptorRingLength @ 0x1130;
    reg {
        name="DMAChannel0InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0InterruptEnable @ 0x1134;
    reg {
        name="DMAChannel0ReceiveInterruptWatchdogTimer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0ReceiveInterruptWatchdogTimer @ 0x1138;
    reg {
        name="DMAChannel0SlotFunctionControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0SlotFunctionControlStatus @ 0x113c;
    reg {
        name="DMAChannel0CurrentApplicationTransmitDescriptor";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0CurrentApplicationTransmitDescriptor @ 0x1144;
    reg {
        name="DMAChannel0CurrentApplicationReceiveDescriptor";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0CurrentApplicationReceiveDescriptor @ 0x114c;
    reg {
        name="DMAChannel0CurrentApplicationTransmitBuffer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0CurrentApplicationTransmitBuffer @ 0x1154;
    reg {
        name="DMAChannel0CurrentApplicationReceiveBuffer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0CurrentApplicationReceiveBuffer @ 0x115c;
    reg {
        name="DMAChannel0Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0Status @ 0x1160;
    reg {
        name="DMAChannel0MissedFrameCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0MissedFrameCount @ 0x1164;
    reg {
        name="DMAChannel0ReceiveParserAcceptCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0ReceiveParserAcceptCount @ 0x1168;
    reg {
        name="DMAChannel0ReceiveERICount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel0ReceiveERICount @ 0x116c;
    reg {
        name="DMAChannel1Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1Control @ 0x1180;
    reg {
        name="DMAChannel1TransmitControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1TransmitControl @ 0x1184;
    reg {
        name="DMAChannel1ReceiveControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1ReceiveControl @ 0x1188;
    reg {
        name="DMAChannel1TransmitDescriptorListAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1TransmitDescriptorListAddress @ 0x1194;
    reg {
        name="DMAChannel1ReceiveDescriptorListAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1ReceiveDescriptorListAddress @ 0x119c;
    reg {
        name="DMAChannel1TransmitDescriptorTailPointer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1TransmitDescriptorTailPointer @ 0x11a0;
    reg {
        name="DMAChannel1ReceiveDescriptorTailPointer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1ReceiveDescriptorTailPointer @ 0x11a8;
    reg {
        name="DMAChannel1TransmitDescriptorRingLength";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1TransmitDescriptorRingLength @ 0x11ac;
    reg {
        name="DMAChannel1ReceiveDescriptorRingLength";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1ReceiveDescriptorRingLength @ 0x11b0;
    reg {
        name="DMAChannel1InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1InterruptEnable @ 0x11b4;
    reg {
        name="DMAChannel1ReceiveInterruptWatchdogTimer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1ReceiveInterruptWatchdogTimer @ 0x11b8;
    reg {
        name="DMAChannel1SlotFunctionControlStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1SlotFunctionControlStatus @ 0x11bc;
    reg {
        name="DMAChannel1CurrentApplicationTransmitDescriptor";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1CurrentApplicationTransmitDescriptor @ 0x11c4;
    reg {
        name="DMAChannel1CurrentApplicationReceiveDescriptor";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1CurrentApplicationReceiveDescriptor @ 0x11cc;
    reg {
        name="DMAChannel1CurrentApplicationTransmitBuffer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1CurrentApplicationTransmitBuffer @ 0x11d4;
    reg {
        name="DMAChannel1CurrentApplicationReceiveBuffer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1CurrentApplicationReceiveBuffer @ 0x11dc;
    reg {
        name="DMAChannel1Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1Status @ 0x11e0;
    reg {
        name="DMAChannel1MissedFrameCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1MissedFrameCount @ 0x11e4;
    reg {
        name="DMAChannel1ReceiveParserAcceptCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1ReceiveParserAcceptCount @ 0x11e8;
    reg {
        name="DMAChannel1ReceiveERICount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DMAChannel1ReceiveERICount @ 0x11ec;
} Registers_addrmap;


};