addrmap IMXRT700_SYSCON0 {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="NMISourceSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } NMISourceSelect @ 0x14;
    reg {
        name="CTIMERGlobalStartEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CTIMERGlobalStartEnable @ 0x1c;
    reg {
        name="BusMatrixPriority";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BusMatrixPriority @ 0x78;
    reg {
        name="ReceiveEventPulseGenerator";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiveEventPulseGenerator @ 0x80;
    reg {
        name="LatchedCortexM33TransmitEvent";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LatchedCortexM33TransmitEvent @ 0x84;
    reg {
        name="SystemSecureTickCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemSecureTickCalibration @ 0x90;
    reg {
        name="SystemNonSecureTickCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemNonSecureTickCalibration @ 0x94;
    reg {
        name="CPU0Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CPU0Status @ 0x98;
    reg {
        name="GPIOSynchronizationStages";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOSynchronizationStages @ 0xd0;
    reg {
        name="AutomaticClockGateOverride";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGateOverride @ 0x114;
    reg {
        name="SRAMClockGatingControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SRAMClockGatingControl @ 0x118;
    reg {
        name="MMU0MemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMU0MemoryControl @ 0x130;
    reg {
        name="EDMA0MemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EDMA0MemoryControl @ 0x140;
    reg {
        name="EDMA1MemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EDMA1MemoryControl @ 0x144;
    reg {
        name="ETFMemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ETFMemoryControl @ 0x14c;
    reg {
        name="MMU1MemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MMU1MemoryControl @ 0x150;
    reg {
        name="XSPI0MemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XSPI0MemoryControl @ 0x154;
    reg {
        name="XSPI1MemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XSPI1MemoryControl @ 0x158;
    reg {
        name="CACHE64_CTRL0DataMemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CACHE64_CTRL0DataMemoryControl @ 0x15c;
    reg {
        name="CACHE64_CTRL1DataMemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CACHE64_CTRL1DataMemoryControl @ 0x160;
    reg {
        name="NPUMemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } NPUMemoryControl @ 0x164;
    reg {
        name="CPU0MemoryDataControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CPU0MemoryDataControl @ 0x174;
    reg {
        name="CPU0MemoryTagControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CPU0MemoryTagControl @ 0x178;
    reg {
        name="HiFi4MemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiFi4MemoryControl @ 0x208;
    reg {
        name="SAI0_2MCLKIODirectionControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SAI0_2MCLKIODirectionControl @ 0x240;
    reg {
        name="CACHE64_CTRL0TagMemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CACHE64_CTRL0TagMemoryControl @ 0x25c;
    reg {
        name="CACHE64_CTRL1TagMemoryControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CACHE64_CTRL1TagMemoryControl @ 0x260;
    reg {
        name="VDD2_COMPAutoGatingEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VDD2_COMPAutoGatingEnable @ 0x280;
    reg {
        name="HiFi4Stall";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiFi4Stall @ 0x300;
    reg {
        name="HiFi4OCDHaltOnReset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiFi4OCDHaltOnReset @ 0x304;
    reg {
        name="HiFi4GeneralPurposeRegister0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiFi4GeneralPurposeRegister0 @ 0x308;
    reg {
        name="HiFi4GeneralPurposeRegister1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiFi4GeneralPurposeRegister1 @ 0x314;
    reg {
        name="HiFi4GeneralPurposeRegister2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiFi4GeneralPurposeRegister2 @ 0x318;
    reg {
        name="HiFi4DSPVectorRemap";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiFi4DSPVectorRemap @ 0x31c;
    reg {
        name="EDMA0RequestEnable0";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_1[31:0];
    } EDMA0RequestEnable0 [4]@ 0x420 += 4;
    reg {
        name="EDMA1RequestEnable0";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_2[31:0];
    } EDMA1RequestEnable0 [4]@ 0x430 += 4;
    reg {
        name="AXBSControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AXBSControl @ 0x600;
    reg {
        name="I3CAsynchronousWakeupControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I3CAsynchronousWakeupControl @ 0x628;
    reg {
        name="GrayToBinaryConverterGrayCodeLSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GrayToBinaryConverterGrayCodeLSB @ 0x650;
    reg {
        name="GrayToBinaryConverterGrayCodeMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GrayToBinaryConverterGrayCodeMSB @ 0x654;
    reg {
        name="GrayToBinaryConverterBinaryCodeLSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GrayToBinaryConverterBinaryCodeLSB @ 0x658;
    reg {
        name="GrayToBinaryConverterBinaryCodeMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GrayToBinaryConverterBinaryCodeMSB @ 0x65c;
} Registers_addrmap;


};