addrmap OpenTitan_AlertHandler {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="InterruptState";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
                onwrite = woclr;
            } classa[0:0];
            field {
                sw = rw;
                onwrite = woclr;
            } classb[1:1];
            field {
                sw = rw;
                onwrite = woclr;
            } classc[2:2];
            field {
                sw = rw;
                onwrite = woclr;
            } classd[3:3];
    } InterruptState @ 0x0;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
            } classa[0:0];
            field {
                sw = rw;
            } classb[1:1];
            field {
                sw = rw;
            } classc[2:2];
            field {
                sw = rw;
            } classd[3:3];
    } InterruptEnable @ 0x4;
    reg {
        name="InterruptTest";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } classa[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } classb[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } classc[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } classd[3:3];
    } InterruptTest @ 0x8;
    reg {
        name="PingTimerRegisterWriteEnable";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } PING_TIMER_REGWEN[0:0];
    } PingTimerRegisterWriteEnable @ 0xc;
    reg {
        name="PingTimeoutCycle";
        regwidth=0x20;
            field {
                sw = rw;
                reset=16'b100000000;
            } PING_TIMEOUT_CYC_SHADOWED[15:0];
    } PingTimeoutCycle @ 0x10;
    reg {
        name="PingTimerEnable";
        regwidth=0x20;
            field {
                sw = rw;
                onwrite = woset;
            } PING_TIMER_EN_SHADOWED[0:0];
    } PingTimerEnable @ 0x14;
    reg {
        name="AlertRegisterWriteEnable0";
        regwidth=0x20;
            field {
                sw = rw;
                onwrite = wzc;
                reset=1'b1;
            } EN_idx[0:0];
    } AlertRegisterWriteEnable0 [65]@ 0x18 += 4;
    reg {
        name="AlertEnable0";
        regwidth=0x20;
            field {
                sw = rw;
            } EN_A_idx[0:0];
    } AlertEnable0 [65]@ 0x11c += 4;
    reg {
        name="AlertClass0";
        regwidth=0x20;
            field {
                sw = rw;
            } CLASS_A_idx[1:0];
    } AlertClass0 [65]@ 0x220 += 4;
    reg {
        name="AlertCause0";
        regwidth=0x20;
            field {
                sw = rw;
                onwrite = woclr;
            } A_idx[0:0];
    } AlertCause0 [65]@ 0x324 += 4;
    reg {
        name="LocalAlertRegisterWriteEnable0";
        regwidth=0x20;
            field {
                sw = rw;
                onwrite = wzc;
                reset=1'b1;
            } EN_idx[0:0];
    } LocalAlertRegisterWriteEnable0 [7]@ 0x428 += 4;
    reg {
        name="LocalAlertEnable0";
        regwidth=0x20;
            field {
                sw = rw;
            } EN_LA_idx[0:0];
    } LocalAlertEnable0 [7]@ 0x444 += 4;
    reg {
        name="LocalAlertClass0";
        regwidth=0x20;
            field {
                sw = rw;
            } CLASS_LA_idx[1:0];
    } LocalAlertClass0 [7]@ 0x460 += 4;
    reg {
        name="LocalAlertCause0";
        regwidth=0x20;
            field {
                sw = rw;
                onwrite = woclr;
            } LA_idx[0:0];
    } LocalAlertCause0 [7]@ 0x47c += 4;
    reg {
        name="ClassARegisterWriteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassARegisterWriteEnable @ 0x498;
    reg {
        name="ClassAControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAControl @ 0x49c;
    reg {
        name="ClassAClearRegisterWriteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAClearRegisterWriteEnable @ 0x4a0;
    reg {
        name="ClassAClear";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAClear @ 0x4a4;
    reg {
        name="ClassAAccumulationCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAAccumulationCount @ 0x4a8;
    reg {
        name="ClassAAccumulationThreshold";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAAccumulationThreshold @ 0x4ac;
    reg {
        name="ClassATimeoutCycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassATimeoutCycle @ 0x4b0;
    reg {
        name="ClassACrashdumpTrigger";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassACrashdumpTrigger @ 0x4b4;
    reg {
        name="ClassAPhase0Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAPhase0Cycle @ 0x4b8;
    reg {
        name="ClassAPhase1Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAPhase1Cycle @ 0x4bc;
    reg {
        name="ClassAPhase2Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAPhase2Cycle @ 0x4c0;
    reg {
        name="ClassAPhase3Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAPhase3Cycle @ 0x4c4;
    reg {
        name="ClassAEscalationCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAEscalationCount @ 0x4c8;
    reg {
        name="ClassAState";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassAState @ 0x4cc;
    reg {
        name="ClassBRegisterWriteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBRegisterWriteEnable @ 0x4d0;
    reg {
        name="ClassBControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBControl @ 0x4d4;
    reg {
        name="ClassBClearRegisterWriteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBClearRegisterWriteEnable @ 0x4d8;
    reg {
        name="ClassBClear";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBClear @ 0x4dc;
    reg {
        name="ClassBAccumulationCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBAccumulationCount @ 0x4e0;
    reg {
        name="ClassBAccumulationThreshold";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBAccumulationThreshold @ 0x4e4;
    reg {
        name="ClassBTimeoutCycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBTimeoutCycle @ 0x4e8;
    reg {
        name="ClassBCrashdumpTrigger";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBCrashdumpTrigger @ 0x4ec;
    reg {
        name="ClassBPhase0Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBPhase0Cycle @ 0x4f0;
    reg {
        name="ClassBPhase1Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBPhase1Cycle @ 0x4f4;
    reg {
        name="ClassBPhase2Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBPhase2Cycle @ 0x4f8;
    reg {
        name="ClassBPhase3Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBPhase3Cycle @ 0x4fc;
    reg {
        name="ClassBEscalationCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBEscalationCount @ 0x500;
    reg {
        name="ClassBState";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassBState @ 0x504;
    reg {
        name="ClassCRegisterWriteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCRegisterWriteEnable @ 0x508;
    reg {
        name="ClassCControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCControl @ 0x50c;
    reg {
        name="ClassCClearRegisterWriteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCClearRegisterWriteEnable @ 0x510;
    reg {
        name="ClassCClear";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCClear @ 0x514;
    reg {
        name="ClassCAccumulationCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCAccumulationCount @ 0x518;
    reg {
        name="ClassCAccumulationThreshold";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCAccumulationThreshold @ 0x51c;
    reg {
        name="ClassCTimeoutCycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCTimeoutCycle @ 0x520;
    reg {
        name="ClassCCrashdumpTrigger";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCCrashdumpTrigger @ 0x524;
    reg {
        name="ClassCPhase0Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCPhase0Cycle @ 0x528;
    reg {
        name="ClassCPhase1Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCPhase1Cycle @ 0x52c;
    reg {
        name="ClassCPhase2Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCPhase2Cycle @ 0x530;
    reg {
        name="ClassCPhase3Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCPhase3Cycle @ 0x534;
    reg {
        name="ClassCEscalationCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCEscalationCount @ 0x538;
    reg {
        name="ClassCState";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassCState @ 0x53c;
    reg {
        name="ClassDRegisterWriteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDRegisterWriteEnable @ 0x540;
    reg {
        name="ClassDControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDControl @ 0x544;
    reg {
        name="ClassDClearRegisterWriteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDClearRegisterWriteEnable @ 0x548;
    reg {
        name="ClassDClear";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDClear @ 0x54c;
    reg {
        name="ClassDAccumulationCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDAccumulationCount @ 0x550;
    reg {
        name="ClassDAccumulationThreshold";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDAccumulationThreshold @ 0x554;
    reg {
        name="ClassDTimeoutCycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDTimeoutCycle @ 0x558;
    reg {
        name="ClassDCrashdumpTrigger";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDCrashdumpTrigger @ 0x55c;
    reg {
        name="ClassDPhase0Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDPhase0Cycle @ 0x560;
    reg {
        name="ClassDPhase1Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDPhase1Cycle @ 0x564;
    reg {
        name="ClassDPhase2Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDPhase2Cycle @ 0x568;
    reg {
        name="ClassDPhase3Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDPhase3Cycle @ 0x56c;
    reg {
        name="ClassDEscalationCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDEscalationCount @ 0x570;
    reg {
        name="ClassDState";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClassDState @ 0x574;
} Registers_addrmap;


};