addrmap LiteX_Framebuffer_CSR32 {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Base";
        regwidth=0x20;
            field {
                desc = "This field has reset value calculated at runtime.";
                sw = rw;
            } base[31:0];
    } Base @ 0x0;
    reg {
        name="Length";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Length @ 0x4;
    reg {
        name="Enable";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_1[0:0];
    } Enable @ 0x8;
} DMARegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x0;
    reg {
        name="Hres";
        regwidth=0x20;
            field {
                desc = "This field has reset value calculated at runtime.";
                sw = rw;
            } h_res[15:0];
    } Hres @ 0x4;
    reg {
        name="HsyncStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HsyncStart @ 0x8;
    reg {
        name="HsyncEnd";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HsyncEnd @ 0xc;
    reg {
        name="Hscan";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Hscan @ 0x10;
    reg {
        name="Vres";
        regwidth=0x20;
            field {
                desc = "This field has reset value calculated at runtime.";
                sw = rw;
            } v_res[15:0];
    } Vres @ 0x14;
    reg {
        name="VsyncStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VsyncStart @ 0x18;
    reg {
        name="VsyncEnd";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VsyncEnd @ 0x1c;
    reg {
        name="Vscan";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Vscan @ 0x20;
} VTGRegisters_addrmap;


};