addrmap NS16550 {

/* Some conversion errors detected, this might mean that the peripheral's registers structure in this file is incomplete.
 * Please refer to logs and comments in the file for more information.
 * 
 * Register "DivisorLatchL" overlaps another register at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Register "DivisorLatchH" overlaps another register at the same offset (0x1) and will be skipped, as it is illegal in SystemRDL.
 * Register "FIFOControl" overlaps another register at the same offset (0x2) and will be skipped, as it is illegal in SystemRDL.
 * Register "PrescalerDivision" overlaps another register at the same offset (0x5) and will be skipped, as it is illegal in SystemRDL.
 */

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Data";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data @ 0x0;
    /* Conversion error: Register "DivisorLatchL" overlaps another register at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="DivisorLatchL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } DivisorLatchL @ 0x0;
    */
    reg {
        name="InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable @ 0x1;
    /* Conversion error: Register "DivisorLatchH" overlaps another register at the same offset (0x1) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="DivisorLatchH";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } DivisorLatchH @ 0x1;
    */
    reg {
        name="InterruptIdentification";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptIdentification @ 0x2;
    /* Conversion error: Register "FIFOControl" overlaps another register at the same offset (0x2) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="FIFOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } FIFOControl @ 0x2;
    */
    reg {
        name="LineControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LineControl @ 0x3;
    reg {
        name="ModemControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModemControl @ 0x4;
    reg {
        name="LineStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LineStatus @ 0x5;
    /* Conversion error: Register "PrescalerDivision" overlaps another register at the same offset (0x5) and will be skipped, as it is illegal in SystemRDL.
    reg {
        name="PrescalerDivision";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;

    } PrescalerDivision @ 0x5;
    */
    reg {
        name="ModemStatusRegister";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModemStatusRegister @ 0x6;
    reg {
        name="TriggerLevelScratchpad";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TriggerLevelScratchpad @ 0x7;
    reg {
        name="MultiModeInterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MultiModeInterruptEnable @ 0x9;
    reg {
        name="MultiModeControl0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MultiModeControl0 @ 0xc;
    reg {
        name="MultiModeControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MultiModeControl1 @ 0xd;
    reg {
        name="MultiModeControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MultiModeControl2 @ 0xe;
    reg {
        name="FractionalDivisor";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FractionalDivisor @ 0xf;
    reg {
        name="GlitchFilter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GlitchFilter @ 0x11;
    reg {
        name="TransmitterTimeGuard";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransmitterTimeGuard @ 0x12;
    reg {
        name="ReceiverTimeOut";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceiverTimeOut @ 0x13;
    reg {
        name="LineStatusHack";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LineStatusHack @ 0x14;
} Register_addrmap;


};