addrmap ZynqMP_GQSPI {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Config";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Config @ 0x0;
    reg {
        name="InterruptStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptStatus @ 0x4;
    reg {
        name="InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable @ 0x8;
    reg {
        name="InterruptDisable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptDisable @ 0xc;
    reg {
        name="InterruptUnmask";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptUnmask @ 0x10;
    reg {
        name="Enable";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_1[0:0];
    } LQSPI_En_REG @ 0x14;
    reg {
        name="Delay";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Delay @ 0x18;
    reg {
        name="TxData0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxData0 @ 0x1c;
    reg {
        name="RxData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxData @ 0x20;
    reg {
        name="SlaveIdleCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SlaveIdleCount @ 0x24;
    reg {
        name="TxThreshold";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxThreshold @ 0x28;
    reg {
        name="RxThreshold";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxThreshold @ 0x2c;
    reg {
        name="GPIO";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIO @ 0x30;
    reg {
        name="LoopbackClockDelay";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoopbackClockDelay @ 0x38;
    reg {
        name="TxData1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxData1 @ 0x80;
    reg {
        name="TxData2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxData2 @ 0x84;
    reg {
        name="TxData3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxData3 @ 0x88;
    reg {
        name="LinearConfig";
        regwidth=0x20;
            field {
                sw = rw;
            } No_name_3[30:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_2_[31:31];
    } LQSPI_CFG @ 0xa0;
    reg {
        name="LinearStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearStatus @ 0xa4;
    reg {
        name="Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command @ 0xc0;
    reg {
        name="TransferSize";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransferSize @ 0xc4;
    reg {
        name="DummyCycleEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DummyCycleEnable @ 0xc8;
    reg {
        name="ModuleId";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModuleId @ 0xfc;
} BaseRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Config";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
            } CLK_POL[1:1];
            field {
                sw = rw;
            } CLK_PH[2:2];
            field {
                sw = rw;
            } BAUD_RATE_DIV[5:3];
            field {
                sw = rw;
            } WP_HOLD[19:19];
            field {
                sw = rw;
            } EN_POLL_TIMEOUT[20:20];
            field {
                sw = rw;
            } ENDIAN[26:26];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } START_GEN_FIFO[28:28];
            field {
                sw = rw;
            } GEN_FIFO_START_MODE[29:29];
            field {
                sw = rw;
            } No_name_4[31:30];
    } GQSPI_CFG @ 0x100;
    reg {
        name="InterruptStatus";
        regwidth=0x20;
            field {
                sw = r;
                onread = rclr;
            } Poll_Time_Expire[1:1];
            field {
                sw = r;
                onread = rclr;
            } TX_FIFO_not_full[2:2];
            field {
                sw = r;
                onread = rclr;
            } TX_FIFO_full[3:3];
            field {
                sw = r;
                onread = rclr;
            } RX_FIFO_not_empty[4:4];
            field {
                sw = r;
                onread = rclr;
            } RX_FIFO_full[5:5];
            field {
                sw = r;
                onread = rclr;
            } Gen_FIFO_Empty[7:7];
            field {
                sw = r;
                onread = rclr;
            } TX_FIFO_EMPTY[8:8];
            field {
                sw = r;
                onread = rclr;
            } Gen_FIFO_not_full[9:9];
            field {
                sw = r;
                onread = rclr;
            } Gen_FIFO_full[10:10];
            field {
                sw = r;
                onread = rclr;
            } RX_FIFO_EMPTY[11:11];
    } GQSPI_ISR @ 0x104;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = w;
                onwrite = woset;
            } Poll_Time_Expire[1:1];
            field {
                sw = w;
                onwrite = woset;
            } TX_FIFO_not_full[2:2];
            field {
                sw = w;
                onwrite = woset;
            } TX_FIFO_full[3:3];
            field {
                sw = w;
                onwrite = woset;
            } RX_FIFO_not_empty[4:4];
            field {
                sw = w;
                onwrite = woset;
            } RX_FIFO_full[5:5];
            field {
                sw = w;
                onwrite = woset;
            } Gen_FIFO_Empty[7:7];
            field {
                sw = w;
                onwrite = woset;
            } TX_FIFO_EMPTY[8:8];
            field {
                sw = w;
                onwrite = woset;
            } Gen_FIFO_not_full[9:9];
            field {
                sw = w;
                onwrite = woset;
            } Gen_FIFO_full[10:10];
            field {
                sw = w;
                onwrite = woset;
            } RX_FIFO_EMPTY[11:11];
    } GQSPI_IER @ 0x108;
    reg {
        name="InterruptDisable";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } Poll_Time_Expire[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } TX_FIFO_not_full[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } TX_FIFO_full[3:3];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } RX_FIFO_not_empty[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } RX_FIFO_full[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } Gen_FIFO_Empty[7:7];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } TX_FIFO_EMPTY[8:8];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } Gen_FIFO_not_full[9:9];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } Gen_FIFO_full[10:10];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } RX_FIFO_EMPTY[11:11];
    } GQSPI_IDR @ 0x10c;
    reg {
        name="InterruptMask";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } Poll_Time_Expire[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } TX_FIFO_not_full[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } TX_FIFO_full[3:3];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RX_FIFO_not_empty[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RX_FIFO_full[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } Gen_FIFO_Empty[7:7];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } TX_FIFO_EMPTY[8:8];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } Gen_FIFO_not_full[9:9];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } Gen_FIFO_full[10:10];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RX_FIFO_EMPTY[11:11];
    } GQSPI_IMASK @ 0x110;
    reg {
        name="Enable";
        regwidth=0x20;
            field {
                sw = rw;
            } No_name_6[0:0];
            field {
                sw = r;
            } No_name_5_[31:1];
    } GQSPI_En_REG @ 0x114;
    reg {
        name="TxData";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } TX_DATA[31:0];
    } GQSPI_TXD @ 0x11c;
    reg {
        name="RxData";
        desc = "This register has the following custom Renode callbacks: Read";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RX_DATA[31:0];
    } GQSPI_RXD @ 0x120;
    reg {
        name="TxThreshold";
        regwidth=0x20;
            field {
                sw = rw;
            } Level_RX_FIFO[5:0];
    } GQSPI_TX_THRESH @ 0x128;
    reg {
        name="RxThreshold";
        regwidth=0x20;
            field {
                sw = rw;
            } Level_TX_FIFO[5:0];
    } GQSPI_RX_THRESH @ 0x12c;
    reg {
        name="GPIO";
        regwidth=0x20;
            field {
                sw = rw;
            } WP_N[0:0];
    } GQSPI_GPIO @ 0x130;
    reg {
        name="LoopbackClockDelay";
        regwidth=0x20;
            field {
                sw = rw;
                reset=3'b11;
            } DLY0[2:0];
            field {
                sw = rw;
                reset=2'b10;
            } DLY1[4:3];
            field {
                sw = rw;
                reset=1'b1;
            } USE_LPBK[5:5];
    } GQSPI_LPBK_DLY_ADJ @ 0x138;
    reg {
        name="GenericFifo";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = w;
            } No_name_7[19:0];
    } GQSPI_GEN_FIFO @ 0x140;
    reg {
        name="Select";
        regwidth=0x20;
            field {
                sw = rw;
            } No_name_8[0:0];
    } GQSPI_SEL @ 0x144;
    reg {
        name="FifoControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } No_name_11[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } No_name_9_[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } No_name_10_[2:2];
    } GQSPI_FIFO_CTRL @ 0x14c;
    reg {
        name="GenericFifoThreshold";
        regwidth=0x20;
            field {
                sw = rw;
            } Level_GF_FIFO[4:0];
    } GQSPI_GF_THRESH @ 0x150;
    reg {
        name="PollConfig";
        regwidth=0x20;
            field {
                sw = rw;
            } DATA_VALUE[7:0];
            field {
                sw = rw;
            } MASK_EN[15:8];
            field {
                sw = rw;
            } EN_MASK_LOWER[30:30];
            field {
                sw = rw;
            } EN_MASK_UPPER[31:31];
    } GQSPI_POLL_CFG @ 0x154;
    reg {
        name="PollTimeout";
        regwidth=0x20;
            field {
                sw = rw;
            } VALUE[31:0];
    } GQSPI_P_TIMEOUT @ 0x158;
    reg {
        name="TransferStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TransferStatus @ 0x15c;
    reg {
        name="FifoSnapshot";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FifoSnapshot @ 0x160;
    reg {
        name="RxCopy";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxCopy @ 0x164;
    reg {
        name="DataDelay";
        regwidth=0x20;
            field {
                sw = rw;
            } DATA_DLY_ADJ[30:28];
            field {
                sw = rw;
            } USE_DATA_DLY[31:31];
    } QSPI_DATA_DLY_ADJ @ 0x1f8;
    reg {
        name="ModuleId";
        regwidth=0x20;
            field {
                sw = rw;
                reset=32'b1000010100000000000000000;
            } No_name_12[31:0];
    } MOD_ID @ 0x1fc;
} GenericQSPIRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="DmaDestinationAddress";
        regwidth=0x20;
            field {
                sw = w;
            } No_name_13[31:0];
    } QSPIDMA_DST_ADDR @ 0x800;
    reg {
        name="DmaDestinationSize";
        regwidth=0x20;
            field {
                sw = w;
            } No_name_14[31:2];
    } QSPIDMA_DST_SIZE @ 0x804;
    external reg {
        name="DmaDestinationStatus";
        regwidth=0x20;
            field {
                sw = r;
            } BUSY[0:0];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } No_name_15[15:13];
    } QSPIDMA_DST_STS @ 0x808;
    reg {
        name="DmaDestinationControl";
        regwidth=0x20;
            field {
                sw = rw;
            } PAUSE_MEM[0:0];
            field {
                sw = rw;
            } PAUSE_STRM[1:1];
            field {
                sw = rw;
                reset=8'b10000000;
            } FIFO_THRESH[9:2];
            field {
                sw = rw;
                reset=12'b111111111110;
            } TIMEOUT_VAL[21:10];
            field {
                sw = rw;
            } AXI_BRST_TYPE[22:22];
            field {
                sw = rw;
            } ENDIANNESS[23:23];
            field {
                sw = rw;
            } APB_ERR_RESP[24:24];
            field {
                sw = rw;
                reset=7'b1000000;
            } FIFO_LVL_HIT_THRESH[31:25];
    } QSPIDMA_DST_CTRL @ 0x80c;
    external reg {
        name="DmaDestinationInterruptStatus";
        regwidth=0x20;
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } DONE[1:1];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } AXI_BRESP_ERR[2:2];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } TIMEOUT_STRM[3:3];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } TIMEOUT_MEM[4:4];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } THRESH_HIT[5:5];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } INVALID_APB[6:6];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } FIFO_OVERFLOW[7:7];
    } QSPIDMA_DST_I_STS @ 0x814;
    external reg {
        name="DmaDestinationInterruptEnable";
        regwidth=0x20;
            field {
                sw = rw;
                onwrite = woset;
            } DONE[1:1];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } AXI_BRESP_ERR[2:2];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } TIMEOUT_STRM[3:3];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } TIMEOUT_MEM[4:4];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } THRESH_HIT[5:5];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } INVALID_APB[6:6];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } FIFO_OVERFLOW[7:7];
    } QSPIDMA_DST_I_EN @ 0x818;
    external reg {
        name="DmaDestinationInterruptDisable";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } DONE[1:1];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } AXI_BRESP_ERR[2:2];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } TIMEOUT_STRM[3:3];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } TIMEOUT_MEM[4:4];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } THRESH_HIT[5:5];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } INVALID_APB[6:6];
            field {
                desc = "This field uses access mode that cannot be resolved at compile-time.";
                sw = rw;
                onwrite = wuser;
                onread = ruser;
            } FIFO_OVERFLOW[7:7];
    } QSPIDMA_DST_I_DIS @ 0x81c;
    reg {
        name="DmaDestinationInterruptMask";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } DONE[1:1];
            field {
                sw = r;
            } AXI_BRESP_ERR[2:2];
            field {
                sw = r;
            } TIMEOUT_STRM[3:3];
            field {
                sw = r;
            } TIMEOUT_MEM[4:4];
            field {
                sw = r;
            } THRESH_HIT[5:5];
            field {
                sw = r;
            } INVALID_APB[6:6];
            field {
                sw = r;
            } FIFO_OVERFLOW[7:7];
    } QSPIDMA_DST_I_MASK @ 0x820;
    reg {
        name="DmaDestinationControl2";
        regwidth=0x20;
            field {
                sw = rw;
                reset=4'b1000;
            } MAX_OUTS_CMDS[3:0];
            field {
                sw = rw;
                reset=12'b111111111111;
            } TIMEOUT_PRE[15:4];
            field {
                sw = rw;
            } TIMEOUT_EN[22:22];
            field {
                sw = rw;
            } AWCACHE[26:24];
    } QSPIDMA_DST_CTRL2 @ 0x824;
    reg {
        name="DmaDestinationAddressMsb";
        regwidth=0x20;
            field {
                sw = w;
            } No_name_17[11:0];
            field {
                sw = rw;
            } No_name_16_[31:12];
    } QSPIDMA_DST_ADDR_MSB @ 0x828;
} DMARegisters_addrmap;


};