addrmap FocalTechFT9001_TRNG {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="CONTROL";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Clock_prescaler_CLK_DIV[7:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TRNG_enable_EN[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Interrupt_enable_EN_IT[9:9];
            field {
                sw = w;
                onwrite = woclr;
            } Clear_interrupt_CLR_IT[10:10];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } Interrupt_IT[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Analog_model_enable_EN_ANA[19:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Analog_model_reset_RST_ANA[23:20];
    } CONTROL @ 0x0;
    reg {
        name="DATA";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } No_name_1[31:0];
    } DATA @ 0x4;
    reg {
        name="TMCTRL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TMCTRL @ 0x8;
    reg {
        name="STSCR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } STSCR @ 0xc;
    reg {
        name="OSCR_Mx0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OSCR_Mx0 @ 0x10;
    reg {
        name="OSCR_Mx1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OSCR_Mx1 @ 0x14;
    reg {
        name="OSCR_Mx2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OSCR_Mx2 @ 0x18;
    reg {
        name="OSCR_Mx3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OSCR_Mx3 @ 0x1c;
    reg {
        name="RESERVED0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED0 @ 0x20;
    reg {
        name="RESERVED1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED1 @ 0x24;
    reg {
        name="RESERVED2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED2 @ 0x28;
    reg {
        name="RESERVED3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED3 @ 0x2c;
    reg {
        name="RESERVED4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED4 @ 0x30;
    reg {
        name="RESERVED5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED5 @ 0x34;
    reg {
        name="RESERVED6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED6 @ 0x38;
    reg {
        name="RESERVED7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED7 @ 0x3c;
    reg {
        name="RESERVED8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED8 @ 0x40;
    reg {
        name="RESERVED9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RESERVED9 @ 0x44;
    reg {
        name="SM3DRx0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM3DRx0 @ 0x48;
    reg {
        name="SM3DRx1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM3DRx1 @ 0x4c;
    reg {
        name="SM3DRx2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM3DRx2 @ 0x50;
    reg {
        name="SM3DRx3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM3DRx3 @ 0x54;
    reg {
        name="SM3DRx4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM3DRx4 @ 0x58;
    reg {
        name="SM3DRx5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM3DRx5 @ 0x5c;
    reg {
        name="SM3DRx6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM3DRx6 @ 0x60;
    reg {
        name="SM3DRx7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM3DRx7 @ 0x64;
    reg {
        name="OSCTRIMR1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OSCTRIMR1 @ 0x68;
    reg {
        name="OSCTRIMR2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OSCTRIMR2 @ 0x6c;
    reg {
        name="OSCCTR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OSCCTR @ 0x70;
    reg {
        name="OSCDIVR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OSCDIVR @ 0x74;
} Registers_addrmap;


};