addrmap EFR32xG24_Radio {

/* Some conversion errors detected, this might mean that the peripheral's registers structure in this file is incomplete.
 * Please refer to logs and comments in the file for more information.
 * 
 * Field "MBOXIEN0_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "MBOXIEN1_" overlaps another field at the same offset (0x1) and will be skipped, as it is illegal in SystemRDL.
 * Field "MBOXIEN2_" overlaps another field at the same offset (0x2) and will be skipped, as it is illegal in SystemRDL.
 * Field "MBOXIEN3_" overlaps another field at the same offset (0x3) and will be skipped, as it is illegal in SystemRDL.
 */

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion @ 0x0;
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x4;
    reg {
        name="Status";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SNIFFDCOUNT[4:0];
            field {
                sw = r;
            } ACTIVETXFCD[5:5];
            field {
                sw = r;
            } ACTIVERXFCD[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SNIFFDFRAME[7:7];
            field {
                sw = r;
            } RXRAWBLOCKED[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMEOK[9:9];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RXABORTINPROGRESS[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXWORD[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXWORD[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CONVPAUSED[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXSUBFRAMEPAUSED[14:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEREADPAUSED[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEWRITEPAUSED[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMEDETPAUSED[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMELENGTHERROR[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEMODERROR[19:19];
            field {
                sw = rw;
            } FSMSTATE[24:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXWCNTMATCHPAUSED[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CRCERRORTOLERATED[26:26];
    } Status @ 0x8;
    reg {
        name="DynamicFrameLengthControl";
        regwidth=0x20;
            field {
                sw = rw;
            } DFLMODE[2:0];
            field {
                sw = rw;
            } DFLBITORDER[3:3];
            field {
                sw = rw;
            } DFLSHIFT[6:4];
            field {
                sw = rw;
            } DFLOFFSET[11:8];
            field {
                sw = rw;
            } DFLBITS[15:12];
            field {
                sw = rw;
            } MINLENGTH[19:16];
            field {
                sw = rw;
            } DFLINCLUDECRC[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DFLBOIOFFSET[24:21];
    } DynamicFrameLengthControl @ 0xc;
    reg {
        name="MaximumFrameLength";
        regwidth=0x20;
            field {
                sw = rw;
            } MAXLENGTH[11:0];
            field {
                sw = rw;
            } INILENGTH[15:12];
    } MaximumFrameLength @ 0x10;
    reg {
        name="AddressFilterControl";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EN[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BRDCST00EN[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BRDCSTFFEN[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADDRESS[15:8];
    } AddressFilterControl @ 0x14;
    reg {
        name="FrameControllerDataBuffer";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DATABUFFER[7:0];
    } FrameControllerDataBuffer @ 0x18;
    reg {
        name="WordCounter";
        regwidth=0x20;
            field {
                sw = r;
            } WCNT[11:0];
    } WordCounter @ 0x1c;
    reg {
        name="WordCounterCompare0";
        regwidth=0x20;
            field {
                sw = rw;
            } FRAMELENGTH[11:0];
    } WordCounterCompare0 @ 0x20;
    reg {
        name="WordCounterCompare1";
        regwidth=0x20;
            field {
                sw = rw;
            } LENGTHFIELDLOC[11:0];
    } WordCounterCompare1 @ 0x24;
    reg {
        name="WordCounterCompare2";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADDRFIELDLOC[11:0];
    } WordCounterCompare2 @ 0x28;
    reg {
        name="Command";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } RXABORT[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMEDETRESUME[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEWRITERESUME[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEREADRESUME[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CONVRESUME[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CONVTERMINATE[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXSUBFRAMERESUME[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEINIT[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVECNTCLEAR[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CONVINIT[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BLOCKINIT[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } STATEINIT[11:11];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } RXRAWUNBLOCK[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXPAUSERESUME[13:13];
    } Command @ 0x2c;
    reg {
        name="WhitenerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerControl @ 0x30;
    reg {
        name="WhitenerPolynomial";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerPolynomial @ 0x34;
    reg {
        name="WhitenerInitialValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerInitialValue @ 0x38;
    reg {
        name="ForwardErrorCorrectionControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ForwardErrorCorrectionControl @ 0x3c;
    reg {
        name="BlockDecodingRamAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BlockDecodingRamAddress @ 0x40;
    reg {
        name="ConvolutionalDecodingRamAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConvolutionalDecodingRamAddress @ 0x44;
    reg {
        name="Control";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RANDOMTX[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } UARTMODE[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BITORDER[2:2];
            field {
                sw = rw;
            } TXFCDMODE[5:4];
            field {
                sw = rw;
            } RXFCDMODE[7:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BITSPERWORD[10:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RATESELECT[12:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXPREFETCH[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXFETCHBLOCKING[14:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SEQHANDSHAKE[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRBSTEST[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LPMODEDIS[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WAITEOFEN[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXABORTIGNOREDIS[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SKIPTXTRAILDATAWHITEN[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SKIPRXSUPSTATEWHITEN[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HOLDTXTRAILDATAACTIVE[26:26];
    } Control @ 0x48;
    reg {
        name="RxControl";
        regwidth=0x20;
            field {
                sw = rw;
            } STORECRC[0:0];
            field {
                sw = rw;
            } ACCEPTCRCERRORS[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ACCEPTBLOCKERRORS[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TRACKABFRAME[3:3];
            field {
                sw = rw;
            } BUFCLEAR[4:4];
            field {
                sw = rw;
            } BUFRESTOREFRAMEERROR[5:5];
            field {
                sw = rw;
            } BUFRESTORERXABORTED[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXFRAMEENDAHEADBYTES[10:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ACCEPTUARTERRORS[11:11];
    } RxControl @ 0x4c;
    reg {
        name="TrailingTxDataControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrailingTxDataControl @ 0x50;
    reg {
        name="TrailingRxData";
        regwidth=0x20;
            field {
                sw = rw;
            } RSSI[0:0];
            field {
                sw = rw;
            } CRCOK[1:1];
            field {
                sw = rw;
            } PROTIMERCC0BASE[2:2];
            field {
                sw = rw;
            } PROTIMERCC0WRAPL[3:3];
            field {
                sw = rw;
            } PROTIMERCC0WRAPH[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RTCSTAMP[5:5];
    } TrailingRxData @ 0x54;
    reg {
        name="SubFrameCounterValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SubFrameCounterValue @ 0x58;
    reg {
        name="ConvolutionalCoderGeneratorPolynomials";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConvolutionalCoderGeneratorPolynomials @ 0x5c;
    reg {
        name="PuncturingControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PuncturingControl @ 0x60;
    reg {
        name="PauseControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PauseControl @ 0x64;
    reg {
        name="InterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXDONEIF[0:0];
            field {
                sw = rw;
            } TXAFTERFRAMEDONEIF[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXABORTEDIF[2:2];
            field {
                sw = rw;
            } TXUFIF[3:3];
            field {
                sw = rw;
            } RXDONEIF[4:4];
            field {
                sw = rw;
            } RXABORTEDIF[5:5];
            field {
                sw = rw;
            } FRAMEERRORIF[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BLOCKERRORIF[7:7];
            field {
                sw = rw;
            } RXOFIF[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP0IF[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP1IF[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP2IF[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADDRERRORIF[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BUSERRORIF[13:13];
            field {
                sw = rw;
            } RXRAWEVENTIF[14:14];
            field {
                sw = rw;
            } TXRAWEVENTIF[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SNIFFOFIF[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP3IF[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP4IF[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BOISETIF[19:19];
            field {
                sw = rw;
            } PKTBUFSTARTIF[20:20];
            field {
                sw = rw;
            } PKTBUFTHRESHOLDIF[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRAWOFIF[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP5IF[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMEDETPAUSEDIF[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEWRITEPAUSEDIF[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEREADPAUSEDIF[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXSUBFRAMEPAUSEDIF[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CONVPAUSEDIF[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXWORDIF[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXWORDIF[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } UARTERRORIF[31:31];
    } InterruptFlags @ 0x68;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXDONEIEN[0:0];
            field {
                sw = rw;
            } TXAFTERFRAMEDONEIEN[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXABORTEDIEN[2:2];
            field {
                sw = rw;
            } TXUFIEN[3:3];
            field {
                sw = rw;
            } RXDONEIEN[4:4];
            field {
                sw = rw;
            } RXABORTEDIEN[5:5];
            field {
                sw = rw;
            } FRAMEERRORIEN[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BLOCKERRORIEN[7:7];
            field {
                sw = rw;
            } RXOFIEN[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP0IEN[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP1IEN[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP2IEN[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADDRERRORIEN[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BUSERRORIEN[13:13];
            field {
                sw = rw;
            } RXRAWEVENTIEN[14:14];
            field {
                sw = rw;
            } TXRAWEVENTIEN[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SNIFFOFIEN[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP3IEN[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP4IEN[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BOISETIEN[19:19];
            field {
                sw = rw;
            } PKTBUFSTARTIEN[20:20];
            field {
                sw = rw;
            } PKTBUFTHRESHOLDIEN[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRAWOFIEN[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP5IEN[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMEDETPAUSEDIEN[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEWRITEPAUSEDIEN[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEREADPAUSEDIEN[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXSUBFRAMEPAUSEDIEN[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CONVPAUSEDIEN[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXWORDIEN[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXWORDIEN[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } UARTERRORIEN[31:31];
    } InterruptEnable @ 0x6c;
    reg {
        name="OverTheAirNumberOfBitsCounter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OverTheAirNumberOfBitsCounter @ 0x70;
    reg {
        name="BufferControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BufferControl @ 0x78;
    reg {
        name="SnifferControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SnifferControl @ 0x84;
    reg {
        name="AuxiliarySnifferDataOutput";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliarySnifferDataOutput @ 0x88;
    reg {
        name="RawDataControl";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXRAWMODE[1:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } RXRAWMODE[4:2];
            field {
                sw = rw;
            } RXRAWRANDOM[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } RXRAWTRIGGER[8:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEMODRAWDATAMUX[13:13];
    } RawDataControl @ 0x8c;
    reg {
        name="RxRawData";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RXRAWDATA[31:0];
    } RxRawData @ 0x90;
    reg {
        name="RxPauseData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxPauseData @ 0x94;
    reg {
        name="MostLikelyConvolutionalDecoderState";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MostLikelyConvolutionalDecoderState @ 0x98;
    reg {
        name="InterleaverElementValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue @ 0x9c;
    reg {
        name="InterleaverWritePointer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverWritePointer @ 0xa0;
    reg {
        name="InterleaverReadPointer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverReadPointer @ 0xa4;
    reg {
        name="AutomaticClockGating";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGating @ 0xa8;
    reg {
        name="AutomaticClockGatingClockStop";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGatingClockStop @ 0xac;
    reg {
        name="SequencerInterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXDONESEQIF[0:0];
            field {
                sw = rw;
            } TXAFTERFRAMEDONESEQIF[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXABORTEDSEQIF[2:2];
            field {
                sw = rw;
            } TXUFSEQIF[3:3];
            field {
                sw = rw;
            } RXDONESEQIF[4:4];
            field {
                sw = rw;
            } RXABORTEDSEQIF[5:5];
            field {
                sw = rw;
            } FRAMEERRORSEQIF[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BLOCKERRORSEQIF[7:7];
            field {
                sw = rw;
            } RXOFSEQIF[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP0SEQIF[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP1SEQIF[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP2SEQIF[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADDRERRORSEQIF[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BUSERRORSEQIF[13:13];
            field {
                sw = rw;
            } RXRAWEVENTSEQIF[14:14];
            field {
                sw = rw;
            } TXRAWEVENTSEQIF[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SNIFFOFSEQIF[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP3SEQIF[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP4SEQIF[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BOISETSEQIF[19:19];
            field {
                sw = rw;
            } PKTBUFSTARTSEQIF[20:20];
            field {
                sw = rw;
            } PKTBUFTHRESHOLDSEQIF[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRAWOFSEQIF[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP5SEQIF[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMEDETPAUSEDSEQIF[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEWRITEPAUSEDSEQIF[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEREADPAUSEDSEQIF[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXSUBFRAMEPAUSEDSEQIF[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CONVPAUSEDSEQIF[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXWORDSEQIF[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXWORDSEQIF[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } UARTERRORSEQIF[31:31];
    } SequencerInterruptFlags @ 0xb4;
    reg {
        name="SequencerInterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXDONESEQIEN[0:0];
            field {
                sw = rw;
            } TXAFTERFRAMEDONESEQIEN[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXABORTEDSEQIEN[2:2];
            field {
                sw = rw;
            } TXUFSEQIEN[3:3];
            field {
                sw = rw;
            } RXDONESEQIEN[4:4];
            field {
                sw = rw;
            } RXABORTEDSEQIEN[5:5];
            field {
                sw = rw;
            } FRAMEERRORSEQIEN[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BLOCKERRORSEQIEN[7:7];
            field {
                sw = rw;
            } RXOFSEQIEN[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP0SEQIEN[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP1SEQIEN[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP2SEQIEN[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADDRERRORSEQIEN[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BUSERRORSEQIEN[13:13];
            field {
                sw = rw;
            } RXRAWEVENTSEQIEN[14:14];
            field {
                sw = rw;
            } TXRAWEVENTSEQIEN[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SNIFFOFSEQIEN[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP3SEQIEN[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP4SEQIEN[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BOISETSEQIEN[19:19];
            field {
                sw = rw;
            } PKTBUFSTARTSEQIEN[20:20];
            field {
                sw = rw;
            } PKTBUFTHRESHOLDSEQIEN[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRAWOFSEQIEN[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WCNTCMP5SEQIEN[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMEDETPAUSEDSEQIEN[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEWRITEPAUSEDSEQIEN[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INTERLEAVEREADPAUSEDSEQIEN[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXSUBFRAMEPAUSEDSEQIEN[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CONVPAUSEDSEQIEN[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXWORDSEQIEN[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXWORDSEQIEN[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } UARTERRORSEQIEN[31:31];
    } SequencerInterruptEnable @ 0xb8;
    reg {
        name="WordCounterCompare3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare3 @ 0xbc;
    reg {
        name="BitOfInterestControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BitOfInterestControl @ 0xc0;
    reg {
        name="DynamicSuppLengthControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DynamicSuppLengthControl @ 0xc4;
    reg {
        name="WordCounterCompare4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare4 @ 0xc8;
    reg {
        name="WordCounterCompare5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare5 @ 0xcc;
    reg {
        name="PacketCaptureBufferControl";
        regwidth=0x20;
            field {
                sw = rw;
            } PKTBUFSTARTLOC[11:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } PKTBUFTHRESHOLD[17:12];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } PKTBUFTHRESHOLDEN[24:24];
            field {
                sw = w;
            } PKTBUFSTOP[25:25];
    } PacketCaptureBufferControl @ 0xd0;
    reg {
        name="PacketCaptureBufferStatus";
        regwidth=0x20;
            field {
                sw = r;
            } PKTBUFCOUNT[5:0];
    } PacketCaptureBufferStatus @ 0xd4;
    reg {
        name="PacketCaptureDataBuffer0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer0 @ 0xd8;
    reg {
        name="PacketCaptureDataBuffer1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer1 @ 0xdc;
    reg {
        name="PacketCaptureDataBuffer2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer2 @ 0xe0;
    reg {
        name="PacketCaptureDataBuffer3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer3 @ 0xe4;
    reg {
        name="PacketCaptureDataBuffer4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer4 @ 0xe8;
    reg {
        name="PacketCaptureDataBuffer5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer5 @ 0xec;
    reg {
        name="PacketCaptureDataBuffer6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer6 @ 0xf0;
    reg {
        name="PacketCaptureDataBuffer7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer7 @ 0xf4;
    reg {
        name="PacketCaptureDataBuffer8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer8 @ 0xf8;
    reg {
        name="PacketCaptureDataBuffer9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer9 @ 0xfc;
    reg {
        name="PacketCaptureDataBuffer10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer10 @ 0x100;
    reg {
        name="PacketCaptureDataBuffer11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer11 @ 0x104;
    reg {
        name="FrameControlDescriptor0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor0 @ 0x108;
    reg {
        name="FrameControlDescriptor1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor1 @ 0x10c;
    reg {
        name="FrameControlDescriptor2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor2 @ 0x110;
    reg {
        name="FrameControlDescriptor3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor3 @ 0x114;
    reg {
        name="InterleaverElementValue0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue0 @ 0x140;
    reg {
        name="InterleaverElementValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue1 @ 0x144;
    reg {
        name="InterleaverElementValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue2 @ 0x148;
    reg {
        name="InterleaverElementValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue3 @ 0x14c;
    reg {
        name="InterleaverElementValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue4 @ 0x150;
    reg {
        name="InterleaverElementValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue5 @ 0x154;
    reg {
        name="InterleaverElementValue6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue6 @ 0x158;
    reg {
        name="InterleaverElementValue7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue7 @ 0x15c;
    reg {
        name="InterleaverElementValue8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue8 @ 0x160;
    reg {
        name="InterleaverElementValue9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue9 @ 0x164;
    reg {
        name="InterleaverElementValue10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue10 @ 0x168;
    reg {
        name="InterleaverElementValue11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue11 @ 0x16c;
    reg {
        name="InterleaverElementValue12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue12 @ 0x170;
    reg {
        name="InterleaverElementValue13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue13 @ 0x174;
    reg {
        name="InterleaverElementValue14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue14 @ 0x178;
    reg {
        name="InterleaverElementValue15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue15 @ 0x17c;
    reg {
        name="AhbConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbConfiguration @ 0x180;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Enable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Set @ 0x1004;
    reg {
        name="Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Set @ 0x1008;
    reg {
        name="DynamicFrameLengthControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DynamicFrameLengthControl_Set @ 0x100c;
    reg {
        name="MaximumFrameLength_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MaximumFrameLength_Set @ 0x1010;
    reg {
        name="AddressFilterControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AddressFilterControl_Set @ 0x1014;
    reg {
        name="FrameControllerDataBuffer_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControllerDataBuffer_Set @ 0x1018;
    reg {
        name="WordCounter_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounter_Set @ 0x101c;
    reg {
        name="WordCounterCompare0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare0_Set @ 0x1020;
    reg {
        name="WordCounterCompare1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare1_Set @ 0x1024;
    reg {
        name="WordCounterCompare2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare2_Set @ 0x1028;
    reg {
        name="Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Set @ 0x102c;
    reg {
        name="WhitenerControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerControl_Set @ 0x1030;
    reg {
        name="WhitenerPolynomial_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerPolynomial_Set @ 0x1034;
    reg {
        name="WhitenerInitialValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerInitialValue_Set @ 0x1038;
    reg {
        name="ForwardErrorCorrectionControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ForwardErrorCorrectionControl_Set @ 0x103c;
    reg {
        name="BlockDecodingRamAddress_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BlockDecodingRamAddress_Set @ 0x1040;
    reg {
        name="ConvolutionalDecodingRamAddress_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConvolutionalDecodingRamAddress_Set @ 0x1044;
    reg {
        name="Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Set @ 0x1048;
    reg {
        name="RxControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxControl_Set @ 0x104c;
    reg {
        name="TrailingTxDataControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrailingTxDataControl_Set @ 0x1050;
    reg {
        name="TrailingRxData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrailingRxData_Set @ 0x1054;
    reg {
        name="SubFrameCounterValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SubFrameCounterValue_Set @ 0x1058;
    reg {
        name="ConvolutionalCoderGeneratorPolynomials_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConvolutionalCoderGeneratorPolynomials_Set @ 0x105c;
    reg {
        name="PuncturingControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PuncturingControl_Set @ 0x1060;
    reg {
        name="PauseControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PauseControl_Set @ 0x1064;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x1068;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x106c;
    reg {
        name="OverTheAirNumberOfBitsCounter_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OverTheAirNumberOfBitsCounter_Set @ 0x1070;
    reg {
        name="BufferControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BufferControl_Set @ 0x1078;
    reg {
        name="SnifferControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SnifferControl_Set @ 0x1084;
    reg {
        name="AuxiliarySnifferDataOutput_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliarySnifferDataOutput_Set @ 0x1088;
    reg {
        name="RawDataControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RawDataControl_Set @ 0x108c;
    reg {
        name="RxRawData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxRawData_Set @ 0x1090;
    reg {
        name="RxPauseData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxPauseData_Set @ 0x1094;
    reg {
        name="MostLikelyConvolutionalDecoderState_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MostLikelyConvolutionalDecoderState_Set @ 0x1098;
    reg {
        name="InterleaverElementValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue_Set @ 0x109c;
    reg {
        name="InterleaverWritePointer_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverWritePointer_Set @ 0x10a0;
    reg {
        name="InterleaverReadPointer_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverReadPointer_Set @ 0x10a4;
    reg {
        name="AutomaticClockGating_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGating_Set @ 0x10a8;
    reg {
        name="AutomaticClockGatingClockStop_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGatingClockStop_Set @ 0x10ac;
    reg {
        name="SequencerInterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Set @ 0x10b4;
    reg {
        name="SequencerInterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Set @ 0x10b8;
    reg {
        name="WordCounterCompare3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare3_Set @ 0x10bc;
    reg {
        name="BitOfInterestControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BitOfInterestControl_Set @ 0x10c0;
    reg {
        name="DynamicSuppLengthControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DynamicSuppLengthControl_Set @ 0x10c4;
    reg {
        name="WordCounterCompare4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare4_Set @ 0x10c8;
    reg {
        name="WordCounterCompare5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare5_Set @ 0x10cc;
    reg {
        name="PacketCaptureBufferControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureBufferControl_Set @ 0x10d0;
    reg {
        name="PacketCaptureBufferStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureBufferStatus_Set @ 0x10d4;
    reg {
        name="PacketCaptureDataBuffer0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer0_Set @ 0x10d8;
    reg {
        name="PacketCaptureDataBuffer1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer1_Set @ 0x10dc;
    reg {
        name="PacketCaptureDataBuffer2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer2_Set @ 0x10e0;
    reg {
        name="PacketCaptureDataBuffer3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer3_Set @ 0x10e4;
    reg {
        name="PacketCaptureDataBuffer4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer4_Set @ 0x10e8;
    reg {
        name="PacketCaptureDataBuffer5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer5_Set @ 0x10ec;
    reg {
        name="PacketCaptureDataBuffer6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer6_Set @ 0x10f0;
    reg {
        name="PacketCaptureDataBuffer7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer7_Set @ 0x10f4;
    reg {
        name="PacketCaptureDataBuffer8_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer8_Set @ 0x10f8;
    reg {
        name="PacketCaptureDataBuffer9_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer9_Set @ 0x10fc;
    reg {
        name="PacketCaptureDataBuffer10_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer10_Set @ 0x1100;
    reg {
        name="PacketCaptureDataBuffer11_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer11_Set @ 0x1104;
    reg {
        name="FrameControlDescriptor0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor0_Set @ 0x1108;
    reg {
        name="FrameControlDescriptor1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor1_Set @ 0x110c;
    reg {
        name="FrameControlDescriptor2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor2_Set @ 0x1110;
    reg {
        name="FrameControlDescriptor3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor3_Set @ 0x1114;
    reg {
        name="InterleaverElementValue0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue0_Set @ 0x1140;
    reg {
        name="InterleaverElementValue1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue1_Set @ 0x1144;
    reg {
        name="InterleaverElementValue2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue2_Set @ 0x1148;
    reg {
        name="InterleaverElementValue3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue3_Set @ 0x114c;
    reg {
        name="InterleaverElementValue4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue4_Set @ 0x1150;
    reg {
        name="InterleaverElementValue5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue5_Set @ 0x1154;
    reg {
        name="InterleaverElementValue6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue6_Set @ 0x1158;
    reg {
        name="InterleaverElementValue7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue7_Set @ 0x115c;
    reg {
        name="InterleaverElementValue8_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue8_Set @ 0x1160;
    reg {
        name="InterleaverElementValue9_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue9_Set @ 0x1164;
    reg {
        name="InterleaverElementValue10_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue10_Set @ 0x1168;
    reg {
        name="InterleaverElementValue11_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue11_Set @ 0x116c;
    reg {
        name="InterleaverElementValue12_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue12_Set @ 0x1170;
    reg {
        name="InterleaverElementValue13_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue13_Set @ 0x1174;
    reg {
        name="InterleaverElementValue14_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue14_Set @ 0x1178;
    reg {
        name="InterleaverElementValue15_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue15_Set @ 0x117c;
    reg {
        name="AhbConfiguration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbConfiguration_Set @ 0x1180;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Enable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Clr @ 0x2004;
    reg {
        name="Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Clr @ 0x2008;
    reg {
        name="DynamicFrameLengthControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DynamicFrameLengthControl_Clr @ 0x200c;
    reg {
        name="MaximumFrameLength_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MaximumFrameLength_Clr @ 0x2010;
    reg {
        name="AddressFilterControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AddressFilterControl_Clr @ 0x2014;
    reg {
        name="FrameControllerDataBuffer_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControllerDataBuffer_Clr @ 0x2018;
    reg {
        name="WordCounter_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounter_Clr @ 0x201c;
    reg {
        name="WordCounterCompare0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare0_Clr @ 0x2020;
    reg {
        name="WordCounterCompare1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare1_Clr @ 0x2024;
    reg {
        name="WordCounterCompare2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare2_Clr @ 0x2028;
    reg {
        name="Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Clr @ 0x202c;
    reg {
        name="WhitenerControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerControl_Clr @ 0x2030;
    reg {
        name="WhitenerPolynomial_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerPolynomial_Clr @ 0x2034;
    reg {
        name="WhitenerInitialValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerInitialValue_Clr @ 0x2038;
    reg {
        name="ForwardErrorCorrectionControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ForwardErrorCorrectionControl_Clr @ 0x203c;
    reg {
        name="BlockDecodingRamAddress_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BlockDecodingRamAddress_Clr @ 0x2040;
    reg {
        name="ConvolutionalDecodingRamAddress_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConvolutionalDecodingRamAddress_Clr @ 0x2044;
    reg {
        name="Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Clr @ 0x2048;
    reg {
        name="RxControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxControl_Clr @ 0x204c;
    reg {
        name="TrailingTxDataControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrailingTxDataControl_Clr @ 0x2050;
    reg {
        name="TrailingRxData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrailingRxData_Clr @ 0x2054;
    reg {
        name="SubFrameCounterValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SubFrameCounterValue_Clr @ 0x2058;
    reg {
        name="ConvolutionalCoderGeneratorPolynomials_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConvolutionalCoderGeneratorPolynomials_Clr @ 0x205c;
    reg {
        name="PuncturingControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PuncturingControl_Clr @ 0x2060;
    reg {
        name="PauseControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PauseControl_Clr @ 0x2064;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x2068;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x206c;
    reg {
        name="OverTheAirNumberOfBitsCounter_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OverTheAirNumberOfBitsCounter_Clr @ 0x2070;
    reg {
        name="BufferControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BufferControl_Clr @ 0x2078;
    reg {
        name="SnifferControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SnifferControl_Clr @ 0x2084;
    reg {
        name="AuxiliarySnifferDataOutput_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliarySnifferDataOutput_Clr @ 0x2088;
    reg {
        name="RawDataControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RawDataControl_Clr @ 0x208c;
    reg {
        name="RxRawData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxRawData_Clr @ 0x2090;
    reg {
        name="RxPauseData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxPauseData_Clr @ 0x2094;
    reg {
        name="MostLikelyConvolutionalDecoderState_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MostLikelyConvolutionalDecoderState_Clr @ 0x2098;
    reg {
        name="InterleaverElementValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue_Clr @ 0x209c;
    reg {
        name="InterleaverWritePointer_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverWritePointer_Clr @ 0x20a0;
    reg {
        name="InterleaverReadPointer_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverReadPointer_Clr @ 0x20a4;
    reg {
        name="AutomaticClockGating_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGating_Clr @ 0x20a8;
    reg {
        name="AutomaticClockGatingClockStop_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGatingClockStop_Clr @ 0x20ac;
    reg {
        name="SequencerInterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Clr @ 0x20b4;
    reg {
        name="SequencerInterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Clr @ 0x20b8;
    reg {
        name="WordCounterCompare3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare3_Clr @ 0x20bc;
    reg {
        name="BitOfInterestControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BitOfInterestControl_Clr @ 0x20c0;
    reg {
        name="DynamicSuppLengthControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DynamicSuppLengthControl_Clr @ 0x20c4;
    reg {
        name="WordCounterCompare4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare4_Clr @ 0x20c8;
    reg {
        name="WordCounterCompare5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare5_Clr @ 0x20cc;
    reg {
        name="PacketCaptureBufferControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureBufferControl_Clr @ 0x20d0;
    reg {
        name="PacketCaptureBufferStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureBufferStatus_Clr @ 0x20d4;
    reg {
        name="PacketCaptureDataBuffer0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer0_Clr @ 0x20d8;
    reg {
        name="PacketCaptureDataBuffer1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer1_Clr @ 0x20dc;
    reg {
        name="PacketCaptureDataBuffer2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer2_Clr @ 0x20e0;
    reg {
        name="PacketCaptureDataBuffer3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer3_Clr @ 0x20e4;
    reg {
        name="PacketCaptureDataBuffer4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer4_Clr @ 0x20e8;
    reg {
        name="PacketCaptureDataBuffer5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer5_Clr @ 0x20ec;
    reg {
        name="PacketCaptureDataBuffer6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer6_Clr @ 0x20f0;
    reg {
        name="PacketCaptureDataBuffer7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer7_Clr @ 0x20f4;
    reg {
        name="PacketCaptureDataBuffer8_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer8_Clr @ 0x20f8;
    reg {
        name="PacketCaptureDataBuffer9_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer9_Clr @ 0x20fc;
    reg {
        name="PacketCaptureDataBuffer10_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer10_Clr @ 0x2100;
    reg {
        name="PacketCaptureDataBuffer11_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer11_Clr @ 0x2104;
    reg {
        name="FrameControlDescriptor0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor0_Clr @ 0x2108;
    reg {
        name="FrameControlDescriptor1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor1_Clr @ 0x210c;
    reg {
        name="FrameControlDescriptor2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor2_Clr @ 0x2110;
    reg {
        name="FrameControlDescriptor3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor3_Clr @ 0x2114;
    reg {
        name="InterleaverElementValue0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue0_Clr @ 0x2140;
    reg {
        name="InterleaverElementValue1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue1_Clr @ 0x2144;
    reg {
        name="InterleaverElementValue2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue2_Clr @ 0x2148;
    reg {
        name="InterleaverElementValue3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue3_Clr @ 0x214c;
    reg {
        name="InterleaverElementValue4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue4_Clr @ 0x2150;
    reg {
        name="InterleaverElementValue5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue5_Clr @ 0x2154;
    reg {
        name="InterleaverElementValue6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue6_Clr @ 0x2158;
    reg {
        name="InterleaverElementValue7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue7_Clr @ 0x215c;
    reg {
        name="InterleaverElementValue8_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue8_Clr @ 0x2160;
    reg {
        name="InterleaverElementValue9_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue9_Clr @ 0x2164;
    reg {
        name="InterleaverElementValue10_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue10_Clr @ 0x2168;
    reg {
        name="InterleaverElementValue11_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue11_Clr @ 0x216c;
    reg {
        name="InterleaverElementValue12_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue12_Clr @ 0x2170;
    reg {
        name="InterleaverElementValue13_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue13_Clr @ 0x2174;
    reg {
        name="InterleaverElementValue14_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue14_Clr @ 0x2178;
    reg {
        name="InterleaverElementValue15_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue15_Clr @ 0x217c;
    reg {
        name="AhbConfiguration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbConfiguration_Clr @ 0x2180;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Enable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Tgl @ 0x3004;
    reg {
        name="Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Tgl @ 0x3008;
    reg {
        name="DynamicFrameLengthControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DynamicFrameLengthControl_Tgl @ 0x300c;
    reg {
        name="MaximumFrameLength_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MaximumFrameLength_Tgl @ 0x3010;
    reg {
        name="AddressFilterControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AddressFilterControl_Tgl @ 0x3014;
    reg {
        name="FrameControllerDataBuffer_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControllerDataBuffer_Tgl @ 0x3018;
    reg {
        name="WordCounter_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounter_Tgl @ 0x301c;
    reg {
        name="WordCounterCompare0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare0_Tgl @ 0x3020;
    reg {
        name="WordCounterCompare1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare1_Tgl @ 0x3024;
    reg {
        name="WordCounterCompare2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare2_Tgl @ 0x3028;
    reg {
        name="Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Tgl @ 0x302c;
    reg {
        name="WhitenerControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerControl_Tgl @ 0x3030;
    reg {
        name="WhitenerPolynomial_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerPolynomial_Tgl @ 0x3034;
    reg {
        name="WhitenerInitialValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WhitenerInitialValue_Tgl @ 0x3038;
    reg {
        name="ForwardErrorCorrectionControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ForwardErrorCorrectionControl_Tgl @ 0x303c;
    reg {
        name="BlockDecodingRamAddress_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BlockDecodingRamAddress_Tgl @ 0x3040;
    reg {
        name="ConvolutionalDecodingRamAddress_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConvolutionalDecodingRamAddress_Tgl @ 0x3044;
    reg {
        name="Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Tgl @ 0x3048;
    reg {
        name="RxControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxControl_Tgl @ 0x304c;
    reg {
        name="TrailingTxDataControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrailingTxDataControl_Tgl @ 0x3050;
    reg {
        name="TrailingRxData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrailingRxData_Tgl @ 0x3054;
    reg {
        name="SubFrameCounterValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SubFrameCounterValue_Tgl @ 0x3058;
    reg {
        name="ConvolutionalCoderGeneratorPolynomials_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConvolutionalCoderGeneratorPolynomials_Tgl @ 0x305c;
    reg {
        name="PuncturingControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PuncturingControl_Tgl @ 0x3060;
    reg {
        name="PauseControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PauseControl_Tgl @ 0x3064;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x3068;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x306c;
    reg {
        name="OverTheAirNumberOfBitsCounter_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OverTheAirNumberOfBitsCounter_Tgl @ 0x3070;
    reg {
        name="BufferControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BufferControl_Tgl @ 0x3078;
    reg {
        name="SnifferControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SnifferControl_Tgl @ 0x3084;
    reg {
        name="AuxiliarySnifferDataOutput_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliarySnifferDataOutput_Tgl @ 0x3088;
    reg {
        name="RawDataControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RawDataControl_Tgl @ 0x308c;
    reg {
        name="RxRawData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxRawData_Tgl @ 0x3090;
    reg {
        name="RxPauseData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxPauseData_Tgl @ 0x3094;
    reg {
        name="MostLikelyConvolutionalDecoderState_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MostLikelyConvolutionalDecoderState_Tgl @ 0x3098;
    reg {
        name="InterleaverElementValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue_Tgl @ 0x309c;
    reg {
        name="InterleaverWritePointer_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverWritePointer_Tgl @ 0x30a0;
    reg {
        name="InterleaverReadPointer_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverReadPointer_Tgl @ 0x30a4;
    reg {
        name="AutomaticClockGating_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGating_Tgl @ 0x30a8;
    reg {
        name="AutomaticClockGatingClockStop_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGatingClockStop_Tgl @ 0x30ac;
    reg {
        name="SequencerInterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Tgl @ 0x30b4;
    reg {
        name="SequencerInterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Tgl @ 0x30b8;
    reg {
        name="WordCounterCompare3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare3_Tgl @ 0x30bc;
    reg {
        name="BitOfInterestControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BitOfInterestControl_Tgl @ 0x30c0;
    reg {
        name="DynamicSuppLengthControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DynamicSuppLengthControl_Tgl @ 0x30c4;
    reg {
        name="WordCounterCompare4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare4_Tgl @ 0x30c8;
    reg {
        name="WordCounterCompare5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WordCounterCompare5_Tgl @ 0x30cc;
    reg {
        name="PacketCaptureBufferControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureBufferControl_Tgl @ 0x30d0;
    reg {
        name="PacketCaptureBufferStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureBufferStatus_Tgl @ 0x30d4;
    reg {
        name="PacketCaptureDataBuffer0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer0_Tgl @ 0x30d8;
    reg {
        name="PacketCaptureDataBuffer1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer1_Tgl @ 0x30dc;
    reg {
        name="PacketCaptureDataBuffer2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer2_Tgl @ 0x30e0;
    reg {
        name="PacketCaptureDataBuffer3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer3_Tgl @ 0x30e4;
    reg {
        name="PacketCaptureDataBuffer4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer4_Tgl @ 0x30e8;
    reg {
        name="PacketCaptureDataBuffer5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer5_Tgl @ 0x30ec;
    reg {
        name="PacketCaptureDataBuffer6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer6_Tgl @ 0x30f0;
    reg {
        name="PacketCaptureDataBuffer7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer7_Tgl @ 0x30f4;
    reg {
        name="PacketCaptureDataBuffer8_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer8_Tgl @ 0x30f8;
    reg {
        name="PacketCaptureDataBuffer9_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer9_Tgl @ 0x30fc;
    reg {
        name="PacketCaptureDataBuffer10_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer10_Tgl @ 0x3100;
    reg {
        name="PacketCaptureDataBuffer11_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PacketCaptureDataBuffer11_Tgl @ 0x3104;
    reg {
        name="FrameControlDescriptor0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor0_Tgl @ 0x3108;
    reg {
        name="FrameControlDescriptor1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor1_Tgl @ 0x310c;
    reg {
        name="FrameControlDescriptor2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor2_Tgl @ 0x3110;
    reg {
        name="FrameControlDescriptor3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlDescriptor3_Tgl @ 0x3114;
    reg {
        name="InterleaverElementValue0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue0_Tgl @ 0x3140;
    reg {
        name="InterleaverElementValue1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue1_Tgl @ 0x3144;
    reg {
        name="InterleaverElementValue2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue2_Tgl @ 0x3148;
    reg {
        name="InterleaverElementValue3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue3_Tgl @ 0x314c;
    reg {
        name="InterleaverElementValue4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue4_Tgl @ 0x3150;
    reg {
        name="InterleaverElementValue5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue5_Tgl @ 0x3154;
    reg {
        name="InterleaverElementValue6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue6_Tgl @ 0x3158;
    reg {
        name="InterleaverElementValue7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue7_Tgl @ 0x315c;
    reg {
        name="InterleaverElementValue8_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue8_Tgl @ 0x3160;
    reg {
        name="InterleaverElementValue9_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue9_Tgl @ 0x3164;
    reg {
        name="InterleaverElementValue10_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue10_Tgl @ 0x3168;
    reg {
        name="InterleaverElementValue11_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue11_Tgl @ 0x316c;
    reg {
        name="InterleaverElementValue12_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue12_Tgl @ 0x3170;
    reg {
        name="InterleaverElementValue13_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue13_Tgl @ 0x3174;
    reg {
        name="InterleaverElementValue14_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue14_Tgl @ 0x3178;
    reg {
        name="InterleaverElementValue15_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterleaverElementValue15_Tgl @ 0x317c;
    reg {
        name="AhbConfiguration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbConfiguration_Tgl @ 0x3180;
} FrameControllerRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion @ 0x0;
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x4;
    reg {
        name="LowPowerMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPowerMode @ 0x8;
    reg {
        name="Buffer0Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Control @ 0xc;
    reg {
        name="Buffer0Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Address @ 0x10;
    reg {
        name="Buffer0WriteOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteOffset @ 0x14;
    reg {
        name="Buffer0ReadOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadOffset @ 0x18;
    reg {
        name="Buffer0WriteStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteStart @ 0x1c;
    reg {
        name="Buffer0ReadData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadData @ 0x20;
    reg {
        name="Buffer0WriteData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteData @ 0x24;
    reg {
        name="Buffer0XorWrite";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0XorWrite @ 0x28;
    reg {
        name="Buffer0Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Status @ 0x2c;
    reg {
        name="Buffer0ThresholdControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ThresholdControl @ 0x30;
    reg {
        name="Buffer0Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Command @ 0x34;
    reg {
        name="Buffer0FifoAsync";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0FifoAsync @ 0x38;
    reg {
        name="Buffer0ReadData32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadData32 @ 0x3c;
    reg {
        name="Buffer0WriteData32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteData32 @ 0x40;
    reg {
        name="Buffer0XorWrite32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0XorWrite32 @ 0x44;
    reg {
        name="Buffer1Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Control @ 0x4c;
    reg {
        name="Buffer1Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Address @ 0x50;
    reg {
        name="Buffer1WriteOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteOffset @ 0x54;
    reg {
        name="Buffer1ReadOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadOffset @ 0x58;
    reg {
        name="Buffer1WriteStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteStart @ 0x5c;
    reg {
        name="Buffer1ReadData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadData @ 0x60;
    reg {
        name="Buffer1WriteData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteData @ 0x64;
    reg {
        name="Buffer1XorWrite";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1XorWrite @ 0x68;
    reg {
        name="Buffer1Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Status @ 0x6c;
    reg {
        name="Buffer1ThresholdControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ThresholdControl @ 0x70;
    reg {
        name="Buffer1Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Command @ 0x74;
    reg {
        name="Buffer1FifoAsync";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1FifoAsync @ 0x78;
    reg {
        name="Buffer1ReadData32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadData32 @ 0x7c;
    reg {
        name="Buffer1WriteData32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteData32 @ 0x80;
    reg {
        name="Buffer1XorWrite32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1XorWrite32 @ 0x84;
    reg {
        name="Buffer2Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Control @ 0x8c;
    reg {
        name="Buffer2Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Address @ 0x90;
    reg {
        name="Buffer2WriteOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteOffset @ 0x94;
    reg {
        name="Buffer2ReadOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadOffset @ 0x98;
    reg {
        name="Buffer2WriteStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteStart @ 0x9c;
    reg {
        name="Buffer2ReadData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadData @ 0xa0;
    reg {
        name="Buffer2WriteData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteData @ 0xa4;
    reg {
        name="Buffer2XorWrite";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2XorWrite @ 0xa8;
    reg {
        name="Buffer2Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Status @ 0xac;
    reg {
        name="Buffer2ThresholdControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ThresholdControl @ 0xb0;
    reg {
        name="Buffer2Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Command @ 0xb4;
    reg {
        name="Buffer2FifoAsync";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2FifoAsync @ 0xb8;
    reg {
        name="Buffer2ReadData32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadData32 @ 0xbc;
    reg {
        name="Buffer2WriteData32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteData32 @ 0xc0;
    reg {
        name="Buffer2XorWrite32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2XorWrite32 @ 0xc4;
    reg {
        name="Buffer3Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Control @ 0xcc;
    reg {
        name="Buffer3Address";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Address @ 0xd0;
    reg {
        name="Buffer3WriteOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteOffset @ 0xd4;
    reg {
        name="Buffer3ReadOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadOffset @ 0xd8;
    reg {
        name="Buffer3WriteStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteStart @ 0xdc;
    reg {
        name="Buffer3ReadData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadData @ 0xe0;
    reg {
        name="Buffer3WriteData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteData @ 0xe4;
    reg {
        name="Buffer3XorWrite";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3XorWrite @ 0xe8;
    reg {
        name="Buffer3Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Status @ 0xec;
    reg {
        name="Buffer3ThresholdControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ThresholdControl @ 0xf0;
    reg {
        name="Buffer3Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Command @ 0xf4;
    reg {
        name="Buffer3FifoAsync";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3FifoAsync @ 0xf8;
    reg {
        name="Buffer3ReadData32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadData32 @ 0xfc;
    reg {
        name="Buffer3WriteData32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteData32 @ 0x100;
    reg {
        name="Buffer3XorWrite32";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3XorWrite32 @ 0x104;
    reg {
        name="InterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } BUF0OFIF[0:0];
            field {
                sw = rw;
            } BUF0UFIF[1:1];
            field {
                sw = rw;
            } BUF0THRIF[2:2];
            field {
                sw = rw;
            } BUF0CORRIF[3:3];
            field {
                sw = rw;
            } BUF0NWAIF[4:4];
            field {
                sw = rw;
            } BUF1OFIF[8:8];
            field {
                sw = rw;
            } BUF1UFIF[9:9];
            field {
                sw = rw;
            } BUF1THRIF[10:10];
            field {
                sw = rw;
            } BUF1CORRIF[11:11];
            field {
                sw = rw;
            } BUF1NWAIF[12:12];
            field {
                sw = rw;
            } BUF2OFIF[16:16];
            field {
                sw = rw;
            } BUF2UFIF[17:17];
            field {
                sw = rw;
            } BUF2THRIF[18:18];
            field {
                sw = rw;
            } BUF2CORRIF[19:19];
            field {
                sw = rw;
            } BUF2NWAIF[20:20];
            field {
                sw = rw;
            } BUF3OFIF[24:24];
            field {
                sw = rw;
            } BUF3UFIF[25:25];
            field {
                sw = rw;
            } BUF3THRIF[26:26];
            field {
                sw = rw;
            } BUF3CORRIF[27:27];
            field {
                sw = rw;
            } BUF3NWAIF[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BUSERRORIF[31:31];
    } InterruptFlags @ 0x114;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } BUF0OFIEN[0:0];
            field {
                sw = rw;
            } BUF0UFIEN[1:1];
            field {
                sw = rw;
            } BUF0THRIEN[2:2];
            field {
                sw = rw;
            } BUF0CORRIEN[3:3];
            field {
                sw = rw;
            } BUF0NWAIEN[4:4];
            field {
                sw = rw;
            } BUF1OFIEN[8:8];
            field {
                sw = rw;
            } BUF1UFIEN[9:9];
            field {
                sw = rw;
            } BUF1THRIEN[10:10];
            field {
                sw = rw;
            } BUF1CORRIEN[11:11];
            field {
                sw = rw;
            } BUF1NWAIEN[12:12];
            field {
                sw = rw;
            } BUF2OFIEN[16:16];
            field {
                sw = rw;
            } BUF2UFIEN[17:17];
            field {
                sw = rw;
            } BUF2THRIEN[18:18];
            field {
                sw = rw;
            } BUF2CORRIEN[19:19];
            field {
                sw = rw;
            } BUF2NWAIEN[20:20];
            field {
                sw = rw;
            } BUF3OFIEN[24:24];
            field {
                sw = rw;
            } BUF3UFIEN[25:25];
            field {
                sw = rw;
            } BUF3THRIEN[26:26];
            field {
                sw = rw;
            } BUF3CORRIEN[27:27];
            field {
                sw = rw;
            } BUF3NWAIEN[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BUSERRORIEN[31:31];
    } InterruptEnable @ 0x118;
    reg {
        name="SequencerInterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } BUF0OFSEQIF[0:0];
            field {
                sw = rw;
            } BUF0UFSEQIF[1:1];
            field {
                sw = rw;
            } BUF0THRSEQIF[2:2];
            field {
                sw = rw;
            } BUF0CORRSEQIF[3:3];
            field {
                sw = rw;
            } BUF0NWASEQIF[4:4];
            field {
                sw = rw;
            } BUF1OFSEQIF[8:8];
            field {
                sw = rw;
            } BUF1UFSEQIF[9:9];
            field {
                sw = rw;
            } BUF1THRSEQIF[10:10];
            field {
                sw = rw;
            } BUF1CORRSEQIF[11:11];
            field {
                sw = rw;
            } BUF1NWASEQIF[12:12];
            field {
                sw = rw;
            } BUF2OFSEQIF[16:16];
            field {
                sw = rw;
            } BUF2UFSEQIF[17:17];
            field {
                sw = rw;
            } BUF2THRSEQIF[18:18];
            field {
                sw = rw;
            } BUF2CORRSEQIF[19:19];
            field {
                sw = rw;
            } BUF2NWASEQIF[20:20];
            field {
                sw = rw;
            } BUF3OFSEQIF[24:24];
            field {
                sw = rw;
            } BUF3UFSEQIF[25:25];
            field {
                sw = rw;
            } BUF3THRSEQIF[26:26];
            field {
                sw = rw;
            } BUF3CORRSEQIF[27:27];
            field {
                sw = rw;
            } BUF3NWASEQIF[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BUSERRORSEQIF[31:31];
    } SequencerInterruptFlags @ 0x11c;
    reg {
        name="SequencerInterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } BUF0OFSEQIEN[0:0];
            field {
                sw = rw;
            } BUF0UFSEQIEN[1:1];
            field {
                sw = rw;
            } BUF0THRSEQIEN[2:2];
            field {
                sw = rw;
            } BUF0CORRSEQIEN[3:3];
            field {
                sw = rw;
            } BUF0NWASEQIEN[4:4];
            field {
                sw = rw;
            } BUF1OFSEQIEN[8:8];
            field {
                sw = rw;
            } BUF1UFSEQIEN[9:9];
            field {
                sw = rw;
            } BUF1THRSEQIEN[10:10];
            field {
                sw = rw;
            } BUF1CORRSEQIEN[11:11];
            field {
                sw = rw;
            } BUF1NWASEQIEN[12:12];
            field {
                sw = rw;
            } BUF2OFSEQIEN[16:16];
            field {
                sw = rw;
            } BUF2UFSEQIEN[17:17];
            field {
                sw = rw;
            } BUF2THRSEQIEN[18:18];
            field {
                sw = rw;
            } BUF2CORRSEQIEN[19:19];
            field {
                sw = rw;
            } BUF2NWASEQIEN[20:20];
            field {
                sw = rw;
            } BUF3OFSEQIEN[24:24];
            field {
                sw = rw;
            } BUF3UFSEQIEN[25:25];
            field {
                sw = rw;
            } BUF3THRSEQIEN[26:26];
            field {
                sw = rw;
            } BUF3CORRSEQIEN[27:27];
            field {
                sw = rw;
            } BUF3NWASEQIEN[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BUSERRORSEQIEN[31:31];
    } SequencerInterruptEnable @ 0x120;
    reg {
        name="AhbConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbConfiguration @ 0x124;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Enable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Set @ 0x1004;
    reg {
        name="LowPowerMode_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPowerMode_Set @ 0x1008;
    reg {
        name="Buffer0Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Control_Set @ 0x100c;
    reg {
        name="Buffer0Address_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Address_Set @ 0x1010;
    reg {
        name="Buffer0WriteOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteOffset_Set @ 0x1014;
    reg {
        name="Buffer0ReadOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadOffset_Set @ 0x1018;
    reg {
        name="Buffer0WriteStart_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteStart_Set @ 0x101c;
    reg {
        name="Buffer0ReadData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadData_Set @ 0x1020;
    reg {
        name="Buffer0WriteData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteData_Set @ 0x1024;
    reg {
        name="Buffer0XorWrite_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0XorWrite_Set @ 0x1028;
    reg {
        name="Buffer0Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Status_Set @ 0x102c;
    reg {
        name="Buffer0ThresholdControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ThresholdControl_Set @ 0x1030;
    reg {
        name="Buffer0Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Command_Set @ 0x1034;
    reg {
        name="Buffer0FifoAsync_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0FifoAsync_Set @ 0x1038;
    reg {
        name="Buffer0ReadData32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadData32_Set @ 0x103c;
    reg {
        name="Buffer0WriteData32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteData32_Set @ 0x1040;
    reg {
        name="Buffer0XorWrite32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0XorWrite32_Set @ 0x1044;
    reg {
        name="Buffer1Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Control_Set @ 0x104c;
    reg {
        name="Buffer1Address_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Address_Set @ 0x1050;
    reg {
        name="Buffer1WriteOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteOffset_Set @ 0x1054;
    reg {
        name="Buffer1ReadOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadOffset_Set @ 0x1058;
    reg {
        name="Buffer1WriteStart_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteStart_Set @ 0x105c;
    reg {
        name="Buffer1ReadData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadData_Set @ 0x1060;
    reg {
        name="Buffer1WriteData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteData_Set @ 0x1064;
    reg {
        name="Buffer1XorWrite_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1XorWrite_Set @ 0x1068;
    reg {
        name="Buffer1Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Status_Set @ 0x106c;
    reg {
        name="Buffer1ThresholdControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ThresholdControl_Set @ 0x1070;
    reg {
        name="Buffer1Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Command_Set @ 0x1074;
    reg {
        name="Buffer1FifoAsync_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1FifoAsync_Set @ 0x1078;
    reg {
        name="Buffer1ReadData32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadData32_Set @ 0x107c;
    reg {
        name="Buffer1WriteData32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteData32_Set @ 0x1080;
    reg {
        name="Buffer1XorWrite32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1XorWrite32_Set @ 0x1084;
    reg {
        name="Buffer2Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Control_Set @ 0x108c;
    reg {
        name="Buffer2Address_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Address_Set @ 0x1090;
    reg {
        name="Buffer2WriteOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteOffset_Set @ 0x1094;
    reg {
        name="Buffer2ReadOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadOffset_Set @ 0x1098;
    reg {
        name="Buffer2WriteStart_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteStart_Set @ 0x109c;
    reg {
        name="Buffer2ReadData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadData_Set @ 0x10a0;
    reg {
        name="Buffer2WriteData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteData_Set @ 0x10a4;
    reg {
        name="Buffer2XorWrite_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2XorWrite_Set @ 0x10a8;
    reg {
        name="Buffer2Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Status_Set @ 0x10ac;
    reg {
        name="Buffer2ThresholdControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ThresholdControl_Set @ 0x10b0;
    reg {
        name="Buffer2Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Command_Set @ 0x10b4;
    reg {
        name="Buffer2FifoAsync_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2FifoAsync_Set @ 0x10b8;
    reg {
        name="Buffer2ReadData32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadData32_Set @ 0x10bc;
    reg {
        name="Buffer2WriteData32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteData32_Set @ 0x10c0;
    reg {
        name="Buffer2XorWrite32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2XorWrite32_Set @ 0x10c4;
    reg {
        name="Buffer3Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Control_Set @ 0x10cc;
    reg {
        name="Buffer3Address_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Address_Set @ 0x10d0;
    reg {
        name="Buffer3WriteOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteOffset_Set @ 0x10d4;
    reg {
        name="Buffer3ReadOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadOffset_Set @ 0x10d8;
    reg {
        name="Buffer3WriteStart_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteStart_Set @ 0x10dc;
    reg {
        name="Buffer3ReadData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadData_Set @ 0x10e0;
    reg {
        name="Buffer3WriteData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteData_Set @ 0x10e4;
    reg {
        name="Buffer3XorWrite_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3XorWrite_Set @ 0x10e8;
    reg {
        name="Buffer3Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Status_Set @ 0x10ec;
    reg {
        name="Buffer3ThresholdControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ThresholdControl_Set @ 0x10f0;
    reg {
        name="Buffer3Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Command_Set @ 0x10f4;
    reg {
        name="Buffer3FifoAsync_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3FifoAsync_Set @ 0x10f8;
    reg {
        name="Buffer3ReadData32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadData32_Set @ 0x10fc;
    reg {
        name="Buffer3WriteData32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteData32_Set @ 0x1100;
    reg {
        name="Buffer3XorWrite32_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3XorWrite32_Set @ 0x1104;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x1114;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x1118;
    reg {
        name="SequencerInterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Set @ 0x111c;
    reg {
        name="SequencerInterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Set @ 0x1120;
    reg {
        name="AhbConfiguration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbConfiguration_Set @ 0x1124;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Enable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Clr @ 0x2004;
    reg {
        name="LowPowerMode_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPowerMode_Clr @ 0x2008;
    reg {
        name="Buffer0Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Control_Clr @ 0x200c;
    reg {
        name="Buffer0Address_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Address_Clr @ 0x2010;
    reg {
        name="Buffer0WriteOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteOffset_Clr @ 0x2014;
    reg {
        name="Buffer0ReadOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadOffset_Clr @ 0x2018;
    reg {
        name="Buffer0WriteStart_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteStart_Clr @ 0x201c;
    reg {
        name="Buffer0ReadData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadData_Clr @ 0x2020;
    reg {
        name="Buffer0WriteData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteData_Clr @ 0x2024;
    reg {
        name="Buffer0XorWrite_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0XorWrite_Clr @ 0x2028;
    reg {
        name="Buffer0Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Status_Clr @ 0x202c;
    reg {
        name="Buffer0ThresholdControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ThresholdControl_Clr @ 0x2030;
    reg {
        name="Buffer0Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Command_Clr @ 0x2034;
    reg {
        name="Buffer0FifoAsync_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0FifoAsync_Clr @ 0x2038;
    reg {
        name="Buffer0ReadData32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadData32_Clr @ 0x203c;
    reg {
        name="Buffer0WriteData32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteData32_Clr @ 0x2040;
    reg {
        name="Buffer0XorWrite32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0XorWrite32_Clr @ 0x2044;
    reg {
        name="Buffer1Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Control_Clr @ 0x204c;
    reg {
        name="Buffer1Address_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Address_Clr @ 0x2050;
    reg {
        name="Buffer1WriteOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteOffset_Clr @ 0x2054;
    reg {
        name="Buffer1ReadOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadOffset_Clr @ 0x2058;
    reg {
        name="Buffer1WriteStart_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteStart_Clr @ 0x205c;
    reg {
        name="Buffer1ReadData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadData_Clr @ 0x2060;
    reg {
        name="Buffer1WriteData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteData_Clr @ 0x2064;
    reg {
        name="Buffer1XorWrite_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1XorWrite_Clr @ 0x2068;
    reg {
        name="Buffer1Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Status_Clr @ 0x206c;
    reg {
        name="Buffer1ThresholdControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ThresholdControl_Clr @ 0x2070;
    reg {
        name="Buffer1Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Command_Clr @ 0x2074;
    reg {
        name="Buffer1FifoAsync_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1FifoAsync_Clr @ 0x2078;
    reg {
        name="Buffer1ReadData32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadData32_Clr @ 0x207c;
    reg {
        name="Buffer1WriteData32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteData32_Clr @ 0x2080;
    reg {
        name="Buffer1XorWrite32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1XorWrite32_Clr @ 0x2084;
    reg {
        name="Buffer2Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Control_Clr @ 0x208c;
    reg {
        name="Buffer2Address_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Address_Clr @ 0x2090;
    reg {
        name="Buffer2WriteOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteOffset_Clr @ 0x2094;
    reg {
        name="Buffer2ReadOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadOffset_Clr @ 0x2098;
    reg {
        name="Buffer2WriteStart_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteStart_Clr @ 0x209c;
    reg {
        name="Buffer2ReadData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadData_Clr @ 0x20a0;
    reg {
        name="Buffer2WriteData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteData_Clr @ 0x20a4;
    reg {
        name="Buffer2XorWrite_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2XorWrite_Clr @ 0x20a8;
    reg {
        name="Buffer2Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Status_Clr @ 0x20ac;
    reg {
        name="Buffer2ThresholdControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ThresholdControl_Clr @ 0x20b0;
    reg {
        name="Buffer2Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Command_Clr @ 0x20b4;
    reg {
        name="Buffer2FifoAsync_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2FifoAsync_Clr @ 0x20b8;
    reg {
        name="Buffer2ReadData32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadData32_Clr @ 0x20bc;
    reg {
        name="Buffer2WriteData32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteData32_Clr @ 0x20c0;
    reg {
        name="Buffer2XorWrite32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2XorWrite32_Clr @ 0x20c4;
    reg {
        name="Buffer3Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Control_Clr @ 0x20cc;
    reg {
        name="Buffer3Address_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Address_Clr @ 0x20d0;
    reg {
        name="Buffer3WriteOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteOffset_Clr @ 0x20d4;
    reg {
        name="Buffer3ReadOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadOffset_Clr @ 0x20d8;
    reg {
        name="Buffer3WriteStart_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteStart_Clr @ 0x20dc;
    reg {
        name="Buffer3ReadData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadData_Clr @ 0x20e0;
    reg {
        name="Buffer3WriteData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteData_Clr @ 0x20e4;
    reg {
        name="Buffer3XorWrite_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3XorWrite_Clr @ 0x20e8;
    reg {
        name="Buffer3Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Status_Clr @ 0x20ec;
    reg {
        name="Buffer3ThresholdControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ThresholdControl_Clr @ 0x20f0;
    reg {
        name="Buffer3Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Command_Clr @ 0x20f4;
    reg {
        name="Buffer3FifoAsync_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3FifoAsync_Clr @ 0x20f8;
    reg {
        name="Buffer3ReadData32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadData32_Clr @ 0x20fc;
    reg {
        name="Buffer3WriteData32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteData32_Clr @ 0x2100;
    reg {
        name="Buffer3XorWrite32_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3XorWrite32_Clr @ 0x2104;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x2114;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x2118;
    reg {
        name="SequencerInterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Clr @ 0x211c;
    reg {
        name="SequencerInterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Clr @ 0x2120;
    reg {
        name="AhbConfiguration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbConfiguration_Clr @ 0x2124;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Enable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Tgl @ 0x3004;
    reg {
        name="LowPowerMode_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPowerMode_Tgl @ 0x3008;
    reg {
        name="Buffer0Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Control_Tgl @ 0x300c;
    reg {
        name="Buffer0Address_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Address_Tgl @ 0x3010;
    reg {
        name="Buffer0WriteOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteOffset_Tgl @ 0x3014;
    reg {
        name="Buffer0ReadOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadOffset_Tgl @ 0x3018;
    reg {
        name="Buffer0WriteStart_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteStart_Tgl @ 0x301c;
    reg {
        name="Buffer0ReadData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadData_Tgl @ 0x3020;
    reg {
        name="Buffer0WriteData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteData_Tgl @ 0x3024;
    reg {
        name="Buffer0XorWrite_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0XorWrite_Tgl @ 0x3028;
    reg {
        name="Buffer0Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Status_Tgl @ 0x302c;
    reg {
        name="Buffer0ThresholdControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ThresholdControl_Tgl @ 0x3030;
    reg {
        name="Buffer0Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0Command_Tgl @ 0x3034;
    reg {
        name="Buffer0FifoAsync_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0FifoAsync_Tgl @ 0x3038;
    reg {
        name="Buffer0ReadData32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0ReadData32_Tgl @ 0x303c;
    reg {
        name="Buffer0WriteData32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0WriteData32_Tgl @ 0x3040;
    reg {
        name="Buffer0XorWrite32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer0XorWrite32_Tgl @ 0x3044;
    reg {
        name="Buffer1Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Control_Tgl @ 0x304c;
    reg {
        name="Buffer1Address_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Address_Tgl @ 0x3050;
    reg {
        name="Buffer1WriteOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteOffset_Tgl @ 0x3054;
    reg {
        name="Buffer1ReadOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadOffset_Tgl @ 0x3058;
    reg {
        name="Buffer1WriteStart_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteStart_Tgl @ 0x305c;
    reg {
        name="Buffer1ReadData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadData_Tgl @ 0x3060;
    reg {
        name="Buffer1WriteData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteData_Tgl @ 0x3064;
    reg {
        name="Buffer1XorWrite_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1XorWrite_Tgl @ 0x3068;
    reg {
        name="Buffer1Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Status_Tgl @ 0x306c;
    reg {
        name="Buffer1ThresholdControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ThresholdControl_Tgl @ 0x3070;
    reg {
        name="Buffer1Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1Command_Tgl @ 0x3074;
    reg {
        name="Buffer1FifoAsync_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1FifoAsync_Tgl @ 0x3078;
    reg {
        name="Buffer1ReadData32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1ReadData32_Tgl @ 0x307c;
    reg {
        name="Buffer1WriteData32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1WriteData32_Tgl @ 0x3080;
    reg {
        name="Buffer1XorWrite32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer1XorWrite32_Tgl @ 0x3084;
    reg {
        name="Buffer2Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Control_Tgl @ 0x308c;
    reg {
        name="Buffer2Address_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Address_Tgl @ 0x3090;
    reg {
        name="Buffer2WriteOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteOffset_Tgl @ 0x3094;
    reg {
        name="Buffer2ReadOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadOffset_Tgl @ 0x3098;
    reg {
        name="Buffer2WriteStart_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteStart_Tgl @ 0x309c;
    reg {
        name="Buffer2ReadData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadData_Tgl @ 0x30a0;
    reg {
        name="Buffer2WriteData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteData_Tgl @ 0x30a4;
    reg {
        name="Buffer2XorWrite_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2XorWrite_Tgl @ 0x30a8;
    reg {
        name="Buffer2Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Status_Tgl @ 0x30ac;
    reg {
        name="Buffer2ThresholdControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ThresholdControl_Tgl @ 0x30b0;
    reg {
        name="Buffer2Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2Command_Tgl @ 0x30b4;
    reg {
        name="Buffer2FifoAsync_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2FifoAsync_Tgl @ 0x30b8;
    reg {
        name="Buffer2ReadData32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2ReadData32_Tgl @ 0x30bc;
    reg {
        name="Buffer2WriteData32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2WriteData32_Tgl @ 0x30c0;
    reg {
        name="Buffer2XorWrite32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer2XorWrite32_Tgl @ 0x30c4;
    reg {
        name="Buffer3Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Control_Tgl @ 0x30cc;
    reg {
        name="Buffer3Address_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Address_Tgl @ 0x30d0;
    reg {
        name="Buffer3WriteOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteOffset_Tgl @ 0x30d4;
    reg {
        name="Buffer3ReadOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadOffset_Tgl @ 0x30d8;
    reg {
        name="Buffer3WriteStart_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteStart_Tgl @ 0x30dc;
    reg {
        name="Buffer3ReadData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadData_Tgl @ 0x30e0;
    reg {
        name="Buffer3WriteData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteData_Tgl @ 0x30e4;
    reg {
        name="Buffer3XorWrite_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3XorWrite_Tgl @ 0x30e8;
    reg {
        name="Buffer3Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Status_Tgl @ 0x30ec;
    reg {
        name="Buffer3ThresholdControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ThresholdControl_Tgl @ 0x30f0;
    reg {
        name="Buffer3Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3Command_Tgl @ 0x30f4;
    reg {
        name="Buffer3FifoAsync_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3FifoAsync_Tgl @ 0x30f8;
    reg {
        name="Buffer3ReadData32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3ReadData32_Tgl @ 0x30fc;
    reg {
        name="Buffer3WriteData32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3WriteData32_Tgl @ 0x3100;
    reg {
        name="Buffer3XorWrite32_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Buffer3XorWrite32_Tgl @ 0x3104;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x3114;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x3118;
    reg {
        name="SequencerInterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Tgl @ 0x311c;
    reg {
        name="SequencerInterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Tgl @ 0x3120;
    reg {
        name="AhbConfiguration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbConfiguration_Tgl @ 0x3124;
} BufferControllerRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion @ 0x0;
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x4;
    reg {
        name="InterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXFRAMESENTIF[0:0];
            field {
                sw = rw;
            } TXSYNCSENTIF[1:1];
            field {
                sw = rw;
            } TXPRESENTIF[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
                reset=1'b1;
            } TXRAMPDONEIF[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LDTNOARRIF[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHDSADETIF[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHYUNCODEDETIF[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHYCODEDETIF[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMDETIF[8:8];
            field {
                sw = rw;
            } RXPREDETIF[9:9];
            field {
                sw = rw;
            } RXFRAMEDET0IF[10:10];
            field {
                sw = rw;
            } RXFRAMEDET1IF[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMLOSTIF[12:12];
            field {
                sw = rw;
            } RXPRELOSTIF[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXFRAMEDETOFIF[14:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMNFIF[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCTIMOUTIF[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ETSIF[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFGANTPATTRDIF[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRESTARTRSSIMAPREIF[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRESTARTRSSIMASYNCIF[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQDETIF[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQNOTDETIF[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ANTDIVRDYIF[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SOFTRESETDONEIF[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQPRENOTDETIF[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQFRAMENOTDETIF[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQAFCOUTOFBANDIF[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIDETIF[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIRESETIF[29:29];
    } InterruptFlags @ 0x8;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXFRAMESENTIEN[0:0];
            field {
                sw = rw;
            } TXSYNCSENTIEN[1:1];
            field {
                sw = rw;
            } TXPRESENTIEN[2:2];
            field {
                sw = rw;
            } TXRAMPDONEIEN[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LDTNOARRIEN[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHDSADETIEN[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHYUNCODEDETIEN[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHYCODEDETIEN[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMDETIEN[8:8];
            field {
                sw = rw;
            } RXPREDETIEN[9:9];
            field {
                sw = rw;
            } RXFRAMEDET0IEN[10:10];
            field {
                sw = rw;
            } RXFRAMEDET1IEN[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMLOSTIEN[12:12];
            field {
                sw = rw;
            } RXPRELOSTIEN[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXFRAMEDETOFIEN[14:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMNFIEN[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCTIMOUTIEN[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ETSIEN[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFGANTPATTRDIEN[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRESTARTRSSIMAPREIEN[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRESTARTRSSIMASYNCIEN[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQDETIEN[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQNOTDETIEN[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ANTDIVRDYIEN[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SOFTRESETDONEIEN[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQPRENOTDETIEN[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQFRAMENOTDETIEN[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQAFCOUTOFBANDIEN[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIDETIEN[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIRESETIEN[29:29];
    } InterruptEnable @ 0xc;
    reg {
        name="SequencerInterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXFRAMESENTSEQIF[0:0];
            field {
                sw = rw;
            } TXSYNCSENTSEQIF[1:1];
            field {
                sw = rw;
            } TXPRESENTSEQIF[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
                reset=1'b1;
            } TXRAMPDONESEQIF[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LDTNOARRSEQIF[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHDSADETSEQIF[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHYUNCODEDETSEQIF[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHYCODEDETSEQIF[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMDETSEQIF[8:8];
            field {
                sw = rw;
            } RXPREDETSEQIF[9:9];
            field {
                sw = rw;
            } RXFRAMEDET0SEQIF[10:10];
            field {
                sw = rw;
            } RXFRAMEDET1SEQIF[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMLOSTSEQIF[12:12];
            field {
                sw = rw;
            } RXPRELOSTSEQIF[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXFRAMEDETOFSEQIF[14:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMNFSEQIF[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCTIMOUTSEQIF[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ETSSEQIF[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFGANTPATTRDSEQIF[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRESTARTRSSIMAPRESEQIF[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRESTARTRSSIMASYNCSEQIF[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQDETSEQIF[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQNOTDETSEQIF[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ANTDIVRDYSEQIF[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SOFTRESETDONESEQIF[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQPRENOTDETSEQIF[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQFRAMENOTDETSEQIF[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQAFCOUTOFBANDSEQIF[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIDETSEQIF[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIRESETSEQIF[29:29];
    } SequencerInterruptFlags @ 0x10;
    reg {
        name="SequencerInterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXFRAMESENTSEQIEN[0:0];
            field {
                sw = rw;
            } TXSYNCSENTSEQIEN[1:1];
            field {
                sw = rw;
            } TXPRESENTSEQIEN[2:2];
            field {
                sw = rw;
            } TXRAMPDONESEQIEN[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LDTNOARRSEQIEN[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHDSADETSEQIEN[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHYUNCODEDETSEQIEN[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHYCODEDETSEQIEN[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMDETSEQIEN[8:8];
            field {
                sw = rw;
            } RXPREDETSEQIEN[9:9];
            field {
                sw = rw;
            } RXFRAMEDET0SEQIEN[10:10];
            field {
                sw = rw;
            } RXFRAMEDET1SEQIEN[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMLOSTSEQIEN[12:12];
            field {
                sw = rw;
            } RXPRELOSTSEQIEN[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXFRAMEDETOFSEQIEN[14:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXTIMNFSEQIEN[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCTIMOUTSEQIEN[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ETSSEQIEN[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFGANTPATTRDSEQIEN[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRESTARTRSSIMAPRESEQIEN[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXRESTARTRSSIMASYNCSEQIEN[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQDETSEQIEN[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQNOTDETSEQIEN[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ANTDIVRDYSEQIEN[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SOFTRESETDONESEQIEN[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQPRENOTDETSEQIEN[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQFRAMENOTDETSEQIEN[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SQAFCOUTOFBANDSEQIEN[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIDETSEQIEN[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIRESETSEQIEN[29:29];
    } SequencerInterruptEnable @ 0x14;
    reg {
        name="Status";
        regwidth=0x20;
            field {
                sw = r;
            } DEMODSTATE[2:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BCRCFEDSADET[3:3];
            field {
                sw = r;
            } FRAMEDETID[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ANTSEL[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TIMSEQINV[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TIMLOSTCAUSE[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DSADETECTED[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DSAFREQESTDONE[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } VITERBIDEMODTIMDET[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } VITERBIDEMODFRAMEDET[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } STAMPSTATE[14:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TRECSDSAADET[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CORR[23:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WEAKSYMBOLS[31:24];
    } Status @ 0x18;
    reg {
        name="Status2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2 @ 0x1c;
    reg {
        name="Status3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status3 @ 0x20;
    reg {
        name="Status4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status4 @ 0x24;
    reg {
        name="Status5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status5 @ 0x28;
    reg {
        name="Status6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status6 @ 0x2c;
    reg {
        name="Status7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status7 @ 0x30;
    reg {
        name="TimingDetectionStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimingDetectionStatus @ 0x34;
    reg {
        name="DemodulatorFSMStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DemodulatorFSMStatus @ 0x38;
    reg {
        name="FrequencyOffsetEstimate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetEstimate @ 0x3c;
    reg {
        name="AutomaticFrequencyControlAdjustmentRx";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControlAdjustmentRx @ 0x40;
    reg {
        name="AutomaticFrequencyControldAjustmentTx";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControldAjustmentTx @ 0x44;
    reg {
        name="AnalogMixerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogMixerControl @ 0x48;
    reg {
        name="Control0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control0 @ 0x4c;
    reg {
        name="Control1";
        regwidth=0x20;
            field {
                sw = rw;
            } SYNCBITS[4:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SYNCERRORS[8:5];
            field {
                sw = rw;
            } DUALSYNC[9:9];
            field {
                sw = rw;
            } TXSYNC[10:10];
            field {
                sw = rw;
            } SYNCDATA[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SYNC1INV[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } COMPMODE[15:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RESYNCPER[19:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PHASEDEMOD[21:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FREQOFFESTPER[24:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FREQOFFESTLIM[31:25];
    } Control1 @ 0x50;
    reg {
        name="Control2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control2 @ 0x54;
    reg {
        name="Control3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control3 @ 0x58;
    reg {
        name="Control4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control4 @ 0x5c;
    reg {
        name="Control5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control5 @ 0x60;
    reg {
        name="Control6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control6 @ 0x64;
    reg {
        name="TxBaudrate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxBaudrate @ 0x68;
    reg {
        name="RxBaudrate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxBaudrate @ 0x6c;
    reg {
        name="ChannelFilter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilter @ 0x70;
    reg {
        name="Preamble";
        regwidth=0x20;
            field {
                sw = rw;
            } TXBASES[31:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PREWNDERRORS[15:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PREAMBDETEN[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SYNCSYMB4FSK[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DSSSPRE[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PREERRORS[10:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRESYMB4FSK[6:6];
            field {
                sw = rw;
            } BASEBITS[5:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BASE[3:0];
    } Preamble @ 0x74;
    reg {
        name="SyncWord0";
        regwidth=0x20;
            field {
                sw = rw;
            } SYNC0[31:0];
    } SyncWord0 @ 0x78;
    reg {
        name="SyncWord1";
        regwidth=0x20;
            field {
                sw = rw;
            } SYNC1[31:0];
    } SyncWord1 @ 0x7c;
    reg {
        name="Timing";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timing @ 0x80;
    reg {
        name="DirectSequenceSpreadSpectrumSymbol0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectSequenceSpreadSpectrumSymbol0 @ 0x84;
    reg {
        name="ModulationIndex";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModulationIndex @ 0x88;
    reg {
        name="AutomaticFrequencyControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControl @ 0x8c;
    reg {
        name="AutomaticFrequencyControlAdjustmentLimit";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControlAdjustmentLimit @ 0x90;
    reg {
        name="ShapingCoefficients0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients0 @ 0x94;
    reg {
        name="ShapingCoefficients1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients1 @ 0x98;
    reg {
        name="ShapingCoefficients2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients2 @ 0x9c;
    reg {
        name="ShapingCoefficients3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients3 @ 0xa0;
    reg {
        name="ShapingCoefficients4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients4 @ 0xa4;
    reg {
        name="ShapingCoefficients5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients5 @ 0xa8;
    reg {
        name="ShapingCoefficients6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients6 @ 0xac;
    reg {
        name="ShapingCoefficients7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients7 @ 0xb0;
    reg {
        name="ShapingCoefficients8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients8 @ 0xb4;
    reg {
        name="ShapingCoefficients9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients9 @ 0xb8;
    reg {
        name="ShapingCoefficients10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients10 @ 0xbc;
    reg {
        name="ShapingCoefficients11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients11 @ 0xc0;
    reg {
        name="ShapingCoefficients12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients12 @ 0xc4;
    reg {
        name="ShapingCoefficients13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients13 @ 0xc8;
    reg {
        name="ShapingCoefficients14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients14 @ 0xcc;
    reg {
        name="ShapingCoefficients15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients15 @ 0xd0;
    reg {
        name="RampingControl";
        regwidth=0x20;
            field {
                sw = rw;
            } RAMPRATE0[3:0];
            field {
                sw = rw;
            } RAMPRATE1[7:4];
            field {
                sw = rw;
            } RAMPRATE2[11:8];
            field {
                sw = rw;
            } RAMPDIS[12:12];
            field {
                sw = rw;
            } RAMPVAL[23:16];
    } RampingControl @ 0xd8;
    reg {
        name="RampingLevels";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RampingLevels @ 0xdc;
    reg {
        name="AnalogRampingControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogRampingControl @ 0xe0;
    reg {
        name="DirectCurrentOffsetCompensationFilterSettings";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetCompensationFilterSettings @ 0x110;
    reg {
        name="DirectCurrentOffsetCompensationFilterInitialization";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetCompensationFilterInitialization @ 0x114;
    reg {
        name="DirectCurrentOffsetEstimatedValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetEstimatedValue @ 0x118;
    reg {
        name="SampleRateConverterRatioValuesAndChannelFilter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SampleRateConverterRatioValuesAndChannelFilter @ 0x11c;
    reg {
        name="InternalAutomaticFrequencyControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalAutomaticFrequencyControl @ 0x120;
    reg {
        name="DetectionOfSignalArrivalThreshold0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold0 @ 0x124;
    reg {
        name="DetectionOfSignalArrivalThreshold1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold1 @ 0x128;
    reg {
        name="DetectionOfSignalArrivalThreshold2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold2 @ 0x12c;
    reg {
        name="DetectionOfSignalArrivalThreshold3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold3 @ 0x130;
    reg {
        name="DetectionOfSignalArrivalThreshold4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold4 @ 0x134;
    reg {
        name="DetectionOfSignalArrivalMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalMode @ 0x138;
    reg {
        name="DigitalMixerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalMixerControl @ 0x13c;
    reg {
        name="ViterbiDemodulator";
        regwidth=0x20;
            field {
                sw = rw;
            } VTDEMODEN[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HARDDECISION[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } VITERBIKSI1[8:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } VITERBIKSI2[15:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } VITERBIKSI3[22:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SYNTHAFC[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CORRCYCLE[27:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CORRSTPSIZE[31:28];
    } ViterbiDemodulator @ 0x140;
    reg {
        name="ViterbiDemodulatorCorrelationConfiguration0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorCorrelationConfiguration0 @ 0x144;
    reg {
        name="ViterbiDemodulatorCorrelationConfiguration1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorCorrelationConfiguration1 @ 0x148;
    reg {
        name="ViterbiDemodulatorTrackingLoop";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorTrackingLoop @ 0x14c;
    reg {
        name="ViterbiBleTimingStampControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiBleTimingStampControl @ 0x150;
    reg {
        name="BaudrateEstimate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaudrateEstimate @ 0x154;
    reg {
        name="AutomaticClockGating";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGating @ 0x158;
    reg {
        name="AutomaticClockGatingClockStop";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGatingClockStop @ 0x15c;
    reg {
        name="PhaseOffsetEstimate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseOffsetEstimate @ 0x160;
    reg {
        name="DirectModeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectModeControl @ 0x164;
    reg {
        name="BleLongRange";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRange @ 0x168;
    reg {
        name="BleLongRangeSet1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet1 @ 0x16c;
    reg {
        name="BleLongRangeSet2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet2 @ 0x170;
    reg {
        name="BleLongRangeSet3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet3 @ 0x174;
    reg {
        name="BleLongRangeSet4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet4 @ 0x178;
    reg {
        name="BleLongRangeSet5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet5 @ 0x17c;
    reg {
        name="BleLongRangeSet6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet6 @ 0x180;
    reg {
        name="BleLongRangeFrameControllerInterface";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeFrameControllerInterface @ 0x184;
    reg {
        name="CoherentDemodulatorSignals0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals0 @ 0x188;
    reg {
        name="CoherentDemodulatorSignals1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals1 @ 0x18c;
    reg {
        name="CoherentDemodulatorSignals2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals2 @ 0x190;
    reg {
        name="CoherentDemodulatorSignals3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals3 @ 0x194;
    reg {
        name="Command";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRESTOP[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CHPWRACCUCLR[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } AFCTXLOCK[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } AFCTXCLEAR[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } AFCRXCLEAR[5:5];
    } Command @ 0x198;
    reg {
        name="SyncWordProperties";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWordProperties @ 0x1a4;
    reg {
        name="DigitalGainControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalGainControl @ 0x1a8;
    reg {
        name="PeripheralReflexSystemControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PeripheralReflexSystemControl @ 0x1ac;
    reg {
        name="PowerAmplifierDebug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierDebug @ 0x1b0;
    reg {
        name="RealTimeCostFunctionEngineControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RealTimeCostFunctionEngineControl @ 0x1b4;
    reg {
        name="EarlyTimeStampControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EarlyTimeStampControl @ 0x1b8;
    reg {
        name="EarlyTimeStampTiming";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EarlyTimeStampTiming @ 0x1bc;
    reg {
        name="AntennaSwitchControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchControl @ 0x1c0;
    reg {
        name="AntennaSwitchControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchControl1 @ 0x1c4;
    reg {
        name="AntennaSwitchStart";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchStart @ 0x1c8;
    reg {
        name="AntennaSwitchEnd";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchEnd @ 0x1cc;
    reg {
        name="TrecsPreamblePattern";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsPreamblePattern @ 0x1d0;
    reg {
        name="TrecsPreambleDetectionControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsPreambleDetectionControl @ 0x1d4;
    reg {
        name="TrecsConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsConfiguration @ 0x1d8;
    reg {
        name="ConfigureAntennaPattern";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigureAntennaPattern @ 0x1dc;
    reg {
        name="ConcurrentMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConcurrentMode @ 0x1e0;
    reg {
        name="ChannelFilterCoeSet0Group0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group0 @ 0x1e4;
    reg {
        name="ChannelFilterCoeSet0Group1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group1 @ 0x1e8;
    reg {
        name="ChannelFilterCoeSet0Group2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group2 @ 0x1ec;
    reg {
        name="ChannelFilterCoeSet0Group3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group3 @ 0x1f0;
    reg {
        name="ChannelFilterCoeSet0Group4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group4 @ 0x1f4;
    reg {
        name="ChannelFilterCoeSet0Group5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group5 @ 0x1f8;
    reg {
        name="ChannelFilterCoeSet0Group6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group6 @ 0x1fc;
    reg {
        name="ChannelFilterCoeSet1Group0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group0 @ 0x200;
    reg {
        name="ChannelFilterCoeSet1Group1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group1 @ 0x204;
    reg {
        name="ChannelFilterCoeSet1Group2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group2 @ 0x208;
    reg {
        name="ChannelFilterCoeSet1Group3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group3 @ 0x20c;
    reg {
        name="ChannelFilterCoeSet1Group4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group4 @ 0x210;
    reg {
        name="ChannelFilterCoeSet1Group5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group5 @ 0x214;
    reg {
        name="ChannelFilterCoeSet1Group6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group6 @ 0x218;
    reg {
        name="ChannelFilterControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterControl @ 0x21c;
    reg {
        name="ChannelFilterLatencyControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterLatencyControl @ 0x220;
    reg {
        name="FrameSchTimeoutLength";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameSchTimeoutLength @ 0x224;
    reg {
        name="PreambleFilterCoefficients";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleFilterCoefficients @ 0x228;
    reg {
        name="CollisionRestartControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CollisionRestartControl @ 0x22c;
    reg {
        name="PreambleSenseMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleSenseMode @ 0x230;
    reg {
        name="PreambleSenseModeExtended";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleSenseModeExtended @ 0x234;
    reg {
        name="SignalQualityIndicator";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalQualityIndicator @ 0x238;
    reg {
        name="AntennaDiversityModeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversityModeControl @ 0x23c;
    reg {
        name="PhaseDemodulatorFwMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorFwMode @ 0x240;
    reg {
        name="PhaseDemodulatorAntennaDiversity";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorAntennaDiversity @ 0x244;
    reg {
        name="PhaseDemodulatorAntennaDiversityDecision";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorAntennaDiversityDecision @ 0x248;
    reg {
        name="PhaseDemodulatorControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorControl @ 0x24c;
    reg {
        name="SignalIdentifierControl0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl0 @ 0x250;
    reg {
        name="SignalIdentifierControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl1 @ 0x254;
    reg {
        name="SignalIdentifierStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierStatus @ 0x258;
    reg {
        name="ConfigureAntennaPatternExtended";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigureAntennaPatternExtended @ 0x25c;
    reg {
        name="SignalIdentifierControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl2 @ 0x264;
    reg {
        name="ChannelFilterSwitchTime";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterSwitchTime @ 0x268;
    reg {
        name="IrCalibrationControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalibrationControl @ 0x270;
    reg {
        name="IrCalCoefficientValues";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientValues @ 0x274;
    reg {
        name="IrCalCoefficientWrPerAntenna0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientWrPerAntenna0 @ 0x278;
    reg {
        name="IrCalCoefficientWrPerAntenna1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientWrPerAntenna1 @ 0x27c;
    reg {
        name="AdControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdControl1 @ 0x280;
    reg {
        name="AdControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdControl2 @ 0x284;
    reg {
        name="AdQual0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual0 @ 0x288;
    reg {
        name="AdQual1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual1 @ 0x28c;
    reg {
        name="AdQual2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual2 @ 0x290;
    reg {
        name="AdQual3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual3 @ 0x294;
    reg {
        name="AdQual4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual4 @ 0x298;
    reg {
        name="AdQual5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual5 @ 0x29c;
    reg {
        name="AdQual6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual6 @ 0x2a0;
    reg {
        name="AdQual7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual7 @ 0x2a4;
    reg {
        name="AdQual8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual8 @ 0x2a8;
    reg {
        name="AdQual9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual9 @ 0x2ac;
    reg {
        name="AdQual10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual10 @ 0x2b0;
    reg {
        name="AdFsm0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm0 @ 0x2b4;
    reg {
        name="AdFsm1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm1 @ 0x2b8;
    reg {
        name="AdFsm2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm2 @ 0x2bc;
    reg {
        name="AdFsm3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm3 @ 0x2c0;
    reg {
        name="AdFsm4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm4 @ 0x2c4;
    reg {
        name="AdFsm5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm5 @ 0x2c8;
    reg {
        name="AdFsm6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm6 @ 0x2cc;
    reg {
        name="AdFsm7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm7 @ 0x2d0;
    reg {
        name="AdFsm8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm8 @ 0x2d4;
    reg {
        name="AdFsm9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm9 @ 0x2d8;
    reg {
        name="AdFsm10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm10 @ 0x2dc;
    reg {
        name="AdFsm11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm11 @ 0x2e0;
    reg {
        name="AdFsm12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm12 @ 0x2e4;
    reg {
        name="AdFsm13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm13 @ 0x2e8;
    reg {
        name="AdFsm14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm14 @ 0x2ec;
    reg {
        name="AdFsm15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm15 @ 0x2f0;
    reg {
        name="AdFsm16";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm16 @ 0x2f4;
    reg {
        name="AdFsm17";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm17 @ 0x2f8;
    reg {
        name="AdFsm18";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm18 @ 0x2fc;
    reg {
        name="AdFsm19";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm19 @ 0x300;
    reg {
        name="AdFsm20";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm20 @ 0x304;
    reg {
        name="AdFsm21";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm21 @ 0x308;
    reg {
        name="AdFsm22";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm22 @ 0x30c;
    reg {
        name="AdFsm23";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm23 @ 0x310;
    reg {
        name="AdFsm24";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm24 @ 0x314;
    reg {
        name="AdFsm25";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm25 @ 0x318;
    reg {
        name="AdFsm26";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm26 @ 0x31c;
    reg {
        name="AdFsm27";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm27 @ 0x320;
    reg {
        name="AdFsm28";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm28 @ 0x324;
    reg {
        name="AdFsm29";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm29 @ 0x328;
    reg {
        name="AdFsm30";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm30 @ 0x32c;
    reg {
        name="AdPc1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc1 @ 0x330;
    reg {
        name="AdPc2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc2 @ 0x334;
    reg {
        name="AdPc3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc3 @ 0x338;
    reg {
        name="AdPc4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc4 @ 0x33c;
    reg {
        name="AdPc5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc5 @ 0x340;
    reg {
        name="AdPc6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc6 @ 0x344;
    reg {
        name="AdPc7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc7 @ 0x348;
    reg {
        name="AdPc8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc8 @ 0x34c;
    reg {
        name="AdPc9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc9 @ 0x350;
    reg {
        name="AdPc10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc10 @ 0x354;
    reg {
        name="HadmControl0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmControl0 @ 0x3b0;
    reg {
        name="HadmControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmControl1 @ 0x3b4;
    reg {
        name="HadmStatus0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus0 @ 0x3b8;
    reg {
        name="HadmStatus1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus1 @ 0x3bc;
    reg {
        name="HadmStatus2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus2 @ 0x3c0;
    reg {
        name="HadmStatus3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus3 @ 0x3c4;
    reg {
        name="HadmStatus4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus4 @ 0x3c8;
    reg {
        name="HadmStatus5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus5 @ 0x3cc;
    reg {
        name="HadmStatus6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus6 @ 0x3d0;
    reg {
        name="Src2NcoControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Src2NcoControl @ 0x3e0;
    reg {
        name="Spare";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare @ 0x400;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Enable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Set @ 0x1004;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x1008;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x100c;
    reg {
        name="SequencerInterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Set @ 0x1010;
    reg {
        name="SequencerInterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Set @ 0x1014;
    reg {
        name="Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Set @ 0x1018;
    reg {
        name="Status2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Set @ 0x101c;
    reg {
        name="Status3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status3_Set @ 0x1020;
    reg {
        name="Status4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status4_Set @ 0x1024;
    reg {
        name="Status5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status5_Set @ 0x1028;
    reg {
        name="Status6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status6_Set @ 0x102c;
    reg {
        name="Status7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status7_Set @ 0x1030;
    reg {
        name="TimingDetectionStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimingDetectionStatus_Set @ 0x1034;
    reg {
        name="DemodulatorFSMStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DemodulatorFSMStatus_Set @ 0x1038;
    reg {
        name="FrequencyOffsetEstimate_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetEstimate_Set @ 0x103c;
    reg {
        name="AutomaticFrequencyControlAdjustmentRx_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControlAdjustmentRx_Set @ 0x1040;
    reg {
        name="AutomaticFrequencyControldAjustmentTx_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControldAjustmentTx_Set @ 0x1044;
    reg {
        name="AnalogMixerControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogMixerControl_Set @ 0x1048;
    reg {
        name="Control0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control0_Set @ 0x104c;
    reg {
        name="Control1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control1_Set @ 0x1050;
    reg {
        name="Control2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control2_Set @ 0x1054;
    reg {
        name="Control3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control3_Set @ 0x1058;
    reg {
        name="Control4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control4_Set @ 0x105c;
    reg {
        name="Control5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control5_Set @ 0x1060;
    reg {
        name="Control6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control6_Set @ 0x1064;
    reg {
        name="TxBaudrate_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxBaudrate_Set @ 0x1068;
    reg {
        name="RxBaudrate_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxBaudrate_Set @ 0x106c;
    reg {
        name="ChannelFilter_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilter_Set @ 0x1070;
    reg {
        name="Preamble_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Preamble_Set @ 0x1074;
    reg {
        name="SyncWord0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWord0_Set @ 0x1078;
    reg {
        name="SyncWord1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWord1_Set @ 0x107c;
    reg {
        name="Timing_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timing_Set @ 0x1080;
    reg {
        name="DirectSequenceSpreadSpectrumSymbol0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectSequenceSpreadSpectrumSymbol0_Set @ 0x1084;
    reg {
        name="ModulationIndex_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModulationIndex_Set @ 0x1088;
    reg {
        name="AutomaticFrequencyControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControl_Set @ 0x108c;
    reg {
        name="AutomaticFrequencyControlAdjustmentLimit_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControlAdjustmentLimit_Set @ 0x1090;
    reg {
        name="ShapingCoefficients0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients0_Set @ 0x1094;
    reg {
        name="ShapingCoefficients1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients1_Set @ 0x1098;
    reg {
        name="ShapingCoefficients2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients2_Set @ 0x109c;
    reg {
        name="ShapingCoefficients3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients3_Set @ 0x10a0;
    reg {
        name="ShapingCoefficients4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients4_Set @ 0x10a4;
    reg {
        name="ShapingCoefficients5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients5_Set @ 0x10a8;
    reg {
        name="ShapingCoefficients6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients6_Set @ 0x10ac;
    reg {
        name="ShapingCoefficients7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients7_Set @ 0x10b0;
    reg {
        name="ShapingCoefficients8_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients8_Set @ 0x10b4;
    reg {
        name="ShapingCoefficients9_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients9_Set @ 0x10b8;
    reg {
        name="ShapingCoefficients10_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients10_Set @ 0x10bc;
    reg {
        name="ShapingCoefficients11_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients11_Set @ 0x10c0;
    reg {
        name="ShapingCoefficients12_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients12_Set @ 0x10c4;
    reg {
        name="ShapingCoefficients13_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients13_Set @ 0x10c8;
    reg {
        name="ShapingCoefficients14_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients14_Set @ 0x10cc;
    reg {
        name="ShapingCoefficients15_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients15_Set @ 0x10d0;
    reg {
        name="RampingControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RampingControl_Set @ 0x10d8;
    reg {
        name="RampingLevels_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RampingLevels_Set @ 0x10dc;
    reg {
        name="AnalogRampingControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogRampingControl_Set @ 0x10e0;
    reg {
        name="DirectCurrentOffsetCompensationFilterSettings_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetCompensationFilterSettings_Set @ 0x1110;
    reg {
        name="DirectCurrentOffsetCompensationFilterInitialization_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetCompensationFilterInitialization_Set @ 0x1114;
    reg {
        name="DirectCurrentOffsetEstimatedValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetEstimatedValue_Set @ 0x1118;
    reg {
        name="SampleRateConverterRatioValuesAndChannelFilter_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SampleRateConverterRatioValuesAndChannelFilter_Set @ 0x111c;
    reg {
        name="InternalAutomaticFrequencyControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalAutomaticFrequencyControl_Set @ 0x1120;
    reg {
        name="DetectionOfSignalArrivalThreshold0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold0_Set @ 0x1124;
    reg {
        name="DetectionOfSignalArrivalThreshold1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold1_Set @ 0x1128;
    reg {
        name="DetectionOfSignalArrivalThreshold2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold2_Set @ 0x112c;
    reg {
        name="DetectionOfSignalArrivalThreshold3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold3_Set @ 0x1130;
    reg {
        name="DetectionOfSignalArrivalThreshold4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold4_Set @ 0x1134;
    reg {
        name="DetectionOfSignalArrivalMode_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalMode_Set @ 0x1138;
    reg {
        name="DigitalMixerControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalMixerControl_Set @ 0x113c;
    reg {
        name="ViterbiDemodulator_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulator_Set @ 0x1140;
    reg {
        name="ViterbiDemodulatorCorrelationConfiguration0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorCorrelationConfiguration0_Set @ 0x1144;
    reg {
        name="ViterbiDemodulatorCorrelationConfiguration1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorCorrelationConfiguration1_Set @ 0x1148;
    reg {
        name="ViterbiDemodulatorTrackingLoop_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorTrackingLoop_Set @ 0x114c;
    reg {
        name="ViterbiBleTimingStampControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiBleTimingStampControl_Set @ 0x1150;
    reg {
        name="BaudrateEstimate_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaudrateEstimate_Set @ 0x1154;
    reg {
        name="AutomaticClockGating_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGating_Set @ 0x1158;
    reg {
        name="AutomaticClockGatingClockStop_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGatingClockStop_Set @ 0x115c;
    reg {
        name="PhaseOffsetEstimate_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseOffsetEstimate_Set @ 0x1160;
    reg {
        name="DirectModeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectModeControl_Set @ 0x1164;
    reg {
        name="BleLongRange_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRange_Set @ 0x1168;
    reg {
        name="BleLongRangeSet1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet1_Set @ 0x116c;
    reg {
        name="BleLongRangeSet2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet2_Set @ 0x1170;
    reg {
        name="BleLongRangeSet3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet3_Set @ 0x1174;
    reg {
        name="BleLongRangeSet4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet4_Set @ 0x1178;
    reg {
        name="BleLongRangeSet5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet5_Set @ 0x117c;
    reg {
        name="BleLongRangeSet6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet6_Set @ 0x1180;
    reg {
        name="BleLongRangeFrameControllerInterface_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeFrameControllerInterface_Set @ 0x1184;
    reg {
        name="CoherentDemodulatorSignals0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals0_Set @ 0x1188;
    reg {
        name="CoherentDemodulatorSignals1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals1_Set @ 0x118c;
    reg {
        name="CoherentDemodulatorSignals2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals2_Set @ 0x1190;
    reg {
        name="CoherentDemodulatorSignals3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals3_Set @ 0x1194;
    reg {
        name="Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Set @ 0x1198;
    reg {
        name="SyncWordProperties_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWordProperties_Set @ 0x11a4;
    reg {
        name="DigitalGainControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalGainControl_Set @ 0x11a8;
    reg {
        name="PeripheralReflexSystemControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PeripheralReflexSystemControl_Set @ 0x11ac;
    reg {
        name="PowerAmplifierDebug_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierDebug_Set @ 0x11b0;
    reg {
        name="RealTimeCostFunctionEngineControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RealTimeCostFunctionEngineControl_Set @ 0x11b4;
    reg {
        name="EarlyTimeStampControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EarlyTimeStampControl_Set @ 0x11b8;
    reg {
        name="EarlyTimeStampTiming_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EarlyTimeStampTiming_Set @ 0x11bc;
    reg {
        name="AntennaSwitchControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchControl_Set @ 0x11c0;
    reg {
        name="AntennaSwitchControl1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchControl1_Set @ 0x11c4;
    reg {
        name="AntennaSwitchStart_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchStart_Set @ 0x11c8;
    reg {
        name="AntennaSwitchEnd_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchEnd_Set @ 0x11cc;
    reg {
        name="TrecsPreamblePattern_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsPreamblePattern_Set @ 0x11d0;
    reg {
        name="TrecsPreambleDetectionControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsPreambleDetectionControl_Set @ 0x11d4;
    reg {
        name="TrecsConfiguration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsConfiguration_Set @ 0x11d8;
    reg {
        name="ConfigureAntennaPattern_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigureAntennaPattern_Set @ 0x11dc;
    reg {
        name="ConcurrentMode_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConcurrentMode_Set @ 0x11e0;
    reg {
        name="ChannelFilterCoeSet0Group0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group0_Set @ 0x11e4;
    reg {
        name="ChannelFilterCoeSet0Group1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group1_Set @ 0x11e8;
    reg {
        name="ChannelFilterCoeSet0Group2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group2_Set @ 0x11ec;
    reg {
        name="ChannelFilterCoeSet0Group3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group3_Set @ 0x11f0;
    reg {
        name="ChannelFilterCoeSet0Group4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group4_Set @ 0x11f4;
    reg {
        name="ChannelFilterCoeSet0Group5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group5_Set @ 0x11f8;
    reg {
        name="ChannelFilterCoeSet0Group6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group6_Set @ 0x11fc;
    reg {
        name="ChannelFilterCoeSet1Group0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group0_Set @ 0x1200;
    reg {
        name="ChannelFilterCoeSet1Group1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group1_Set @ 0x1204;
    reg {
        name="ChannelFilterCoeSet1Group2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group2_Set @ 0x1208;
    reg {
        name="ChannelFilterCoeSet1Group3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group3_Set @ 0x120c;
    reg {
        name="ChannelFilterCoeSet1Group4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group4_Set @ 0x1210;
    reg {
        name="ChannelFilterCoeSet1Group5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group5_Set @ 0x1214;
    reg {
        name="ChannelFilterCoeSet1Group6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group6_Set @ 0x1218;
    reg {
        name="ChannelFilterControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterControl_Set @ 0x121c;
    reg {
        name="ChannelFilterLatencyControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterLatencyControl_Set @ 0x1220;
    reg {
        name="FrameSchTimeoutLength_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameSchTimeoutLength_Set @ 0x1224;
    reg {
        name="PreambleFilterCoefficients_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleFilterCoefficients_Set @ 0x1228;
    reg {
        name="CollisionRestartControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CollisionRestartControl_Set @ 0x122c;
    reg {
        name="PreambleSenseMode_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleSenseMode_Set @ 0x1230;
    reg {
        name="PreambleSenseModeExtended_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleSenseModeExtended_Set @ 0x1234;
    reg {
        name="SignalQualityIndicator_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalQualityIndicator_Set @ 0x1238;
    reg {
        name="AntennaDiversityModeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversityModeControl_Set @ 0x123c;
    reg {
        name="PhaseDemodulatorFwMode_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorFwMode_Set @ 0x1240;
    reg {
        name="PhaseDemodulatorAntennaDiversity_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorAntennaDiversity_Set @ 0x1244;
    reg {
        name="PhaseDemodulatorAntennaDiversityDecision_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorAntennaDiversityDecision_Set @ 0x1248;
    reg {
        name="PhaseDemodulatorControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorControl_Set @ 0x124c;
    reg {
        name="SignalIdentifierControl0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl0_Set @ 0x1250;
    reg {
        name="SignalIdentifierControl1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl1_Set @ 0x1254;
    reg {
        name="SignalIdentifierStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierStatus_Set @ 0x1258;
    reg {
        name="ConfigureAntennaPatternExtended_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigureAntennaPatternExtended_Set @ 0x125c;
    reg {
        name="SignalIdentifierControl2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl2_Set @ 0x1264;
    reg {
        name="ChannelFilterSwitchTime_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterSwitchTime_Set @ 0x1268;
    reg {
        name="IrCalibrationControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalibrationControl_Set @ 0x1270;
    reg {
        name="IrCalCoefficientValues_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientValues_Set @ 0x1274;
    reg {
        name="IrCalCoefficientWrPerAntenna0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientWrPerAntenna0_Set @ 0x1278;
    reg {
        name="IrCalCoefficientWrPerAntenna1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientWrPerAntenna1_Set @ 0x127c;
    reg {
        name="AdControl1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdControl1_Set @ 0x1280;
    reg {
        name="AdControl2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdControl2_Set @ 0x1284;
    reg {
        name="AdQual0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual0_Set @ 0x1288;
    reg {
        name="AdQual1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual1_Set @ 0x128c;
    reg {
        name="AdQual2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual2_Set @ 0x1290;
    reg {
        name="AdQual3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual3_Set @ 0x1294;
    reg {
        name="AdQual4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual4_Set @ 0x1298;
    reg {
        name="AdQual5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual5_Set @ 0x129c;
    reg {
        name="AdQual6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual6_Set @ 0x12a0;
    reg {
        name="AdQual7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual7_Set @ 0x12a4;
    reg {
        name="AdQual8_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual8_Set @ 0x12a8;
    reg {
        name="AdQual9_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual9_Set @ 0x12ac;
    reg {
        name="AdQual10_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual10_Set @ 0x12b0;
    reg {
        name="AdFsm0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm0_Set @ 0x12b4;
    reg {
        name="AdFsm1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm1_Set @ 0x12b8;
    reg {
        name="AdFsm2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm2_Set @ 0x12bc;
    reg {
        name="AdFsm3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm3_Set @ 0x12c0;
    reg {
        name="AdFsm4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm4_Set @ 0x12c4;
    reg {
        name="AdFsm5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm5_Set @ 0x12c8;
    reg {
        name="AdFsm6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm6_Set @ 0x12cc;
    reg {
        name="AdFsm7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm7_Set @ 0x12d0;
    reg {
        name="AdFsm8_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm8_Set @ 0x12d4;
    reg {
        name="AdFsm9_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm9_Set @ 0x12d8;
    reg {
        name="AdFsm10_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm10_Set @ 0x12dc;
    reg {
        name="AdFsm11_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm11_Set @ 0x12e0;
    reg {
        name="AdFsm12_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm12_Set @ 0x12e4;
    reg {
        name="AdFsm13_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm13_Set @ 0x12e8;
    reg {
        name="AdFsm14_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm14_Set @ 0x12ec;
    reg {
        name="AdFsm15_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm15_Set @ 0x12f0;
    reg {
        name="AdFsm16_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm16_Set @ 0x12f4;
    reg {
        name="AdFsm17_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm17_Set @ 0x12f8;
    reg {
        name="AdFsm18_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm18_Set @ 0x12fc;
    reg {
        name="AdFsm19_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm19_Set @ 0x1300;
    reg {
        name="AdFsm20_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm20_Set @ 0x1304;
    reg {
        name="AdFsm21_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm21_Set @ 0x1308;
    reg {
        name="AdFsm22_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm22_Set @ 0x130c;
    reg {
        name="AdFsm23_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm23_Set @ 0x1310;
    reg {
        name="AdFsm24_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm24_Set @ 0x1314;
    reg {
        name="AdFsm25_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm25_Set @ 0x1318;
    reg {
        name="AdFsm26_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm26_Set @ 0x131c;
    reg {
        name="AdFsm27_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm27_Set @ 0x1320;
    reg {
        name="AdFsm28_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm28_Set @ 0x1324;
    reg {
        name="AdFsm29_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm29_Set @ 0x1328;
    reg {
        name="AdFsm30_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm30_Set @ 0x132c;
    reg {
        name="AdPc1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc1_Set @ 0x1330;
    reg {
        name="AdPc2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc2_Set @ 0x1334;
    reg {
        name="AdPc3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc3_Set @ 0x1338;
    reg {
        name="AdPc4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc4_Set @ 0x133c;
    reg {
        name="AdPc5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc5_Set @ 0x1340;
    reg {
        name="AdPc6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc6_Set @ 0x1344;
    reg {
        name="AdPc7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc7_Set @ 0x1348;
    reg {
        name="AdPc8_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc8_Set @ 0x134c;
    reg {
        name="AdPc9_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc9_Set @ 0x1350;
    reg {
        name="AdPc10_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc10_Set @ 0x1354;
    reg {
        name="HadmControl0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmControl0_Set @ 0x13b0;
    reg {
        name="HadmControl1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmControl1_Set @ 0x13b4;
    reg {
        name="HadmStatus0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus0_Set @ 0x13b8;
    reg {
        name="HadmStatus1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus1_Set @ 0x13bc;
    reg {
        name="HadmStatus2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus2_Set @ 0x13c0;
    reg {
        name="HadmStatus3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus3_Set @ 0x13c4;
    reg {
        name="HadmStatus4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus4_Set @ 0x13c8;
    reg {
        name="HadmStatus5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus5_Set @ 0x13cc;
    reg {
        name="HadmStatus6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus6_Set @ 0x13d0;
    reg {
        name="Src2NcoControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Src2NcoControl_Set @ 0x13e0;
    reg {
        name="Spare_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Set @ 0x1400;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Enable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Clr @ 0x2004;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x2008;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x200c;
    reg {
        name="SequencerInterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Clr @ 0x2010;
    reg {
        name="SequencerInterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Clr @ 0x2014;
    reg {
        name="Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Clr @ 0x2018;
    reg {
        name="Status2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Clr @ 0x201c;
    reg {
        name="Status3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status3_Clr @ 0x2020;
    reg {
        name="Status4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status4_Clr @ 0x2024;
    reg {
        name="Status5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status5_Clr @ 0x2028;
    reg {
        name="Status6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status6_Clr @ 0x202c;
    reg {
        name="Status7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status7_Clr @ 0x2030;
    reg {
        name="TimingDetectionStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimingDetectionStatus_Clr @ 0x2034;
    reg {
        name="DemodulatorFSMStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DemodulatorFSMStatus_Clr @ 0x2038;
    reg {
        name="FrequencyOffsetEstimate_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetEstimate_Clr @ 0x203c;
    reg {
        name="AutomaticFrequencyControlAdjustmentRx_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControlAdjustmentRx_Clr @ 0x2040;
    reg {
        name="AutomaticFrequencyControldAjustmentTx_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControldAjustmentTx_Clr @ 0x2044;
    reg {
        name="AnalogMixerControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogMixerControl_Clr @ 0x2048;
    reg {
        name="Control0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control0_Clr @ 0x204c;
    reg {
        name="Control1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control1_Clr @ 0x2050;
    reg {
        name="Control2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control2_Clr @ 0x2054;
    reg {
        name="Control3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control3_Clr @ 0x2058;
    reg {
        name="Control4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control4_Clr @ 0x205c;
    reg {
        name="Control5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control5_Clr @ 0x2060;
    reg {
        name="Control6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control6_Clr @ 0x2064;
    reg {
        name="TxBaudrate_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxBaudrate_Clr @ 0x2068;
    reg {
        name="RxBaudrate_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxBaudrate_Clr @ 0x206c;
    reg {
        name="ChannelFilter_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilter_Clr @ 0x2070;
    reg {
        name="Preamble_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Preamble_Clr @ 0x2074;
    reg {
        name="SyncWord0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWord0_Clr @ 0x2078;
    reg {
        name="SyncWord1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWord1_Clr @ 0x207c;
    reg {
        name="Timing_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timing_Clr @ 0x2080;
    reg {
        name="DirectSequenceSpreadSpectrumSymbol0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectSequenceSpreadSpectrumSymbol0_Clr @ 0x2084;
    reg {
        name="ModulationIndex_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModulationIndex_Clr @ 0x2088;
    reg {
        name="AutomaticFrequencyControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControl_Clr @ 0x208c;
    reg {
        name="AutomaticFrequencyControlAdjustmentLimit_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControlAdjustmentLimit_Clr @ 0x2090;
    reg {
        name="ShapingCoefficients0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients0_Clr @ 0x2094;
    reg {
        name="ShapingCoefficients1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients1_Clr @ 0x2098;
    reg {
        name="ShapingCoefficients2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients2_Clr @ 0x209c;
    reg {
        name="ShapingCoefficients3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients3_Clr @ 0x20a0;
    reg {
        name="ShapingCoefficients4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients4_Clr @ 0x20a4;
    reg {
        name="ShapingCoefficients5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients5_Clr @ 0x20a8;
    reg {
        name="ShapingCoefficients6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients6_Clr @ 0x20ac;
    reg {
        name="ShapingCoefficients7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients7_Clr @ 0x20b0;
    reg {
        name="ShapingCoefficients8_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients8_Clr @ 0x20b4;
    reg {
        name="ShapingCoefficients9_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients9_Clr @ 0x20b8;
    reg {
        name="ShapingCoefficients10_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients10_Clr @ 0x20bc;
    reg {
        name="ShapingCoefficients11_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients11_Clr @ 0x20c0;
    reg {
        name="ShapingCoefficients12_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients12_Clr @ 0x20c4;
    reg {
        name="ShapingCoefficients13_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients13_Clr @ 0x20c8;
    reg {
        name="ShapingCoefficients14_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients14_Clr @ 0x20cc;
    reg {
        name="ShapingCoefficients15_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients15_Clr @ 0x20d0;
    reg {
        name="RampingControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RampingControl_Clr @ 0x20d8;
    reg {
        name="RampingLevels_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RampingLevels_Clr @ 0x20dc;
    reg {
        name="AnalogRampingControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogRampingControl_Clr @ 0x20e0;
    reg {
        name="DirectCurrentOffsetCompensationFilterSettings_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetCompensationFilterSettings_Clr @ 0x2110;
    reg {
        name="DirectCurrentOffsetCompensationFilterInitialization_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetCompensationFilterInitialization_Clr @ 0x2114;
    reg {
        name="DirectCurrentOffsetEstimatedValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetEstimatedValue_Clr @ 0x2118;
    reg {
        name="SampleRateConverterRatioValuesAndChannelFilter_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SampleRateConverterRatioValuesAndChannelFilter_Clr @ 0x211c;
    reg {
        name="InternalAutomaticFrequencyControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalAutomaticFrequencyControl_Clr @ 0x2120;
    reg {
        name="DetectionOfSignalArrivalThreshold0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold0_Clr @ 0x2124;
    reg {
        name="DetectionOfSignalArrivalThreshold1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold1_Clr @ 0x2128;
    reg {
        name="DetectionOfSignalArrivalThreshold2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold2_Clr @ 0x212c;
    reg {
        name="DetectionOfSignalArrivalThreshold3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold3_Clr @ 0x2130;
    reg {
        name="DetectionOfSignalArrivalThreshold4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold4_Clr @ 0x2134;
    reg {
        name="DetectionOfSignalArrivalMode_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalMode_Clr @ 0x2138;
    reg {
        name="DigitalMixerControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalMixerControl_Clr @ 0x213c;
    reg {
        name="ViterbiDemodulator_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulator_Clr @ 0x2140;
    reg {
        name="ViterbiDemodulatorCorrelationConfiguration0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorCorrelationConfiguration0_Clr @ 0x2144;
    reg {
        name="ViterbiDemodulatorCorrelationConfiguration1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorCorrelationConfiguration1_Clr @ 0x2148;
    reg {
        name="ViterbiDemodulatorTrackingLoop_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorTrackingLoop_Clr @ 0x214c;
    reg {
        name="ViterbiBleTimingStampControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiBleTimingStampControl_Clr @ 0x2150;
    reg {
        name="BaudrateEstimate_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaudrateEstimate_Clr @ 0x2154;
    reg {
        name="AutomaticClockGating_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGating_Clr @ 0x2158;
    reg {
        name="AutomaticClockGatingClockStop_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGatingClockStop_Clr @ 0x215c;
    reg {
        name="PhaseOffsetEstimate_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseOffsetEstimate_Clr @ 0x2160;
    reg {
        name="DirectModeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectModeControl_Clr @ 0x2164;
    reg {
        name="BleLongRange_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRange_Clr @ 0x2168;
    reg {
        name="BleLongRangeSet1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet1_Clr @ 0x216c;
    reg {
        name="BleLongRangeSet2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet2_Clr @ 0x2170;
    reg {
        name="BleLongRangeSet3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet3_Clr @ 0x2174;
    reg {
        name="BleLongRangeSet4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet4_Clr @ 0x2178;
    reg {
        name="BleLongRangeSet5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet5_Clr @ 0x217c;
    reg {
        name="BleLongRangeSet6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet6_Clr @ 0x2180;
    reg {
        name="BleLongRangeFrameControllerInterface_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeFrameControllerInterface_Clr @ 0x2184;
    reg {
        name="CoherentDemodulatorSignals0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals0_Clr @ 0x2188;
    reg {
        name="CoherentDemodulatorSignals1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals1_Clr @ 0x218c;
    reg {
        name="CoherentDemodulatorSignals2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals2_Clr @ 0x2190;
    reg {
        name="CoherentDemodulatorSignals3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals3_Clr @ 0x2194;
    reg {
        name="Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Clr @ 0x2198;
    reg {
        name="SyncWordProperties_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWordProperties_Clr @ 0x21a4;
    reg {
        name="DigitalGainControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalGainControl_Clr @ 0x21a8;
    reg {
        name="PeripheralReflexSystemControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PeripheralReflexSystemControl_Clr @ 0x21ac;
    reg {
        name="PowerAmplifierDebug_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierDebug_Clr @ 0x21b0;
    reg {
        name="RealTimeCostFunctionEngineControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RealTimeCostFunctionEngineControl_Clr @ 0x21b4;
    reg {
        name="EarlyTimeStampControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EarlyTimeStampControl_Clr @ 0x21b8;
    reg {
        name="EarlyTimeStampTiming_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EarlyTimeStampTiming_Clr @ 0x21bc;
    reg {
        name="AntennaSwitchControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchControl_Clr @ 0x21c0;
    reg {
        name="AntennaSwitchControl1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchControl1_Clr @ 0x21c4;
    reg {
        name="AntennaSwitchStart_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchStart_Clr @ 0x21c8;
    reg {
        name="AntennaSwitchEnd_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchEnd_Clr @ 0x21cc;
    reg {
        name="TrecsPreamblePattern_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsPreamblePattern_Clr @ 0x21d0;
    reg {
        name="TrecsPreambleDetectionControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsPreambleDetectionControl_Clr @ 0x21d4;
    reg {
        name="TrecsConfiguration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsConfiguration_Clr @ 0x21d8;
    reg {
        name="ConfigureAntennaPattern_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigureAntennaPattern_Clr @ 0x21dc;
    reg {
        name="ConcurrentMode_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConcurrentMode_Clr @ 0x21e0;
    reg {
        name="ChannelFilterCoeSet0Group0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group0_Clr @ 0x21e4;
    reg {
        name="ChannelFilterCoeSet0Group1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group1_Clr @ 0x21e8;
    reg {
        name="ChannelFilterCoeSet0Group2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group2_Clr @ 0x21ec;
    reg {
        name="ChannelFilterCoeSet0Group3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group3_Clr @ 0x21f0;
    reg {
        name="ChannelFilterCoeSet0Group4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group4_Clr @ 0x21f4;
    reg {
        name="ChannelFilterCoeSet0Group5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group5_Clr @ 0x21f8;
    reg {
        name="ChannelFilterCoeSet0Group6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group6_Clr @ 0x21fc;
    reg {
        name="ChannelFilterCoeSet1Group0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group0_Clr @ 0x2200;
    reg {
        name="ChannelFilterCoeSet1Group1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group1_Clr @ 0x2204;
    reg {
        name="ChannelFilterCoeSet1Group2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group2_Clr @ 0x2208;
    reg {
        name="ChannelFilterCoeSet1Group3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group3_Clr @ 0x220c;
    reg {
        name="ChannelFilterCoeSet1Group4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group4_Clr @ 0x2210;
    reg {
        name="ChannelFilterCoeSet1Group5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group5_Clr @ 0x2214;
    reg {
        name="ChannelFilterCoeSet1Group6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group6_Clr @ 0x2218;
    reg {
        name="ChannelFilterControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterControl_Clr @ 0x221c;
    reg {
        name="ChannelFilterLatencyControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterLatencyControl_Clr @ 0x2220;
    reg {
        name="FrameSchTimeoutLength_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameSchTimeoutLength_Clr @ 0x2224;
    reg {
        name="PreambleFilterCoefficients_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleFilterCoefficients_Clr @ 0x2228;
    reg {
        name="CollisionRestartControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CollisionRestartControl_Clr @ 0x222c;
    reg {
        name="PreambleSenseMode_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleSenseMode_Clr @ 0x2230;
    reg {
        name="PreambleSenseModeExtended_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleSenseModeExtended_Clr @ 0x2234;
    reg {
        name="SignalQualityIndicator_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalQualityIndicator_Clr @ 0x2238;
    reg {
        name="AntennaDiversityModeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversityModeControl_Clr @ 0x223c;
    reg {
        name="PhaseDemodulatorFwMode_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorFwMode_Clr @ 0x2240;
    reg {
        name="PhaseDemodulatorAntennaDiversity_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorAntennaDiversity_Clr @ 0x2244;
    reg {
        name="PhaseDemodulatorAntennaDiversityDecision_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorAntennaDiversityDecision_Clr @ 0x2248;
    reg {
        name="PhaseDemodulatorControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorControl_Clr @ 0x224c;
    reg {
        name="SignalIdentifierControl0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl0_Clr @ 0x2250;
    reg {
        name="SignalIdentifierControl1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl1_Clr @ 0x2254;
    reg {
        name="SignalIdentifierStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierStatus_Clr @ 0x2258;
    reg {
        name="ConfigureAntennaPatternExtended_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigureAntennaPatternExtended_Clr @ 0x225c;
    reg {
        name="SignalIdentifierControl2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl2_Clr @ 0x2264;
    reg {
        name="ChannelFilterSwitchTime_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterSwitchTime_Clr @ 0x2268;
    reg {
        name="IrCalibrationControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalibrationControl_Clr @ 0x2270;
    reg {
        name="IrCalCoefficientValues_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientValues_Clr @ 0x2274;
    reg {
        name="IrCalCoefficientWrPerAntenna0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientWrPerAntenna0_Clr @ 0x2278;
    reg {
        name="IrCalCoefficientWrPerAntenna1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientWrPerAntenna1_Clr @ 0x227c;
    reg {
        name="AdControl1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdControl1_Clr @ 0x2280;
    reg {
        name="AdControl2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdControl2_Clr @ 0x2284;
    reg {
        name="AdQual0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual0_Clr @ 0x2288;
    reg {
        name="AdQual1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual1_Clr @ 0x228c;
    reg {
        name="AdQual2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual2_Clr @ 0x2290;
    reg {
        name="AdQual3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual3_Clr @ 0x2294;
    reg {
        name="AdQual4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual4_Clr @ 0x2298;
    reg {
        name="AdQual5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual5_Clr @ 0x229c;
    reg {
        name="AdQual6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual6_Clr @ 0x22a0;
    reg {
        name="AdQual7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual7_Clr @ 0x22a4;
    reg {
        name="AdQual8_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual8_Clr @ 0x22a8;
    reg {
        name="AdQual9_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual9_Clr @ 0x22ac;
    reg {
        name="AdQual10_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual10_Clr @ 0x22b0;
    reg {
        name="AdFsm0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm0_Clr @ 0x22b4;
    reg {
        name="AdFsm1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm1_Clr @ 0x22b8;
    reg {
        name="AdFsm2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm2_Clr @ 0x22bc;
    reg {
        name="AdFsm3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm3_Clr @ 0x22c0;
    reg {
        name="AdFsm4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm4_Clr @ 0x22c4;
    reg {
        name="AdFsm5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm5_Clr @ 0x22c8;
    reg {
        name="AdFsm6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm6_Clr @ 0x22cc;
    reg {
        name="AdFsm7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm7_Clr @ 0x22d0;
    reg {
        name="AdFsm8_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm8_Clr @ 0x22d4;
    reg {
        name="AdFsm9_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm9_Clr @ 0x22d8;
    reg {
        name="AdFsm10_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm10_Clr @ 0x22dc;
    reg {
        name="AdFsm11_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm11_Clr @ 0x22e0;
    reg {
        name="AdFsm12_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm12_Clr @ 0x22e4;
    reg {
        name="AdFsm13_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm13_Clr @ 0x22e8;
    reg {
        name="AdFsm14_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm14_Clr @ 0x22ec;
    reg {
        name="AdFsm15_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm15_Clr @ 0x22f0;
    reg {
        name="AdFsm16_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm16_Clr @ 0x22f4;
    reg {
        name="AdFsm17_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm17_Clr @ 0x22f8;
    reg {
        name="AdFsm18_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm18_Clr @ 0x22fc;
    reg {
        name="AdFsm19_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm19_Clr @ 0x2300;
    reg {
        name="AdFsm20_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm20_Clr @ 0x2304;
    reg {
        name="AdFsm21_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm21_Clr @ 0x2308;
    reg {
        name="AdFsm22_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm22_Clr @ 0x230c;
    reg {
        name="AdFsm23_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm23_Clr @ 0x2310;
    reg {
        name="AdFsm24_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm24_Clr @ 0x2314;
    reg {
        name="AdFsm25_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm25_Clr @ 0x2318;
    reg {
        name="AdFsm26_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm26_Clr @ 0x231c;
    reg {
        name="AdFsm27_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm27_Clr @ 0x2320;
    reg {
        name="AdFsm28_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm28_Clr @ 0x2324;
    reg {
        name="AdFsm29_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm29_Clr @ 0x2328;
    reg {
        name="AdFsm30_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm30_Clr @ 0x232c;
    reg {
        name="AdPc1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc1_Clr @ 0x2330;
    reg {
        name="AdPc2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc2_Clr @ 0x2334;
    reg {
        name="AdPc3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc3_Clr @ 0x2338;
    reg {
        name="AdPc4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc4_Clr @ 0x233c;
    reg {
        name="AdPc5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc5_Clr @ 0x2340;
    reg {
        name="AdPc6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc6_Clr @ 0x2344;
    reg {
        name="AdPc7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc7_Clr @ 0x2348;
    reg {
        name="AdPc8_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc8_Clr @ 0x234c;
    reg {
        name="AdPc9_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc9_Clr @ 0x2350;
    reg {
        name="AdPc10_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc10_Clr @ 0x2354;
    reg {
        name="HadmControl0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmControl0_Clr @ 0x23b0;
    reg {
        name="HadmControl1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmControl1_Clr @ 0x23b4;
    reg {
        name="HadmStatus0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus0_Clr @ 0x23b8;
    reg {
        name="HadmStatus1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus1_Clr @ 0x23bc;
    reg {
        name="HadmStatus2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus2_Clr @ 0x23c0;
    reg {
        name="HadmStatus3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus3_Clr @ 0x23c4;
    reg {
        name="HadmStatus4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus4_Clr @ 0x23c8;
    reg {
        name="HadmStatus5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus5_Clr @ 0x23cc;
    reg {
        name="HadmStatus6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus6_Clr @ 0x23d0;
    reg {
        name="Src2NcoControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Src2NcoControl_Clr @ 0x23e0;
    reg {
        name="Spare_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Clr @ 0x2400;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Enable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Tgl @ 0x3004;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x3008;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x300c;
    reg {
        name="SequencerInterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Tgl @ 0x3010;
    reg {
        name="SequencerInterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Tgl @ 0x3014;
    reg {
        name="Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Tgl @ 0x3018;
    reg {
        name="Status2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Tgl @ 0x301c;
    reg {
        name="Status3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status3_Tgl @ 0x3020;
    reg {
        name="Status4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status4_Tgl @ 0x3024;
    reg {
        name="Status5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status5_Tgl @ 0x3028;
    reg {
        name="Status6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status6_Tgl @ 0x302c;
    reg {
        name="Status7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status7_Tgl @ 0x3030;
    reg {
        name="TimingDetectionStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimingDetectionStatus_Tgl @ 0x3034;
    reg {
        name="DemodulatorFSMStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DemodulatorFSMStatus_Tgl @ 0x3038;
    reg {
        name="FrequencyOffsetEstimate_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetEstimate_Tgl @ 0x303c;
    reg {
        name="AutomaticFrequencyControlAdjustmentRx_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControlAdjustmentRx_Tgl @ 0x3040;
    reg {
        name="AutomaticFrequencyControldAjustmentTx_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControldAjustmentTx_Tgl @ 0x3044;
    reg {
        name="AnalogMixerControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogMixerControl_Tgl @ 0x3048;
    reg {
        name="Control0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control0_Tgl @ 0x304c;
    reg {
        name="Control1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control1_Tgl @ 0x3050;
    reg {
        name="Control2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control2_Tgl @ 0x3054;
    reg {
        name="Control3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control3_Tgl @ 0x3058;
    reg {
        name="Control4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control4_Tgl @ 0x305c;
    reg {
        name="Control5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control5_Tgl @ 0x3060;
    reg {
        name="Control6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control6_Tgl @ 0x3064;
    reg {
        name="TxBaudrate_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxBaudrate_Tgl @ 0x3068;
    reg {
        name="RxBaudrate_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxBaudrate_Tgl @ 0x306c;
    reg {
        name="ChannelFilter_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilter_Tgl @ 0x3070;
    reg {
        name="Preamble_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Preamble_Tgl @ 0x3074;
    reg {
        name="SyncWord0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWord0_Tgl @ 0x3078;
    reg {
        name="SyncWord1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWord1_Tgl @ 0x307c;
    reg {
        name="Timing_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timing_Tgl @ 0x3080;
    reg {
        name="DirectSequenceSpreadSpectrumSymbol0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectSequenceSpreadSpectrumSymbol0_Tgl @ 0x3084;
    reg {
        name="ModulationIndex_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModulationIndex_Tgl @ 0x3088;
    reg {
        name="AutomaticFrequencyControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControl_Tgl @ 0x308c;
    reg {
        name="AutomaticFrequencyControlAdjustmentLimit_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticFrequencyControlAdjustmentLimit_Tgl @ 0x3090;
    reg {
        name="ShapingCoefficients0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients0_Tgl @ 0x3094;
    reg {
        name="ShapingCoefficients1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients1_Tgl @ 0x3098;
    reg {
        name="ShapingCoefficients2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients2_Tgl @ 0x309c;
    reg {
        name="ShapingCoefficients3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients3_Tgl @ 0x30a0;
    reg {
        name="ShapingCoefficients4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients4_Tgl @ 0x30a4;
    reg {
        name="ShapingCoefficients5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients5_Tgl @ 0x30a8;
    reg {
        name="ShapingCoefficients6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients6_Tgl @ 0x30ac;
    reg {
        name="ShapingCoefficients7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients7_Tgl @ 0x30b0;
    reg {
        name="ShapingCoefficients8_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients8_Tgl @ 0x30b4;
    reg {
        name="ShapingCoefficients9_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients9_Tgl @ 0x30b8;
    reg {
        name="ShapingCoefficients10_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients10_Tgl @ 0x30bc;
    reg {
        name="ShapingCoefficients11_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients11_Tgl @ 0x30c0;
    reg {
        name="ShapingCoefficients12_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients12_Tgl @ 0x30c4;
    reg {
        name="ShapingCoefficients13_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients13_Tgl @ 0x30c8;
    reg {
        name="ShapingCoefficients14_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients14_Tgl @ 0x30cc;
    reg {
        name="ShapingCoefficients15_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ShapingCoefficients15_Tgl @ 0x30d0;
    reg {
        name="RampingControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RampingControl_Tgl @ 0x30d8;
    reg {
        name="RampingLevels_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RampingLevels_Tgl @ 0x30dc;
    reg {
        name="AnalogRampingControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogRampingControl_Tgl @ 0x30e0;
    reg {
        name="DirectCurrentOffsetCompensationFilterSettings_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetCompensationFilterSettings_Tgl @ 0x3110;
    reg {
        name="DirectCurrentOffsetCompensationFilterInitialization_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetCompensationFilterInitialization_Tgl @ 0x3114;
    reg {
        name="DirectCurrentOffsetEstimatedValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectCurrentOffsetEstimatedValue_Tgl @ 0x3118;
    reg {
        name="SampleRateConverterRatioValuesAndChannelFilter_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SampleRateConverterRatioValuesAndChannelFilter_Tgl @ 0x311c;
    reg {
        name="InternalAutomaticFrequencyControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InternalAutomaticFrequencyControl_Tgl @ 0x3120;
    reg {
        name="DetectionOfSignalArrivalThreshold0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold0_Tgl @ 0x3124;
    reg {
        name="DetectionOfSignalArrivalThreshold1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold1_Tgl @ 0x3128;
    reg {
        name="DetectionOfSignalArrivalThreshold2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold2_Tgl @ 0x312c;
    reg {
        name="DetectionOfSignalArrivalThreshold3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold3_Tgl @ 0x3130;
    reg {
        name="DetectionOfSignalArrivalThreshold4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalThreshold4_Tgl @ 0x3134;
    reg {
        name="DetectionOfSignalArrivalMode_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DetectionOfSignalArrivalMode_Tgl @ 0x3138;
    reg {
        name="DigitalMixerControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalMixerControl_Tgl @ 0x313c;
    reg {
        name="ViterbiDemodulator_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulator_Tgl @ 0x3140;
    reg {
        name="ViterbiDemodulatorCorrelationConfiguration0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorCorrelationConfiguration0_Tgl @ 0x3144;
    reg {
        name="ViterbiDemodulatorCorrelationConfiguration1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorCorrelationConfiguration1_Tgl @ 0x3148;
    reg {
        name="ViterbiDemodulatorTrackingLoop_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiDemodulatorTrackingLoop_Tgl @ 0x314c;
    reg {
        name="ViterbiBleTimingStampControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ViterbiBleTimingStampControl_Tgl @ 0x3150;
    reg {
        name="BaudrateEstimate_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaudrateEstimate_Tgl @ 0x3154;
    reg {
        name="AutomaticClockGating_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGating_Tgl @ 0x3158;
    reg {
        name="AutomaticClockGatingClockStop_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticClockGatingClockStop_Tgl @ 0x315c;
    reg {
        name="PhaseOffsetEstimate_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseOffsetEstimate_Tgl @ 0x3160;
    reg {
        name="DirectModeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DirectModeControl_Tgl @ 0x3164;
    reg {
        name="BleLongRange_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRange_Tgl @ 0x3168;
    reg {
        name="BleLongRangeSet1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet1_Tgl @ 0x316c;
    reg {
        name="BleLongRangeSet2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet2_Tgl @ 0x3170;
    reg {
        name="BleLongRangeSet3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet3_Tgl @ 0x3174;
    reg {
        name="BleLongRangeSet4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet4_Tgl @ 0x3178;
    reg {
        name="BleLongRangeSet5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet5_Tgl @ 0x317c;
    reg {
        name="BleLongRangeSet6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeSet6_Tgl @ 0x3180;
    reg {
        name="BleLongRangeFrameControllerInterface_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BleLongRangeFrameControllerInterface_Tgl @ 0x3184;
    reg {
        name="CoherentDemodulatorSignals0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals0_Tgl @ 0x3188;
    reg {
        name="CoherentDemodulatorSignals1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals1_Tgl @ 0x318c;
    reg {
        name="CoherentDemodulatorSignals2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals2_Tgl @ 0x3190;
    reg {
        name="CoherentDemodulatorSignals3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CoherentDemodulatorSignals3_Tgl @ 0x3194;
    reg {
        name="Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Tgl @ 0x3198;
    reg {
        name="SyncWordProperties_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWordProperties_Tgl @ 0x31a4;
    reg {
        name="DigitalGainControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalGainControl_Tgl @ 0x31a8;
    reg {
        name="PeripheralReflexSystemControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PeripheralReflexSystemControl_Tgl @ 0x31ac;
    reg {
        name="PowerAmplifierDebug_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierDebug_Tgl @ 0x31b0;
    reg {
        name="RealTimeCostFunctionEngineControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RealTimeCostFunctionEngineControl_Tgl @ 0x31b4;
    reg {
        name="EarlyTimeStampControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EarlyTimeStampControl_Tgl @ 0x31b8;
    reg {
        name="EarlyTimeStampTiming_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EarlyTimeStampTiming_Tgl @ 0x31bc;
    reg {
        name="AntennaSwitchControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchControl_Tgl @ 0x31c0;
    reg {
        name="AntennaSwitchControl1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchControl1_Tgl @ 0x31c4;
    reg {
        name="AntennaSwitchStart_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchStart_Tgl @ 0x31c8;
    reg {
        name="AntennaSwitchEnd_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaSwitchEnd_Tgl @ 0x31cc;
    reg {
        name="TrecsPreamblePattern_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsPreamblePattern_Tgl @ 0x31d0;
    reg {
        name="TrecsPreambleDetectionControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsPreambleDetectionControl_Tgl @ 0x31d4;
    reg {
        name="TrecsConfiguration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TrecsConfiguration_Tgl @ 0x31d8;
    reg {
        name="ConfigureAntennaPattern_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigureAntennaPattern_Tgl @ 0x31dc;
    reg {
        name="ConcurrentMode_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConcurrentMode_Tgl @ 0x31e0;
    reg {
        name="ChannelFilterCoeSet0Group0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group0_Tgl @ 0x31e4;
    reg {
        name="ChannelFilterCoeSet0Group1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group1_Tgl @ 0x31e8;
    reg {
        name="ChannelFilterCoeSet0Group2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group2_Tgl @ 0x31ec;
    reg {
        name="ChannelFilterCoeSet0Group3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group3_Tgl @ 0x31f0;
    reg {
        name="ChannelFilterCoeSet0Group4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group4_Tgl @ 0x31f4;
    reg {
        name="ChannelFilterCoeSet0Group5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group5_Tgl @ 0x31f8;
    reg {
        name="ChannelFilterCoeSet0Group6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet0Group6_Tgl @ 0x31fc;
    reg {
        name="ChannelFilterCoeSet1Group0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group0_Tgl @ 0x3200;
    reg {
        name="ChannelFilterCoeSet1Group1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group1_Tgl @ 0x3204;
    reg {
        name="ChannelFilterCoeSet1Group2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group2_Tgl @ 0x3208;
    reg {
        name="ChannelFilterCoeSet1Group3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group3_Tgl @ 0x320c;
    reg {
        name="ChannelFilterCoeSet1Group4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group4_Tgl @ 0x3210;
    reg {
        name="ChannelFilterCoeSet1Group5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group5_Tgl @ 0x3214;
    reg {
        name="ChannelFilterCoeSet1Group6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterCoeSet1Group6_Tgl @ 0x3218;
    reg {
        name="ChannelFilterControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterControl_Tgl @ 0x321c;
    reg {
        name="ChannelFilterLatencyControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterLatencyControl_Tgl @ 0x3220;
    reg {
        name="FrameSchTimeoutLength_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameSchTimeoutLength_Tgl @ 0x3224;
    reg {
        name="PreambleFilterCoefficients_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleFilterCoefficients_Tgl @ 0x3228;
    reg {
        name="CollisionRestartControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CollisionRestartControl_Tgl @ 0x322c;
    reg {
        name="PreambleSenseMode_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleSenseMode_Tgl @ 0x3230;
    reg {
        name="PreambleSenseModeExtended_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleSenseModeExtended_Tgl @ 0x3234;
    reg {
        name="SignalQualityIndicator_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalQualityIndicator_Tgl @ 0x3238;
    reg {
        name="AntennaDiversityModeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversityModeControl_Tgl @ 0x323c;
    reg {
        name="PhaseDemodulatorFwMode_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorFwMode_Tgl @ 0x3240;
    reg {
        name="PhaseDemodulatorAntennaDiversity_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorAntennaDiversity_Tgl @ 0x3244;
    reg {
        name="PhaseDemodulatorAntennaDiversityDecision_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorAntennaDiversityDecision_Tgl @ 0x3248;
    reg {
        name="PhaseDemodulatorControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PhaseDemodulatorControl_Tgl @ 0x324c;
    reg {
        name="SignalIdentifierControl0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl0_Tgl @ 0x3250;
    reg {
        name="SignalIdentifierControl1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl1_Tgl @ 0x3254;
    reg {
        name="SignalIdentifierStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierStatus_Tgl @ 0x3258;
    reg {
        name="ConfigureAntennaPatternExtended_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigureAntennaPatternExtended_Tgl @ 0x325c;
    reg {
        name="SignalIdentifierControl2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalIdentifierControl2_Tgl @ 0x3264;
    reg {
        name="ChannelFilterSwitchTime_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterSwitchTime_Tgl @ 0x3268;
    reg {
        name="IrCalibrationControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalibrationControl_Tgl @ 0x3270;
    reg {
        name="IrCalCoefficientValues_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientValues_Tgl @ 0x3274;
    reg {
        name="IrCalCoefficientWrPerAntenna0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientWrPerAntenna0_Tgl @ 0x3278;
    reg {
        name="IrCalCoefficientWrPerAntenna1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IrCalCoefficientWrPerAntenna1_Tgl @ 0x327c;
    reg {
        name="AdControl1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdControl1_Tgl @ 0x3280;
    reg {
        name="AdControl2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdControl2_Tgl @ 0x3284;
    reg {
        name="AdQual0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual0_Tgl @ 0x3288;
    reg {
        name="AdQual1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual1_Tgl @ 0x328c;
    reg {
        name="AdQual2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual2_Tgl @ 0x3290;
    reg {
        name="AdQual3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual3_Tgl @ 0x3294;
    reg {
        name="AdQual4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual4_Tgl @ 0x3298;
    reg {
        name="AdQual5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual5_Tgl @ 0x329c;
    reg {
        name="AdQual6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual6_Tgl @ 0x32a0;
    reg {
        name="AdQual7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual7_Tgl @ 0x32a4;
    reg {
        name="AdQual8_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual8_Tgl @ 0x32a8;
    reg {
        name="AdQual9_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual9_Tgl @ 0x32ac;
    reg {
        name="AdQual10_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdQual10_Tgl @ 0x32b0;
    reg {
        name="AdFsm0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm0_Tgl @ 0x32b4;
    reg {
        name="AdFsm1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm1_Tgl @ 0x32b8;
    reg {
        name="AdFsm2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm2_Tgl @ 0x32bc;
    reg {
        name="AdFsm3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm3_Tgl @ 0x32c0;
    reg {
        name="AdFsm4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm4_Tgl @ 0x32c4;
    reg {
        name="AdFsm5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm5_Tgl @ 0x32c8;
    reg {
        name="AdFsm6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm6_Tgl @ 0x32cc;
    reg {
        name="AdFsm7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm7_Tgl @ 0x32d0;
    reg {
        name="AdFsm8_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm8_Tgl @ 0x32d4;
    reg {
        name="AdFsm9_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm9_Tgl @ 0x32d8;
    reg {
        name="AdFsm10_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm10_Tgl @ 0x32dc;
    reg {
        name="AdFsm11_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm11_Tgl @ 0x32e0;
    reg {
        name="AdFsm12_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm12_Tgl @ 0x32e4;
    reg {
        name="AdFsm13_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm13_Tgl @ 0x32e8;
    reg {
        name="AdFsm14_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm14_Tgl @ 0x32ec;
    reg {
        name="AdFsm15_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm15_Tgl @ 0x32f0;
    reg {
        name="AdFsm16_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm16_Tgl @ 0x32f4;
    reg {
        name="AdFsm17_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm17_Tgl @ 0x32f8;
    reg {
        name="AdFsm18_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm18_Tgl @ 0x32fc;
    reg {
        name="AdFsm19_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm19_Tgl @ 0x3300;
    reg {
        name="AdFsm20_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm20_Tgl @ 0x3304;
    reg {
        name="AdFsm21_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm21_Tgl @ 0x3308;
    reg {
        name="AdFsm22_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm22_Tgl @ 0x330c;
    reg {
        name="AdFsm23_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm23_Tgl @ 0x3310;
    reg {
        name="AdFsm24_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm24_Tgl @ 0x3314;
    reg {
        name="AdFsm25_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm25_Tgl @ 0x3318;
    reg {
        name="AdFsm26_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm26_Tgl @ 0x331c;
    reg {
        name="AdFsm27_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm27_Tgl @ 0x3320;
    reg {
        name="AdFsm28_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm28_Tgl @ 0x3324;
    reg {
        name="AdFsm29_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm29_Tgl @ 0x3328;
    reg {
        name="AdFsm30_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdFsm30_Tgl @ 0x332c;
    reg {
        name="AdPc1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc1_Tgl @ 0x3330;
    reg {
        name="AdPc2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc2_Tgl @ 0x3334;
    reg {
        name="AdPc3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc3_Tgl @ 0x3338;
    reg {
        name="AdPc4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc4_Tgl @ 0x333c;
    reg {
        name="AdPc5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc5_Tgl @ 0x3340;
    reg {
        name="AdPc6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc6_Tgl @ 0x3344;
    reg {
        name="AdPc7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc7_Tgl @ 0x3348;
    reg {
        name="AdPc8_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc8_Tgl @ 0x334c;
    reg {
        name="AdPc9_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc9_Tgl @ 0x3350;
    reg {
        name="AdPc10_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdPc10_Tgl @ 0x3354;
    reg {
        name="HadmControl0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmControl0_Tgl @ 0x33b0;
    reg {
        name="HadmControl1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmControl1_Tgl @ 0x33b4;
    reg {
        name="HadmStatus0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus0_Tgl @ 0x33b8;
    reg {
        name="HadmStatus1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus1_Tgl @ 0x33bc;
    reg {
        name="HadmStatus2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus2_Tgl @ 0x33c0;
    reg {
        name="HadmStatus3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus3_Tgl @ 0x33c4;
    reg {
        name="HadmStatus4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus4_Tgl @ 0x33c8;
    reg {
        name="HadmStatus5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus5_Tgl @ 0x33cc;
    reg {
        name="HadmStatus6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HadmStatus6_Tgl @ 0x33d0;
    reg {
        name="Src2NcoControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Src2NcoControl_Tgl @ 0x33e0;
    reg {
        name="Spare_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Tgl @ 0x3400;
} ModulatorAndDemodulatorRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion @ 0x0;
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x4;
    reg {
        name="Status0";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAININDEX[5:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDLOWLAT[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDHILAT[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IFPKDLOLAT[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IFPKDHILAT[9:9];
            field {
                sw = r;
            } CCA[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINOK[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PGAINDEX[15:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LNAINDEX[19:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PNIINDEX[24:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADCINDEX[26:25];
    } Status0 @ 0x8;
    reg {
        name="Status1";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CHPWR[7:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FASTLOOPSTATE[12:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFLOOPSTATE[14:13];
            field {
                sw = rw;
            } RSSISTATE[17:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFLOOPSTATE_[29:18];
    } Status1 @ 0xc;
    reg {
        name="Status2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2 @ 0x10;
    reg {
        name="ReceivedSignalStrengthIndicator";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RSSIFRAC[7:6];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
                reset=8'b10000000;
            } RSSIINT[15:8];
    } ReceivedSignalStrengthIndicator @ 0x18;
    reg {
        name="FrameReceivedSignalStrengthIndicator";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } FRAMERSSIFRAC[7:6];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
                reset=8'b10000000;
            } FRAMERSSIINT[15:8];
    } FrameReceivedSignalStrengthIndicator @ 0x1c;
    reg {
        name="Control0";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=8'b1111111;
            } PWRTARGET[7:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=3'b10;
            } MODE[10:8];
            field {
                sw = rw;
                reset=8'b1001110;
            } RSSISHIFT[18:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DISCFLOOPADJ[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } CFLOOPNFADJ[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } CFLOOPNEWCALC[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DISRESETCHPWR[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADCATTENMODE[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } FENOTCHMODESEL[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ADCATTENCODE[26:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ENRSSIRESET[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DSADISCFLOOP[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } DISPNGAINUP[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DISPNDWNCOMP[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } AGCRST[31:31];
    } Control0 @ 0x20;
    reg {
        name="Control1";
        regwidth=0x20;
            field {
                sw = rw;
            } CCATHRSH[7:0];
            field {
                sw = rw;
                reset=4'b11;
            } RSSIPERIOD[11:8];
            field {
                sw = rw;
                reset=3'b1;
            } PWRPERIOD[14:12];
            field {
                sw = rw;
            } CCAMODE[16:15];
            field {
                sw = rw;
            } CCAMODE3LOGIC[17:17];
            field {
                sw = rw;
            } CCASWCTRL[18:18];
    } Control1 @ 0x24;
    reg {
        name="Control2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control2 @ 0x28;
    reg {
        name="Control3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control3 @ 0x2c;
    reg {
        name="Control4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control4 @ 0x30;
    reg {
        name="Control5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control5 @ 0x34;
    reg {
        name="Control6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control6 @ 0x38;
    reg {
        name="Control7";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SUBDEN[7:0];
            field {
                sw = rw;
            } SUBINT[15:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SUBNUM[23:16];
            field {
                sw = rw;
            } SUBPERIOD[24:24];
    } Control7 @ 0x3c;
    reg {
        name="ReceivedSignalStrengthIndicatorStepThreshold";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicatorStepThreshold @ 0x40;
    reg {
        name="ManualGain";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ManualGain @ 0x44;
    reg {
        name="InterruptFlags";
        regwidth=0x20;
            field {
                sw = rw;
            } RSSIVALIDIF[0:0];
            field {
                sw = rw;
            } CCAIF[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSSIPOSSTEPIF[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSSINEGSTEPIF[4:4];
            field {
                sw = rw;
            } RSSIDONEIF[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SHORTRSSIPOSSTEPIF[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDPRDDONEIF[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDCNTDONEIF[9:9];
            field {
                sw = rw;
            } RSSIHIGHIF[10:10];
            field {
                sw = rw;
            } RSSILOWIF[11:11];
            field {
                sw = rw;
            } CCANODETIF[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINBELOWGAINTHDIF[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINUPDATEFRZIF[14:14];
    } InterruptFlags @ 0x48;
    reg {
        name="InterruptEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } RSSIVALIDIEN[0:0];
            field {
                sw = rw;
            } CCAIEN[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSSIPOSSTEPIEN[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSSINEGSTEPIEN[4:4];
            field {
                sw = rw;
            } RSSIDONEIEN[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SHORTRSSIPOSSTEPIEN[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDPRDDONEIEN[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDCNTDONEIEN[9:9];
            field {
                sw = rw;
            } RSSIHIGHIEN[10:10];
            field {
                sw = rw;
            } RSSILOWIEN[11:11];
            field {
                sw = rw;
            } CCANODETIEN[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINBELOWGAINTHDIEN[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINUPDATEFRZIEN[14:14];
    } InterruptEnable @ 0x4c;
    reg {
        name="Command";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } RSSISTART[0:0];
    } Command @ 0x50;
    reg {
        name="RxGainRange";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxGainRange @ 0x54;
    reg {
        name="AutomaticGainControlPeriod0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlPeriod0 @ 0x58;
    reg {
        name="AutomaticGainControlPeriod1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlPeriod1 @ 0x5c;
    reg {
        name="HiCounterRegion0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion0 @ 0x60;
    reg {
        name="HiCounterRegion1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion1 @ 0x64;
    reg {
        name="HiCounterRegion2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion2 @ 0x68;
    reg {
        name="GainStepsLimits0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GainStepsLimits0 @ 0x6c;
    reg {
        name="GainStepsLimits1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GainStepsLimits1 @ 0x70;
    reg {
        name="PnRfAttenuationCodeGroup0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup0 @ 0x74;
    reg {
        name="PnRfAttenuationCodeGroup1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup1 @ 0x78;
    reg {
        name="PnRfAttenuationCodeGroup2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup2 @ 0x7c;
    reg {
        name="PnRfAttenuationCodeGroup3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup3 @ 0x80;
    reg {
        name="PnRfAttenuationCodeGroup4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup4 @ 0x84;
    reg {
        name="PnRfAttenuationCodeGroup5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup5 @ 0x88;
    reg {
        name="PnRfAttenuationCodeGroup6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup6 @ 0x8c;
    reg {
        name="PnRfAttenuationCodeGroup7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup7 @ 0x90;
    reg {
        name="PnRfAttenuationCodeGroupAlternate";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroupAlternate @ 0xa4;
    reg {
        name="LnaMixSliceCodeGroup0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaMixSliceCodeGroup0 @ 0xa8;
    reg {
        name="LnaMixSliceCodeGroup1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaMixSliceCodeGroup1 @ 0xac;
    reg {
        name="ProgrammableGainAmplifierGainCodeGroup0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierGainCodeGroup0 @ 0xb0;
    reg {
        name="ProgrammableGainAmplifierGainCodeGroup1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierGainCodeGroup1 @ 0xb4;
    reg {
        name="ListenBeforeTalkConfiguration";
        regwidth=0x20;
            field {
                sw = rw;
            } CCARSSIPERIOD[3:0];
            field {
                sw = rw;
            } ENCCARSSIPERIOD[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ENCCAGAINREDUCED[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ENCCARSSIMAX[6:6];
    } ListenBeforeTalkConfiguration @ 0xb8;
    reg {
        name="MirrorInterruptFlags";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MirrorInterruptFlags @ 0xbc;
    reg {
        name="SequencerInterruptFlags";
        regwidth=0x20;
            field {
                sw = rw;
            } RSSIVALIDSEQIF[0:0];
            field {
                sw = rw;
            } CCASEQIF[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSSIPOSSTEPSEQIF[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSSINEGSTEPSEQIF[4:4];
            field {
                sw = rw;
            } RSSIDONESEQIF[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SHORTRSSIPOSSTEPSEQIF[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDPRDDONESEQIF[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDCNTDONESEQIF[9:9];
            field {
                sw = rw;
            } RSSIHIGHSEQIF[10:10];
            field {
                sw = rw;
            } RSSILOWSEQIF[11:11];
            field {
                sw = rw;
            } CCANODETSEQIF[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINBELOWGAINTHDSEQIF[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINUPDATEFRZSEQIF[14:14];
    } SequencerInterruptFlags @ 0xc0;
    reg {
        name="SequencerInterruptEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } RSSIVALIDSEQIEN[0:0];
            field {
                sw = rw;
            } CCASEQIEN[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSSIPOSSTEPSEQIEN[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSSINEGSTEPSEQIEN[4:4];
            field {
                sw = rw;
            } RSSIDONESEQIEN[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SHORTRSSIPOSSTEPSEQIEN[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDPRDDONESEQIEN[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RFPKDCNTDONESEQIEN[9:9];
            field {
                sw = rw;
            } RSSIHIGHSEQIEN[10:10];
            field {
                sw = rw;
            } RSSILOWSEQIEN[11:11];
            field {
                sw = rw;
            } CCANODETSEQIEN[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINBELOWGAINTHDSEQIEN[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GAINUPDATEFRZSEQIEN[14:14];
    } SequencerInterruptEnable @ 0xc4;
    reg {
        name="ReceivedSignalStrengthIndicatorAbsoluteThreshold";
        regwidth=0x20;
            field {
                sw = rw;
            } RSSIHIGHTHRSH[7:0];
            field {
                sw = rw;
            } RSSILOWTHRSH[15:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIRSSIHIGHTHR[23:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SIRSSINEGSTEPTHR[31:24];
    } ReceivedSignalStrengthIndicatorAbsoluteThreshold @ 0xc8;
    reg {
        name="LnaBoostControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaBoostControl @ 0xcc;
    reg {
        name="AntennaDiversity";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversity @ 0xd0;
    reg {
        name="DualRfpkdThreshold0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DualRfpkdThreshold0 @ 0xd4;
    reg {
        name="DualRfpkdThreshold1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DualRfpkdThreshold1 @ 0xd8;
    reg {
        name="Spare";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare @ 0xdc;
    reg {
        name="PnRfFilterCodeGroup0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup0 @ 0xe0;
    reg {
        name="PnRfFilterCodeGroup1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup1 @ 0xe4;
    reg {
        name="PnRfFilterCodeGroup2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup2 @ 0xe8;
    reg {
        name="PnRfFilterCodeGroup3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup3 @ 0xec;
    reg {
        name="PnRfFilterCodeGroup4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup4 @ 0xf0;
    reg {
        name="PnRfFilterCodeGroup5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup5 @ 0xf4;
    reg {
        name="PnRfFilterCodeGroup6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup6 @ 0xf8;
    reg {
        name="PnRfFilterCodeGroup7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup7 @ 0xfc;
    reg {
        name="FeNotchAttenuationCodeGroup0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup0 @ 0x100;
    reg {
        name="FeNotchAttenuationCodeGroup1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup1 @ 0x104;
    reg {
        name="FeNotchAttenuationCodeGroup2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup2 @ 0x108;
    reg {
        name="FeNotchAttenuationCodeGroup3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup3 @ 0x10c;
    reg {
        name="FeNotchAttenuationCodeGroup4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup4 @ 0x110;
    reg {
        name="FeNotchAttenuationCodeGroup5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup5 @ 0x114;
    reg {
        name="FeNotchAttenuationCodeGroup6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup6 @ 0x118;
    reg {
        name="FeNotchAttenuationCodeGroup7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup7 @ 0x11c;
    reg {
        name="FeNotchAttenuationCodeGroup8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup8 @ 0x120;
    reg {
        name="FeNotchAttenuationCodeGroup9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup9 @ 0x124;
    reg {
        name="FeNotchAttenuationCodeGroup10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup10 @ 0x128;
    reg {
        name="FeNotchAttenuationCodeGroup11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup11 @ 0x12c;
    reg {
        name="FeNotchFilterCodeGroup0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup0 @ 0x130;
    reg {
        name="FeNotchFilterCodeGroup1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup1 @ 0x134;
    reg {
        name="FeNotchFilterCodeGroup2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup2 @ 0x138;
    reg {
        name="FeNotchFilterCodeGroup3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup3 @ 0x13c;
    reg {
        name="FeNotchFilterCodeGroup4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup4 @ 0x140;
    reg {
        name="FeNotchFilterCodeGroup5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup5 @ 0x144;
    reg {
        name="FeNotchFilterCodeGroup6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup6 @ 0x148;
    reg {
        name="FeNotchFilterCodeGroup7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup7 @ 0x14c;
    reg {
        name="FeNotchFilterCodeGroup8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup8 @ 0x150;
    reg {
        name="FeNotchFilterCodeGroup9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup9 @ 0x154;
    reg {
        name="FeNotchFilterCodeGroup10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup10 @ 0x158;
    reg {
        name="FeNotchFilterCodeGroup11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup11 @ 0x15c;
    reg {
        name="ClearChannelAssessmentDebug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClearChannelAssessmentDebug @ 0x160;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Enable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Set @ 0x1004;
    reg {
        name="Status0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status0_Set @ 0x1008;
    reg {
        name="Status1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status1_Set @ 0x100c;
    reg {
        name="Status2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Set @ 0x1010;
    reg {
        name="ReceivedSignalStrengthIndicator_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicator_Set @ 0x1018;
    reg {
        name="FrameReceivedSignalStrengthIndicator_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameReceivedSignalStrengthIndicator_Set @ 0x101c;
    reg {
        name="Control0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control0_Set @ 0x1020;
    reg {
        name="Control1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control1_Set @ 0x1024;
    reg {
        name="Control2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control2_Set @ 0x1028;
    reg {
        name="Control3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control3_Set @ 0x102c;
    reg {
        name="Control4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control4_Set @ 0x1030;
    reg {
        name="Control5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control5_Set @ 0x1034;
    reg {
        name="Control6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control6_Set @ 0x1038;
    reg {
        name="Control7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control7_Set @ 0x103c;
    reg {
        name="ReceivedSignalStrengthIndicatorStepThreshold_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicatorStepThreshold_Set @ 0x1040;
    reg {
        name="ManualGain_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ManualGain_Set @ 0x1044;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x1048;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x104c;
    reg {
        name="Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Set @ 0x1050;
    reg {
        name="RxGainRange_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxGainRange_Set @ 0x1054;
    reg {
        name="AutomaticGainControlPeriod0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlPeriod0_Set @ 0x1058;
    reg {
        name="AutomaticGainControlPeriod1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlPeriod1_Set @ 0x105c;
    reg {
        name="HiCounterRegion0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion0_Set @ 0x1060;
    reg {
        name="HiCounterRegion1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion1_Set @ 0x1064;
    reg {
        name="HiCounterRegion2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion2_Set @ 0x1068;
    reg {
        name="GainStepsLimits0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GainStepsLimits0_Set @ 0x106c;
    reg {
        name="GainStepsLimits1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GainStepsLimits1_Set @ 0x1070;
    reg {
        name="PnRfAttenuationCodeGroup0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup0_Set @ 0x1074;
    reg {
        name="PnRfAttenuationCodeGroup1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup1_Set @ 0x1078;
    reg {
        name="PnRfAttenuationCodeGroup2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup2_Set @ 0x107c;
    reg {
        name="PnRfAttenuationCodeGroup3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup3_Set @ 0x1080;
    reg {
        name="PnRfAttenuationCodeGroup4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup4_Set @ 0x1084;
    reg {
        name="PnRfAttenuationCodeGroup5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup5_Set @ 0x1088;
    reg {
        name="PnRfAttenuationCodeGroup6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup6_Set @ 0x108c;
    reg {
        name="PnRfAttenuationCodeGroup7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup7_Set @ 0x1090;
    reg {
        name="PnRfAttenuationCodeGroupAlternate_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroupAlternate_Set @ 0x10a4;
    reg {
        name="LnaMixSliceCodeGroup0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaMixSliceCodeGroup0_Set @ 0x10a8;
    reg {
        name="LnaMixSliceCodeGroup1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaMixSliceCodeGroup1_Set @ 0x10ac;
    reg {
        name="ProgrammableGainAmplifierGainCodeGroup0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierGainCodeGroup0_Set @ 0x10b0;
    reg {
        name="ProgrammableGainAmplifierGainCodeGroup1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierGainCodeGroup1_Set @ 0x10b4;
    reg {
        name="ListenBeforeTalkConfiguration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkConfiguration_Set @ 0x10b8;
    reg {
        name="MirrorInterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MirrorInterruptFlags_Set @ 0x10bc;
    reg {
        name="SequencerInterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Set @ 0x10c0;
    reg {
        name="SequencerInterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Set @ 0x10c4;
    reg {
        name="ReceivedSignalStrengthIndicatorAbsoluteThreshold_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicatorAbsoluteThreshold_Set @ 0x10c8;
    reg {
        name="LnaBoostControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaBoostControl_Set @ 0x10cc;
    reg {
        name="AntennaDiversity_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversity_Set @ 0x10d0;
    reg {
        name="DualRfpkdThreshold0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DualRfpkdThreshold0_Set @ 0x10d4;
    reg {
        name="DualRfpkdThreshold1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DualRfpkdThreshold1_Set @ 0x10d8;
    reg {
        name="Spare_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Set @ 0x10dc;
    reg {
        name="PnRfFilterCodeGroup0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup0_Set @ 0x10e0;
    reg {
        name="PnRfFilterCodeGroup1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup1_Set @ 0x10e4;
    reg {
        name="PnRfFilterCodeGroup2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup2_Set @ 0x10e8;
    reg {
        name="PnRfFilterCodeGroup3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup3_Set @ 0x10ec;
    reg {
        name="PnRfFilterCodeGroup4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup4_Set @ 0x10f0;
    reg {
        name="PnRfFilterCodeGroup5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup5_Set @ 0x10f4;
    reg {
        name="PnRfFilterCodeGroup6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup6_Set @ 0x10f8;
    reg {
        name="PnRfFilterCodeGroup7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup7_Set @ 0x10fc;
    reg {
        name="FeNotchAttenuationCodeGroup0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup0_Set @ 0x1100;
    reg {
        name="FeNotchAttenuationCodeGroup1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup1_Set @ 0x1104;
    reg {
        name="FeNotchAttenuationCodeGroup2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup2_Set @ 0x1108;
    reg {
        name="FeNotchAttenuationCodeGroup3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup3_Set @ 0x110c;
    reg {
        name="FeNotchAttenuationCodeGroup4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup4_Set @ 0x1110;
    reg {
        name="FeNotchAttenuationCodeGroup5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup5_Set @ 0x1114;
    reg {
        name="FeNotchAttenuationCodeGroup6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup6_Set @ 0x1118;
    reg {
        name="FeNotchAttenuationCodeGroup7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup7_Set @ 0x111c;
    reg {
        name="FeNotchAttenuationCodeGroup8_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup8_Set @ 0x1120;
    reg {
        name="FeNotchAttenuationCodeGroup9_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup9_Set @ 0x1124;
    reg {
        name="FeNotchAttenuationCodeGroup10_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup10_Set @ 0x1128;
    reg {
        name="FeNotchAttenuationCodeGroup11_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup11_Set @ 0x112c;
    reg {
        name="FeNotchFilterCodeGroup0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup0_Set @ 0x1130;
    reg {
        name="FeNotchFilterCodeGroup1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup1_Set @ 0x1134;
    reg {
        name="FeNotchFilterCodeGroup2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup2_Set @ 0x1138;
    reg {
        name="FeNotchFilterCodeGroup3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup3_Set @ 0x113c;
    reg {
        name="FeNotchFilterCodeGroup4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup4_Set @ 0x1140;
    reg {
        name="FeNotchFilterCodeGroup5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup5_Set @ 0x1144;
    reg {
        name="FeNotchFilterCodeGroup6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup6_Set @ 0x1148;
    reg {
        name="FeNotchFilterCodeGroup7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup7_Set @ 0x114c;
    reg {
        name="FeNotchFilterCodeGroup8_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup8_Set @ 0x1150;
    reg {
        name="FeNotchFilterCodeGroup9_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup9_Set @ 0x1154;
    reg {
        name="FeNotchFilterCodeGroup10_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup10_Set @ 0x1158;
    reg {
        name="FeNotchFilterCodeGroup11_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup11_Set @ 0x115c;
    reg {
        name="ClearChannelAssessmentDebug_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClearChannelAssessmentDebug_Set @ 0x1160;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Enable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Clr @ 0x2004;
    reg {
        name="Status0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status0_Clr @ 0x2008;
    reg {
        name="Status1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status1_Clr @ 0x200c;
    reg {
        name="Status2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Clr @ 0x2010;
    reg {
        name="ReceivedSignalStrengthIndicator_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicator_Clr @ 0x2018;
    reg {
        name="FrameReceivedSignalStrengthIndicator_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameReceivedSignalStrengthIndicator_Clr @ 0x201c;
    reg {
        name="Control0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control0_Clr @ 0x2020;
    reg {
        name="Control1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control1_Clr @ 0x2024;
    reg {
        name="Control2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control2_Clr @ 0x2028;
    reg {
        name="Control3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control3_Clr @ 0x202c;
    reg {
        name="Control4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control4_Clr @ 0x2030;
    reg {
        name="Control5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control5_Clr @ 0x2034;
    reg {
        name="Control6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control6_Clr @ 0x2038;
    reg {
        name="Control7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control7_Clr @ 0x203c;
    reg {
        name="ReceivedSignalStrengthIndicatorStepThreshold_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicatorStepThreshold_Clr @ 0x2040;
    reg {
        name="ManualGain_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ManualGain_Clr @ 0x2044;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x2048;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x204c;
    reg {
        name="Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Clr @ 0x2050;
    reg {
        name="RxGainRange_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxGainRange_Clr @ 0x2054;
    reg {
        name="AutomaticGainControlPeriod0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlPeriod0_Clr @ 0x2058;
    reg {
        name="AutomaticGainControlPeriod1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlPeriod1_Clr @ 0x205c;
    reg {
        name="HiCounterRegion0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion0_Clr @ 0x2060;
    reg {
        name="HiCounterRegion1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion1_Clr @ 0x2064;
    reg {
        name="HiCounterRegion2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion2_Clr @ 0x2068;
    reg {
        name="GainStepsLimits0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GainStepsLimits0_Clr @ 0x206c;
    reg {
        name="GainStepsLimits1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GainStepsLimits1_Clr @ 0x2070;
    reg {
        name="PnRfAttenuationCodeGroup0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup0_Clr @ 0x2074;
    reg {
        name="PnRfAttenuationCodeGroup1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup1_Clr @ 0x2078;
    reg {
        name="PnRfAttenuationCodeGroup2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup2_Clr @ 0x207c;
    reg {
        name="PnRfAttenuationCodeGroup3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup3_Clr @ 0x2080;
    reg {
        name="PnRfAttenuationCodeGroup4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup4_Clr @ 0x2084;
    reg {
        name="PnRfAttenuationCodeGroup5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup5_Clr @ 0x2088;
    reg {
        name="PnRfAttenuationCodeGroup6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup6_Clr @ 0x208c;
    reg {
        name="PnRfAttenuationCodeGroup7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup7_Clr @ 0x2090;
    reg {
        name="PnRfAttenuationCodeGroupAlternate_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroupAlternate_Clr @ 0x20a4;
    reg {
        name="LnaMixSliceCodeGroup0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaMixSliceCodeGroup0_Clr @ 0x20a8;
    reg {
        name="LnaMixSliceCodeGroup1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaMixSliceCodeGroup1_Clr @ 0x20ac;
    reg {
        name="ProgrammableGainAmplifierGainCodeGroup0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierGainCodeGroup0_Clr @ 0x20b0;
    reg {
        name="ProgrammableGainAmplifierGainCodeGroup1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierGainCodeGroup1_Clr @ 0x20b4;
    reg {
        name="ListenBeforeTalkConfiguration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkConfiguration_Clr @ 0x20b8;
    reg {
        name="MirrorInterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MirrorInterruptFlags_Clr @ 0x20bc;
    reg {
        name="SequencerInterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Clr @ 0x20c0;
    reg {
        name="SequencerInterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Clr @ 0x20c4;
    reg {
        name="ReceivedSignalStrengthIndicatorAbsoluteThreshold_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicatorAbsoluteThreshold_Clr @ 0x20c8;
    reg {
        name="LnaBoostControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaBoostControl_Clr @ 0x20cc;
    reg {
        name="AntennaDiversity_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversity_Clr @ 0x20d0;
    reg {
        name="DualRfpkdThreshold0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DualRfpkdThreshold0_Clr @ 0x20d4;
    reg {
        name="DualRfpkdThreshold1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DualRfpkdThreshold1_Clr @ 0x20d8;
    reg {
        name="Spare_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Clr @ 0x20dc;
    reg {
        name="PnRfFilterCodeGroup0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup0_Clr @ 0x20e0;
    reg {
        name="PnRfFilterCodeGroup1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup1_Clr @ 0x20e4;
    reg {
        name="PnRfFilterCodeGroup2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup2_Clr @ 0x20e8;
    reg {
        name="PnRfFilterCodeGroup3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup3_Clr @ 0x20ec;
    reg {
        name="PnRfFilterCodeGroup4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup4_Clr @ 0x20f0;
    reg {
        name="PnRfFilterCodeGroup5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup5_Clr @ 0x20f4;
    reg {
        name="PnRfFilterCodeGroup6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup6_Clr @ 0x20f8;
    reg {
        name="PnRfFilterCodeGroup7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup7_Clr @ 0x20fc;
    reg {
        name="FeNotchAttenuationCodeGroup0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup0_Clr @ 0x2100;
    reg {
        name="FeNotchAttenuationCodeGroup1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup1_Clr @ 0x2104;
    reg {
        name="FeNotchAttenuationCodeGroup2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup2_Clr @ 0x2108;
    reg {
        name="FeNotchAttenuationCodeGroup3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup3_Clr @ 0x210c;
    reg {
        name="FeNotchAttenuationCodeGroup4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup4_Clr @ 0x2110;
    reg {
        name="FeNotchAttenuationCodeGroup5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup5_Clr @ 0x2114;
    reg {
        name="FeNotchAttenuationCodeGroup6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup6_Clr @ 0x2118;
    reg {
        name="FeNotchAttenuationCodeGroup7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup7_Clr @ 0x211c;
    reg {
        name="FeNotchAttenuationCodeGroup8_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup8_Clr @ 0x2120;
    reg {
        name="FeNotchAttenuationCodeGroup9_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup9_Clr @ 0x2124;
    reg {
        name="FeNotchAttenuationCodeGroup10_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup10_Clr @ 0x2128;
    reg {
        name="FeNotchAttenuationCodeGroup11_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup11_Clr @ 0x212c;
    reg {
        name="FeNotchFilterCodeGroup0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup0_Clr @ 0x2130;
    reg {
        name="FeNotchFilterCodeGroup1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup1_Clr @ 0x2134;
    reg {
        name="FeNotchFilterCodeGroup2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup2_Clr @ 0x2138;
    reg {
        name="FeNotchFilterCodeGroup3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup3_Clr @ 0x213c;
    reg {
        name="FeNotchFilterCodeGroup4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup4_Clr @ 0x2140;
    reg {
        name="FeNotchFilterCodeGroup5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup5_Clr @ 0x2144;
    reg {
        name="FeNotchFilterCodeGroup6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup6_Clr @ 0x2148;
    reg {
        name="FeNotchFilterCodeGroup7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup7_Clr @ 0x214c;
    reg {
        name="FeNotchFilterCodeGroup8_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup8_Clr @ 0x2150;
    reg {
        name="FeNotchFilterCodeGroup9_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup9_Clr @ 0x2154;
    reg {
        name="FeNotchFilterCodeGroup10_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup10_Clr @ 0x2158;
    reg {
        name="FeNotchFilterCodeGroup11_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup11_Clr @ 0x215c;
    reg {
        name="ClearChannelAssessmentDebug_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClearChannelAssessmentDebug_Clr @ 0x2160;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Enable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Tgl @ 0x3004;
    reg {
        name="Status0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status0_Tgl @ 0x3008;
    reg {
        name="Status1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status1_Tgl @ 0x300c;
    reg {
        name="Status2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Tgl @ 0x3010;
    reg {
        name="ReceivedSignalStrengthIndicator_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicator_Tgl @ 0x3018;
    reg {
        name="FrameReceivedSignalStrengthIndicator_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameReceivedSignalStrengthIndicator_Tgl @ 0x301c;
    reg {
        name="Control0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control0_Tgl @ 0x3020;
    reg {
        name="Control1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control1_Tgl @ 0x3024;
    reg {
        name="Control2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control2_Tgl @ 0x3028;
    reg {
        name="Control3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control3_Tgl @ 0x302c;
    reg {
        name="Control4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control4_Tgl @ 0x3030;
    reg {
        name="Control5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control5_Tgl @ 0x3034;
    reg {
        name="Control6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control6_Tgl @ 0x3038;
    reg {
        name="Control7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control7_Tgl @ 0x303c;
    reg {
        name="ReceivedSignalStrengthIndicatorStepThreshold_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicatorStepThreshold_Tgl @ 0x3040;
    reg {
        name="ManualGain_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ManualGain_Tgl @ 0x3044;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x3048;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x304c;
    reg {
        name="Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Tgl @ 0x3050;
    reg {
        name="RxGainRange_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxGainRange_Tgl @ 0x3054;
    reg {
        name="AutomaticGainControlPeriod0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlPeriod0_Tgl @ 0x3058;
    reg {
        name="AutomaticGainControlPeriod1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlPeriod1_Tgl @ 0x305c;
    reg {
        name="HiCounterRegion0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion0_Tgl @ 0x3060;
    reg {
        name="HiCounterRegion1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion1_Tgl @ 0x3064;
    reg {
        name="HiCounterRegion2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HiCounterRegion2_Tgl @ 0x3068;
    reg {
        name="GainStepsLimits0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GainStepsLimits0_Tgl @ 0x306c;
    reg {
        name="GainStepsLimits1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GainStepsLimits1_Tgl @ 0x3070;
    reg {
        name="PnRfAttenuationCodeGroup0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup0_Tgl @ 0x3074;
    reg {
        name="PnRfAttenuationCodeGroup1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup1_Tgl @ 0x3078;
    reg {
        name="PnRfAttenuationCodeGroup2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup2_Tgl @ 0x307c;
    reg {
        name="PnRfAttenuationCodeGroup3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup3_Tgl @ 0x3080;
    reg {
        name="PnRfAttenuationCodeGroup4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup4_Tgl @ 0x3084;
    reg {
        name="PnRfAttenuationCodeGroup5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup5_Tgl @ 0x3088;
    reg {
        name="PnRfAttenuationCodeGroup6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup6_Tgl @ 0x308c;
    reg {
        name="PnRfAttenuationCodeGroup7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroup7_Tgl @ 0x3090;
    reg {
        name="PnRfAttenuationCodeGroupAlternate_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfAttenuationCodeGroupAlternate_Tgl @ 0x30a4;
    reg {
        name="LnaMixSliceCodeGroup0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaMixSliceCodeGroup0_Tgl @ 0x30a8;
    reg {
        name="LnaMixSliceCodeGroup1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaMixSliceCodeGroup1_Tgl @ 0x30ac;
    reg {
        name="ProgrammableGainAmplifierGainCodeGroup0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierGainCodeGroup0_Tgl @ 0x30b0;
    reg {
        name="ProgrammableGainAmplifierGainCodeGroup1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierGainCodeGroup1_Tgl @ 0x30b4;
    reg {
        name="ListenBeforeTalkConfiguration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkConfiguration_Tgl @ 0x30b8;
    reg {
        name="MirrorInterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MirrorInterruptFlags_Tgl @ 0x30bc;
    reg {
        name="SequencerInterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Tgl @ 0x30c0;
    reg {
        name="SequencerInterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Tgl @ 0x30c4;
    reg {
        name="ReceivedSignalStrengthIndicatorAbsoluteThreshold_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReceivedSignalStrengthIndicatorAbsoluteThreshold_Tgl @ 0x30c8;
    reg {
        name="LnaBoostControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LnaBoostControl_Tgl @ 0x30cc;
    reg {
        name="AntennaDiversity_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversity_Tgl @ 0x30d0;
    reg {
        name="DualRfpkdThreshold0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DualRfpkdThreshold0_Tgl @ 0x30d4;
    reg {
        name="DualRfpkdThreshold1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DualRfpkdThreshold1_Tgl @ 0x30d8;
    reg {
        name="Spare_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Tgl @ 0x30dc;
    reg {
        name="PnRfFilterCodeGroup0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup0_Tgl @ 0x30e0;
    reg {
        name="PnRfFilterCodeGroup1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup1_Tgl @ 0x30e4;
    reg {
        name="PnRfFilterCodeGroup2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup2_Tgl @ 0x30e8;
    reg {
        name="PnRfFilterCodeGroup3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup3_Tgl @ 0x30ec;
    reg {
        name="PnRfFilterCodeGroup4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup4_Tgl @ 0x30f0;
    reg {
        name="PnRfFilterCodeGroup5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup5_Tgl @ 0x30f4;
    reg {
        name="PnRfFilterCodeGroup6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup6_Tgl @ 0x30f8;
    reg {
        name="PnRfFilterCodeGroup7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PnRfFilterCodeGroup7_Tgl @ 0x30fc;
    reg {
        name="FeNotchAttenuationCodeGroup0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup0_Tgl @ 0x3100;
    reg {
        name="FeNotchAttenuationCodeGroup1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup1_Tgl @ 0x3104;
    reg {
        name="FeNotchAttenuationCodeGroup2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup2_Tgl @ 0x3108;
    reg {
        name="FeNotchAttenuationCodeGroup3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup3_Tgl @ 0x310c;
    reg {
        name="FeNotchAttenuationCodeGroup4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup4_Tgl @ 0x3110;
    reg {
        name="FeNotchAttenuationCodeGroup5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup5_Tgl @ 0x3114;
    reg {
        name="FeNotchAttenuationCodeGroup6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup6_Tgl @ 0x3118;
    reg {
        name="FeNotchAttenuationCodeGroup7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup7_Tgl @ 0x311c;
    reg {
        name="FeNotchAttenuationCodeGroup8_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup8_Tgl @ 0x3120;
    reg {
        name="FeNotchAttenuationCodeGroup9_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup9_Tgl @ 0x3124;
    reg {
        name="FeNotchAttenuationCodeGroup10_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup10_Tgl @ 0x3128;
    reg {
        name="FeNotchAttenuationCodeGroup11_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchAttenuationCodeGroup11_Tgl @ 0x312c;
    reg {
        name="FeNotchFilterCodeGroup0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup0_Tgl @ 0x3130;
    reg {
        name="FeNotchFilterCodeGroup1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup1_Tgl @ 0x3134;
    reg {
        name="FeNotchFilterCodeGroup2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup2_Tgl @ 0x3138;
    reg {
        name="FeNotchFilterCodeGroup3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup3_Tgl @ 0x313c;
    reg {
        name="FeNotchFilterCodeGroup4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup4_Tgl @ 0x3140;
    reg {
        name="FeNotchFilterCodeGroup5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup5_Tgl @ 0x3144;
    reg {
        name="FeNotchFilterCodeGroup6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup6_Tgl @ 0x3148;
    reg {
        name="FeNotchFilterCodeGroup7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup7_Tgl @ 0x314c;
    reg {
        name="FeNotchFilterCodeGroup8_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup8_Tgl @ 0x3150;
    reg {
        name="FeNotchFilterCodeGroup9_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup9_Tgl @ 0x3154;
    reg {
        name="FeNotchFilterCodeGroup10_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup10_Tgl @ 0x3158;
    reg {
        name="FeNotchFilterCodeGroup11_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotchFilterCodeGroup11_Tgl @ 0x315c;
    reg {
        name="ClearChannelAssessmentDebug_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClearChannelAssessmentDebug_Tgl @ 0x3160;
} AutomaticGainControlRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion @ 0x0;
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x4;
    reg {
        name="Control";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INPUTINV[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } OUTPUTINV[1:1];
            field {
                sw = rw;
            } CRCWIDTH[3:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INPUTBITORDER[5:5];
            field {
                sw = rw;
            } BYTEREVERSE[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BITREVERSE[7:7];
            field {
                sw = rw;
            } BITSPERWORD[11:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PADCRCINPUT[12:12];
    } Control @ 0x8;
    reg {
        name="Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status @ 0xc;
    reg {
        name="Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command @ 0x10;
    reg {
        name="InputData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InputData @ 0x14;
    reg {
        name="InitializationValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitializationValue @ 0x18;
    reg {
        name="Data";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data @ 0x1c;
    reg {
        name="PolynomialValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PolynomialValue @ 0x20;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Enable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Set @ 0x1004;
    reg {
        name="Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Set @ 0x1008;
    reg {
        name="Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Set @ 0x100c;
    reg {
        name="Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Set @ 0x1010;
    reg {
        name="InputData_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InputData_Set @ 0x1014;
    reg {
        name="InitializationValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitializationValue_Set @ 0x1018;
    reg {
        name="Data_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data_Set @ 0x101c;
    reg {
        name="PolynomialValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PolynomialValue_Set @ 0x1020;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Enable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Clr @ 0x2004;
    reg {
        name="Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Clr @ 0x2008;
    reg {
        name="Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Clr @ 0x200c;
    reg {
        name="Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Clr @ 0x2010;
    reg {
        name="InputData_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InputData_Clr @ 0x2014;
    reg {
        name="InitializationValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitializationValue_Clr @ 0x2018;
    reg {
        name="Data_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data_Clr @ 0x201c;
    reg {
        name="PolynomialValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PolynomialValue_Clr @ 0x2020;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Enable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Tgl @ 0x3004;
    reg {
        name="Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Tgl @ 0x3008;
    reg {
        name="Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Tgl @ 0x300c;
    reg {
        name="Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Tgl @ 0x3010;
    reg {
        name="InputData_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InputData_Tgl @ 0x3014;
    reg {
        name="InitializationValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InitializationValue_Tgl @ 0x3018;
    reg {
        name="Data_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Data_Tgl @ 0x301c;
    reg {
        name="PolynomialValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PolynomialValue_Tgl @ 0x3020;
} CyclicRedundancyCheckRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion @ 0x0;
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x4;
    reg {
        name="Control";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEBUGRUN[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMACLRACT[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } OSMEN[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ZEROSTARTEN[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } PRECNTSRC[9:8];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } BASECNTSRC[13:12];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } WRAPCNTSRC[17:16];
            field {
                sw = rw;
            } TOUT0SRC[21:20];
            field {
                sw = rw;
            } TOUT0SYNCSRC[23:22];
            field {
                sw = rw;
            } TOUT1SRC[25:24];
            field {
                sw = rw;
            } TOUT1SYNCSRC[27:26];
            field {
                sw = rw;
            } TOUT0MODE[28:28];
            field {
                sw = rw;
            } TOUT1MODE[29:29];
    } Control @ 0x8;
    reg {
        name="Command";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } START[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RTCSYNCSTART[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } STOP[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } TOUT0START[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } TOUT0STOP[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } TOUT1START[6:6];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } TOUT1STOP[7:7];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } FORCETXIDLE[8:8];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } FORCERXIDLE[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FORCERXRX[10:10];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } LBTSTART[16:16];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } LBTPAUSE[17:17];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } LBTSTOP[18:18];
    } Command @ 0xc;
    reg {
        name="PrescalerChannelSelection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PrescalerChannelSelection @ 0x10;
    reg {
        name="Status";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RUNNING[0:0];
            field {
                sw = r;
            } LBTSYNC[1:1];
            field {
                sw = r;
            } LBTRUNNING[2:2];
            field {
                sw = r;
            } LBTPAUSED[3:3];
            field {
                sw = r;
            } TOUT0RUNNING[4:4];
            field {
                sw = r;
            } TOUT0SYNC[5:5];
            field {
                sw = r;
            } TOUT1RUNNING[6:6];
            field {
                sw = r;
            } TOUT1SYNC[7:7];
            field {
                sw = r;
            } ICV0[8:8];
            field {
                sw = r;
            } ICV1[9:9];
            field {
                sw = r;
            } ICV2[10:10];
            field {
                sw = r;
            } ICV3[11:11];
            field {
                sw = r;
            } ICV4[12:12];
            field {
                sw = r;
            } ICV5[13:13];
            field {
                sw = r;
            } ICV6[14:14];
            field {
                sw = r;
            } ICV7[15:15];
    } Status @ 0x14;
    reg {
        name="PreCounterValue";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } PRECNT[15:0];
    } PreCounterValue @ 0x18;
    reg {
        name="BaseCounterValue";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } BASECNT[15:0];
    } BaseCounterValue @ 0x1c;
    reg {
        name="WrapCounterValue";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } WRAPCNT[31:0];
    } WrapCounterValue @ 0x20;
    reg {
        name="BaseAndPreCounterValues";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } PRECNTV[15:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } BASECNTV[31:16];
    } BaseAndPreCounterValues @ 0x24;
    reg {
        name="LatchedWrapCounterValue";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LWRAPCNT[31:0];
    } LatchedWrapCounterValue @ 0x28;
    reg {
        name="PreCounterTopAdjustValue";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRECNTTOPADJ[15:0];
    } PreCounterTopAdjustValue @ 0x2c;
    reg {
        name="PreCounterTopValue";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
            } PRECNTTOPFRAC[7:0];
            field {
                sw = rw;
                reset=16'b1111111111111111;
            } PRECNTTOP[23:8];
    } PreCounterTopValue @ 0x30;
    reg {
        name="BaseCounterTopValue";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
                reset=16'b1111111111111111;
            } BASECNTTOP[15:0];
    } BaseCounterTopValue @ 0x34;
    reg {
        name="WrapCounterTopValue";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
                reset=32'b11111111111111111111111111111111;
            } WRAPCNTTOP[31:0];
    } WrapCounterTopValue @ 0x38;
    reg {
        name="Timeout0Counter";
        regwidth=0x20;
            field {
                sw = rw;
            } TOUT0PCNT[15:0];
            field {
                sw = rw;
            } TOUT0CNT[31:16];
    } Timeout0Counter @ 0x3c;
    reg {
        name="Timeout0CounterTop";
        regwidth=0x20;
            field {
                sw = rw;
                reset=16'b11111111;
            } TOUT0CNTTOP[15:0];
            field {
                sw = rw;
                reset=16'b11111111;
            } TOUT0PCNTTOP[31:16];
    } Timeout0CounterTop @ 0x40;
    reg {
        name="Timeout0Compare";
        regwidth=0x20;
            field {
                sw = rw;
            } TOUT0PCNTCOMP[15:0];
            field {
                sw = rw;
            } TOUT0CNTCOMP[31:16];
    } Timeout0Compare @ 0x44;
    reg {
        name="Timeout1Counter";
        regwidth=0x20;
            field {
                sw = rw;
            } TOUT1PCNT[15:0];
            field {
                sw = rw;
            } TOUT1CNT[31:16];
    } Timeout1Counter @ 0x48;
    reg {
        name="Timeout1CounterTop";
        regwidth=0x20;
            field {
                sw = rw;
                reset=16'b11111111;
            } TOUT1CNTTOP[15:0];
            field {
                sw = rw;
                reset=16'b11111111;
            } TOUT1PCNTTOP[31:16];
    } Timeout1CounterTop @ 0x4c;
    reg {
        name="Timeout1Compare";
        regwidth=0x20;
            field {
                sw = rw;
            } TOUT1PCNTCOMP[15:0];
            field {
                sw = rw;
            } TOUT1CNTCOMP[31:16];
    } Timeout1Compare @ 0x50;
    reg {
        name="ListenBeforeTalkWaitControl";
        regwidth=0x20;
            field {
                sw = rw;
            } STARTEXP[3:0];
            field {
                sw = rw;
            } MAXEXP[7:4];
            field {
                sw = rw;
            } CCADELAY[12:8];
            field {
                sw = rw;
            } CCAREPEAT[19:16];
            field {
                sw = rw;
            } FIXEDBACKOFF[20:20];
            field {
                sw = rw;
            } RETRYLIMIT[27:24];
    } ListenBeforeTalkWaitControl @ 0x54;
    reg {
        name="ListenBeforeTalkPrescalerChannelSelection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkPrescalerChannelSelection @ 0x58;
    reg {
        name="ListenBeforeTalkState";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TOUT0PCNT[15:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TOUT0CNT[31:16];
    } ListenBeforeTalkState @ 0x5c;
    reg {
        name="PseudoRandomGeneratorValue";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } RANDOM[15:0];
    } PseudoRandomGeneratorValue @ 0x60;
    reg {
        name="InterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } PRECNTOFIF[0:0];
            field {
                sw = rw;
            } BASECNTOFIF[1:1];
            field {
                sw = rw;
            } WRAPCNTOFIF[2:2];
            field {
                sw = rw;
            } TOUT0IF[4:4];
            field {
                sw = rw;
            } TOUT1IF[5:5];
            field {
                sw = rw;
            } TOUT0MATCHIF[6:6];
            field {
                sw = rw;
            } TOUT1MATCHIF[7:7];
            field {
                sw = rw;
            } CC0IF[8:8];
            field {
                sw = rw;
            } CC1IF[9:9];
            field {
                sw = rw;
            } CC2IF[10:10];
            field {
                sw = rw;
            } CC3IF[11:11];
            field {
                sw = rw;
            } CC4IF[12:12];
            field {
                sw = rw;
            } CC5IF[13:13];
            field {
                sw = rw;
            } CC6IF[14:14];
            field {
                sw = rw;
            } CC7IF[15:15];
            field {
                sw = rw;
            } COF0IF[16:16];
            field {
                sw = rw;
            } COF1IF[17:17];
            field {
                sw = rw;
            } COF2IF[18:18];
            field {
                sw = rw;
            } COF3IF[19:19];
            field {
                sw = rw;
            } COF4IF[20:20];
            field {
                sw = rw;
            } COF5IF[21:21];
            field {
                sw = rw;
            } COF6IF[22:22];
            field {
                sw = rw;
            } COF7IF[23:23];
            field {
                sw = rw;
            } LBTSUCCESSIF[24:24];
            field {
                sw = rw;
            } LBTFAILUREIF[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LBTPAUSEDIF[26:26];
            field {
                sw = rw;
            } LBTRETRYIF[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RTCCSYNCHEDIF[28:28];
            field {
                sw = rw;
            } TOUT0MATCHLBTIF[29:29];
    } InterruptFlags @ 0x64;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } PRECNTOFIEN[0:0];
            field {
                sw = rw;
            } BASECNTOFIEN[1:1];
            field {
                sw = rw;
            } WRAPCNTOFIEN[2:2];
            field {
                sw = rw;
            } TOUT0IEN[4:4];
            field {
                sw = rw;
            } TOUT1IEN[5:5];
            field {
                sw = rw;
            } TOUT0MATCHIEN[6:6];
            field {
                sw = rw;
            } TOUT1MATCHIEN[7:7];
            field {
                sw = rw;
            } CC0IEN[8:8];
            field {
                sw = rw;
            } CC1IEN[9:9];
            field {
                sw = rw;
            } CC2IEN[10:10];
            field {
                sw = rw;
            } CC3IEN[11:11];
            field {
                sw = rw;
            } CC4IEN[12:12];
            field {
                sw = rw;
            } CC5IEN[13:13];
            field {
                sw = rw;
            } CC6IEN[14:14];
            field {
                sw = rw;
            } CC7IEN[15:15];
            field {
                sw = rw;
            } COF0IEN[16:16];
            field {
                sw = rw;
            } COF1IEN[17:17];
            field {
                sw = rw;
            } COF2IEN[18:18];
            field {
                sw = rw;
            } COF3IEN[19:19];
            field {
                sw = rw;
            } COF4IEN[20:20];
            field {
                sw = rw;
            } COF5IEN[21:21];
            field {
                sw = rw;
            } COF6IEN[22:22];
            field {
                sw = rw;
            } COF7IEN[23:23];
            field {
                sw = rw;
            } LBTSUCCESSIEN[24:24];
            field {
                sw = rw;
            } LBTFAILUREIEN[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LBTPAUSEDIEN[26:26];
            field {
                sw = rw;
            } LBTRETRYIEN[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RTCCSYNCHEDIEN[28:28];
            field {
                sw = rw;
            } TOUT0MATCHLBTIEN[29:29];
    } InterruptEnable @ 0x70;
    reg {
        name="RxControl";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } RXSETEVENT1[4:0];
            field {
                sw = rw;
            } RXSETEVENT2[12:8];
            field {
                sw = rw;
            } RXCLREVENT1[20:16];
            field {
                sw = rw;
            } RXCLREVENT2[28:24];
    } RxControl @ 0x74;
    reg {
        name="TxControl";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } TXSETEVENT1[4:0];
            field {
                sw = rw;
            } TXSETEVENT2[12:8];
    } TxControl @ 0x78;
    reg {
        name="ListenBeforeTalkETSIStandardSupport";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkETSIStandardSupport @ 0x7c;
    reg {
        name="ListenBeforeTalkState1";
        regwidth=0x20;
            field {
                sw = rw;
            } CCACNT[3:0];
            field {
                sw = rw;
            } EXP[7:4];
            field {
                sw = rw;
            } RETRYCNT[11:8];
    } ListenBeforeTalkState1 @ 0x80;
    reg {
        name="LinearRandomValueGeneratedByFirmware0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware0 @ 0x84;
    reg {
        name="LinearRandomValueGeneratedByFirmware1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware1 @ 0x88;
    reg {
        name="LinearRandomValueGeneratedByFirmware2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware2 @ 0x8c;
    reg {
        name="SequencerInterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } PRECNTOFSEQIF[0:0];
            field {
                sw = rw;
            } BASECNTOFSEQIF[1:1];
            field {
                sw = rw;
            } WRAPCNTOFSEQIF[2:2];
            field {
                sw = rw;
            } TOUT0SEQIF[4:4];
            field {
                sw = rw;
            } TOUT1SEQIF[5:5];
            field {
                sw = rw;
            } TOUT0MATCHSEQIF[6:6];
            field {
                sw = rw;
            } TOUT1MATCHSEQIF[7:7];
            field {
                sw = rw;
            } CC0SEQIF[8:8];
            field {
                sw = rw;
            } CC1SEQIF[9:9];
            field {
                sw = rw;
            } CC2SEQIF[10:10];
            field {
                sw = rw;
            } CC3SEQIF[11:11];
            field {
                sw = rw;
            } CC4SEQIF[12:12];
            field {
                sw = rw;
            } CC5SEQIF[13:13];
            field {
                sw = rw;
            } CC6SEQIF[14:14];
            field {
                sw = rw;
            } CC7SEQIF[15:15];
            field {
                sw = rw;
            } COF0SEQIF[16:16];
            field {
                sw = rw;
            } COF1SEQIF[17:17];
            field {
                sw = rw;
            } COF2SEQIF[18:18];
            field {
                sw = rw;
            } COF3SEQIF[19:19];
            field {
                sw = rw;
            } COF4SEQIF[20:20];
            field {
                sw = rw;
            } COF5SEQIF[21:21];
            field {
                sw = rw;
            } COF6SEQIF[22:22];
            field {
                sw = rw;
            } COF7SEQIF[23:23];
            field {
                sw = rw;
            } LBTSUCCESSSEQIF[24:24];
            field {
                sw = rw;
            } LBTFAILURESEQIF[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LBTPAUSEDIF[26:26];
            field {
                sw = rw;
            } LBTRETRYSEQIF[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RTCCSYNCHEDSEQIF[28:28];
            field {
                sw = rw;
            } TOUT0MATCHLBTSEQIF[29:29];
    } SequencerInterruptFlags @ 0x90;
    reg {
        name="SequencerInterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } PRECNTOFSEQIEN[0:0];
            field {
                sw = rw;
            } BASECNTOFSEQIEN[1:1];
            field {
                sw = rw;
            } WRAPCNTOFSEQIEN[2:2];
            field {
                sw = rw;
            } TOUT0SEQIEN[4:4];
            field {
                sw = rw;
            } TOUT1SEQIEN[5:5];
            field {
                sw = rw;
            } TOUT0MATCHSEQIEN[6:6];
            field {
                sw = rw;
            } TOUT1MATCHSEQIEN[7:7];
            field {
                sw = rw;
            } CC0SEQIEN[8:8];
            field {
                sw = rw;
            } CC1SEQIEN[9:9];
            field {
                sw = rw;
            } CC2SEQIEN[10:10];
            field {
                sw = rw;
            } CC3SEQIEN[11:11];
            field {
                sw = rw;
            } CC4SEQIEN[12:12];
            field {
                sw = rw;
            } CC5SEQIEN[13:13];
            field {
                sw = rw;
            } CC6SEQIEN[14:14];
            field {
                sw = rw;
            } CC7SEQIEN[15:15];
            field {
                sw = rw;
            } COF0SEQIEN[16:16];
            field {
                sw = rw;
            } COF1SEQIEN[17:17];
            field {
                sw = rw;
            } COF2SEQIEN[18:18];
            field {
                sw = rw;
            } COF3SEQIEN[19:19];
            field {
                sw = rw;
            } COF4SEQIEN[20:20];
            field {
                sw = rw;
            } COF5SEQIEN[21:21];
            field {
                sw = rw;
            } COF6SEQIEN[22:22];
            field {
                sw = rw;
            } COF7SEQIEN[23:23];
            field {
                sw = rw;
            } LBTSUCCESSSEQIEN[24:24];
            field {
                sw = rw;
            } LBTFAILURESEQIEN[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LBTPAUSEDIEN[26:26];
            field {
                sw = rw;
            } LBTRETRYSEQIEN[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RTCCSYNCHEDSEQIEN[28:28];
            field {
                sw = rw;
            } TOUT0MATCHLBTSEQIEN[29:29];
    } SequencerInterruptEnable @ 0x94;
    reg {
        name="CaptureCompareChannel0Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0Control @ 0x100;
    reg {
        name="CaptureCompareChannel0PreValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0PreValue @ 0x104;
    reg {
        name="CaptureCompareChannel0BaseValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0BaseValue @ 0x108;
    reg {
        name="CaptureCompareChannel0WrapValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0WrapValue @ 0x10c;
    reg {
        name="CaptureCompareChannel1Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1Control @ 0x110;
    reg {
        name="CaptureCompareChannel1PreValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1PreValue @ 0x114;
    reg {
        name="CaptureCompareChannel1BaseValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1BaseValue @ 0x118;
    reg {
        name="CaptureCompareChannel1WrapValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1WrapValue @ 0x11c;
    reg {
        name="CaptureCompareChannel2Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2Control @ 0x120;
    reg {
        name="CaptureCompareChannel2PreValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2PreValue @ 0x124;
    reg {
        name="CaptureCompareChannel2BaseValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2BaseValue @ 0x128;
    reg {
        name="CaptureCompareChannel2WrapValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2WrapValue @ 0x12c;
    reg {
        name="CaptureCompareChannel3Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3Control @ 0x130;
    reg {
        name="CaptureCompareChannel3PreValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3PreValue @ 0x134;
    reg {
        name="CaptureCompareChannel3BaseValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3BaseValue @ 0x138;
    reg {
        name="CaptureCompareChannel3WrapValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3WrapValue @ 0x13c;
    reg {
        name="CaptureCompareChannel4Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4Control @ 0x140;
    reg {
        name="CaptureCompareChannel4PreValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4PreValue @ 0x144;
    reg {
        name="CaptureCompareChannel4BaseValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4BaseValue @ 0x148;
    reg {
        name="CaptureCompareChannel4WrapValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4WrapValue @ 0x14c;
    reg {
        name="CaptureCompareChannel5Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5Control @ 0x150;
    reg {
        name="CaptureCompareChannel5PreValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5PreValue @ 0x154;
    reg {
        name="CaptureCompareChannel5BaseValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5BaseValue @ 0x158;
    reg {
        name="CaptureCompareChannel5WrapValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5WrapValue @ 0x15c;
    reg {
        name="CaptureCompareChannel6Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6Control @ 0x160;
    reg {
        name="CaptureCompareChannel6PreValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6PreValue @ 0x164;
    reg {
        name="CaptureCompareChannel6BaseValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6BaseValue @ 0x168;
    reg {
        name="CaptureCompareChannel6WrapValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6WrapValue @ 0x16c;
    reg {
        name="CaptureCompareChannel7Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7Control @ 0x170;
    reg {
        name="CaptureCompareChannel7PreValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7PreValue @ 0x174;
    reg {
        name="CaptureCompareChannel7BaseValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7BaseValue @ 0x178;
    reg {
        name="CaptureCompareChannel7WrapValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7WrapValue @ 0x17c;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Enable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Set @ 0x1004;
    reg {
        name="Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Set @ 0x1008;
    reg {
        name="Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Set @ 0x100c;
    reg {
        name="PrescalerChannelSelection_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PrescalerChannelSelection_Set @ 0x1010;
    reg {
        name="Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Set @ 0x1014;
    reg {
        name="PreCounterValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterValue_Set @ 0x1018;
    reg {
        name="BaseCounterValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseCounterValue_Set @ 0x101c;
    reg {
        name="WrapCounterValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WrapCounterValue_Set @ 0x1020;
    reg {
        name="BaseAndPreCounterValues_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseAndPreCounterValues_Set @ 0x1024;
    reg {
        name="LatchedWrapCounterValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LatchedWrapCounterValue_Set @ 0x1028;
    reg {
        name="PreCounterTopAdjustValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterTopAdjustValue_Set @ 0x102c;
    reg {
        name="PreCounterTopValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterTopValue_Set @ 0x1030;
    reg {
        name="BaseCounterTopValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseCounterTopValue_Set @ 0x1034;
    reg {
        name="WrapCounterTopValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WrapCounterTopValue_Set @ 0x1038;
    reg {
        name="Timeout0Counter_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0Counter_Set @ 0x103c;
    reg {
        name="Timeout0CounterTop_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0CounterTop_Set @ 0x1040;
    reg {
        name="Timeout0Compare_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0Compare_Set @ 0x1044;
    reg {
        name="Timeout1Counter_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1Counter_Set @ 0x1048;
    reg {
        name="Timeout1CounterTop_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1CounterTop_Set @ 0x104c;
    reg {
        name="Timeout1Compare_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1Compare_Set @ 0x1050;
    reg {
        name="ListenBeforeTalkWaitControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkWaitControl_Set @ 0x1054;
    reg {
        name="ListenBeforeTalkPrescalerChannelSelection_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkPrescalerChannelSelection_Set @ 0x1058;
    reg {
        name="ListenBeforeTalkState_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkState_Set @ 0x105c;
    reg {
        name="PseudoRandomGeneratorValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PseudoRandomGeneratorValue_Set @ 0x1060;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x1064;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x1070;
    reg {
        name="RxControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxControl_Set @ 0x1074;
    reg {
        name="TxControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxControl_Set @ 0x1078;
    reg {
        name="ListenBeforeTalkETSIStandardSupport_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkETSIStandardSupport_Set @ 0x107c;
    reg {
        name="ListenBeforeTalkState1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkState1_Set @ 0x1080;
    reg {
        name="LinearRandomValueGeneratedByFirmware0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware0_Set @ 0x1084;
    reg {
        name="LinearRandomValueGeneratedByFirmware1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware1_Set @ 0x1088;
    reg {
        name="LinearRandomValueGeneratedByFirmware2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware2_Set @ 0x108c;
    reg {
        name="SequencerInterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Set @ 0x1090;
    reg {
        name="SequencerInterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Set @ 0x1094;
    reg {
        name="CaptureCompareChannel0Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0Control_Set @ 0x1100;
    reg {
        name="CaptureCompareChannel0PreValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0PreValue_Set @ 0x1104;
    reg {
        name="CaptureCompareChannel0BaseValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0BaseValue_Set @ 0x1108;
    reg {
        name="CaptureCompareChannel0WrapValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0WrapValue_Set @ 0x110c;
    reg {
        name="CaptureCompareChannel1Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1Control_Set @ 0x1110;
    reg {
        name="CaptureCompareChannel1PreValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1PreValue_Set @ 0x1114;
    reg {
        name="CaptureCompareChannel1BaseValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1BaseValue_Set @ 0x1118;
    reg {
        name="CaptureCompareChannel1WrapValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1WrapValue_Set @ 0x111c;
    reg {
        name="CaptureCompareChannel2Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2Control_Set @ 0x1120;
    reg {
        name="CaptureCompareChannel2PreValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2PreValue_Set @ 0x1124;
    reg {
        name="CaptureCompareChannel2BaseValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2BaseValue_Set @ 0x1128;
    reg {
        name="CaptureCompareChannel2WrapValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2WrapValue_Set @ 0x112c;
    reg {
        name="CaptureCompareChannel3Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3Control_Set @ 0x1130;
    reg {
        name="CaptureCompareChannel3PreValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3PreValue_Set @ 0x1134;
    reg {
        name="CaptureCompareChannel3BaseValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3BaseValue_Set @ 0x1138;
    reg {
        name="CaptureCompareChannel3WrapValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3WrapValue_Set @ 0x113c;
    reg {
        name="CaptureCompareChannel4Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4Control_Set @ 0x1140;
    reg {
        name="CaptureCompareChannel4PreValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4PreValue_Set @ 0x1144;
    reg {
        name="CaptureCompareChannel4BaseValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4BaseValue_Set @ 0x1148;
    reg {
        name="CaptureCompareChannel4WrapValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4WrapValue_Set @ 0x114c;
    reg {
        name="CaptureCompareChannel5Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5Control_Set @ 0x1150;
    reg {
        name="CaptureCompareChannel5PreValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5PreValue_Set @ 0x1154;
    reg {
        name="CaptureCompareChannel5BaseValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5BaseValue_Set @ 0x1158;
    reg {
        name="CaptureCompareChannel5WrapValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5WrapValue_Set @ 0x115c;
    reg {
        name="CaptureCompareChannel6Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6Control_Set @ 0x1160;
    reg {
        name="CaptureCompareChannel6PreValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6PreValue_Set @ 0x1164;
    reg {
        name="CaptureCompareChannel6BaseValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6BaseValue_Set @ 0x1168;
    reg {
        name="CaptureCompareChannel6WrapValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6WrapValue_Set @ 0x116c;
    reg {
        name="CaptureCompareChannel7Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7Control_Set @ 0x1170;
    reg {
        name="CaptureCompareChannel7PreValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7PreValue_Set @ 0x1174;
    reg {
        name="CaptureCompareChannel7BaseValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7BaseValue_Set @ 0x1178;
    reg {
        name="CaptureCompareChannel7WrapValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7WrapValue_Set @ 0x117c;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Enable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Clr @ 0x2004;
    reg {
        name="Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Clr @ 0x2008;
    reg {
        name="Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Clr @ 0x200c;
    reg {
        name="PrescalerChannelSelection_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PrescalerChannelSelection_Clr @ 0x2010;
    reg {
        name="Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Clr @ 0x2014;
    reg {
        name="PreCounterValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterValue_Clr @ 0x2018;
    reg {
        name="BaseCounterValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseCounterValue_Clr @ 0x201c;
    reg {
        name="WrapCounterValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WrapCounterValue_Clr @ 0x2020;
    reg {
        name="BaseAndPreCounterValues_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseAndPreCounterValues_Clr @ 0x2024;
    reg {
        name="LatchedWrapCounterValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LatchedWrapCounterValue_Clr @ 0x2028;
    reg {
        name="PreCounterTopAdjustValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterTopAdjustValue_Clr @ 0x202c;
    reg {
        name="PreCounterTopValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterTopValue_Clr @ 0x2030;
    reg {
        name="BaseCounterTopValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseCounterTopValue_Clr @ 0x2034;
    reg {
        name="WrapCounterTopValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WrapCounterTopValue_Clr @ 0x2038;
    reg {
        name="Timeout0Counter_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0Counter_Clr @ 0x203c;
    reg {
        name="Timeout0CounterTop_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0CounterTop_Clr @ 0x2040;
    reg {
        name="Timeout0Compare_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0Compare_Clr @ 0x2044;
    reg {
        name="Timeout1Counter_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1Counter_Clr @ 0x2048;
    reg {
        name="Timeout1CounterTop_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1CounterTop_Clr @ 0x204c;
    reg {
        name="Timeout1Compare_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1Compare_Clr @ 0x2050;
    reg {
        name="ListenBeforeTalkWaitControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkWaitControl_Clr @ 0x2054;
    reg {
        name="ListenBeforeTalkPrescalerChannelSelection_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkPrescalerChannelSelection_Clr @ 0x2058;
    reg {
        name="ListenBeforeTalkState_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkState_Clr @ 0x205c;
    reg {
        name="PseudoRandomGeneratorValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PseudoRandomGeneratorValue_Clr @ 0x2060;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x2064;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x2070;
    reg {
        name="RxControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxControl_Clr @ 0x2074;
    reg {
        name="TxControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxControl_Clr @ 0x2078;
    reg {
        name="ListenBeforeTalkETSIStandardSupport_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkETSIStandardSupport_Clr @ 0x207c;
    reg {
        name="ListenBeforeTalkState1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkState1_Clr @ 0x2080;
    reg {
        name="LinearRandomValueGeneratedByFirmware0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware0_Clr @ 0x2084;
    reg {
        name="LinearRandomValueGeneratedByFirmware1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware1_Clr @ 0x2088;
    reg {
        name="LinearRandomValueGeneratedByFirmware2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware2_Clr @ 0x208c;
    reg {
        name="SequencerInterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Clr @ 0x2090;
    reg {
        name="SequencerInterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Clr @ 0x2094;
    reg {
        name="CaptureCompareChannel0Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0Control_Clr @ 0x2100;
    reg {
        name="CaptureCompareChannel0PreValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0PreValue_Clr @ 0x2104;
    reg {
        name="CaptureCompareChannel0BaseValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0BaseValue_Clr @ 0x2108;
    reg {
        name="CaptureCompareChannel0WrapValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0WrapValue_Clr @ 0x210c;
    reg {
        name="CaptureCompareChannel1Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1Control_Clr @ 0x2110;
    reg {
        name="CaptureCompareChannel1PreValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1PreValue_Clr @ 0x2114;
    reg {
        name="CaptureCompareChannel1BaseValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1BaseValue_Clr @ 0x2118;
    reg {
        name="CaptureCompareChannel1WrapValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1WrapValue_Clr @ 0x211c;
    reg {
        name="CaptureCompareChannel2Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2Control_Clr @ 0x2120;
    reg {
        name="CaptureCompareChannel2PreValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2PreValue_Clr @ 0x2124;
    reg {
        name="CaptureCompareChannel2BaseValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2BaseValue_Clr @ 0x2128;
    reg {
        name="CaptureCompareChannel2WrapValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2WrapValue_Clr @ 0x212c;
    reg {
        name="CaptureCompareChannel3Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3Control_Clr @ 0x2130;
    reg {
        name="CaptureCompareChannel3PreValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3PreValue_Clr @ 0x2134;
    reg {
        name="CaptureCompareChannel3BaseValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3BaseValue_Clr @ 0x2138;
    reg {
        name="CaptureCompareChannel3WrapValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3WrapValue_Clr @ 0x213c;
    reg {
        name="CaptureCompareChannel4Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4Control_Clr @ 0x2140;
    reg {
        name="CaptureCompareChannel4PreValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4PreValue_Clr @ 0x2144;
    reg {
        name="CaptureCompareChannel4BaseValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4BaseValue_Clr @ 0x2148;
    reg {
        name="CaptureCompareChannel4WrapValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4WrapValue_Clr @ 0x214c;
    reg {
        name="CaptureCompareChannel5Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5Control_Clr @ 0x2150;
    reg {
        name="CaptureCompareChannel5PreValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5PreValue_Clr @ 0x2154;
    reg {
        name="CaptureCompareChannel5BaseValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5BaseValue_Clr @ 0x2158;
    reg {
        name="CaptureCompareChannel5WrapValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5WrapValue_Clr @ 0x215c;
    reg {
        name="CaptureCompareChannel6Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6Control_Clr @ 0x2160;
    reg {
        name="CaptureCompareChannel6PreValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6PreValue_Clr @ 0x2164;
    reg {
        name="CaptureCompareChannel6BaseValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6BaseValue_Clr @ 0x2168;
    reg {
        name="CaptureCompareChannel6WrapValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6WrapValue_Clr @ 0x216c;
    reg {
        name="CaptureCompareChannel7Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7Control_Clr @ 0x2170;
    reg {
        name="CaptureCompareChannel7PreValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7PreValue_Clr @ 0x2174;
    reg {
        name="CaptureCompareChannel7BaseValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7BaseValue_Clr @ 0x2178;
    reg {
        name="CaptureCompareChannel7WrapValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7WrapValue_Clr @ 0x217c;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Enable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Tgl @ 0x3004;
    reg {
        name="Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Tgl @ 0x3008;
    reg {
        name="Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Tgl @ 0x300c;
    reg {
        name="PrescalerChannelSelection_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PrescalerChannelSelection_Tgl @ 0x3010;
    reg {
        name="Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Tgl @ 0x3014;
    reg {
        name="PreCounterValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterValue_Tgl @ 0x3018;
    reg {
        name="BaseCounterValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseCounterValue_Tgl @ 0x301c;
    reg {
        name="WrapCounterValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WrapCounterValue_Tgl @ 0x3020;
    reg {
        name="BaseAndPreCounterValues_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseAndPreCounterValues_Tgl @ 0x3024;
    reg {
        name="LatchedWrapCounterValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LatchedWrapCounterValue_Tgl @ 0x3028;
    reg {
        name="PreCounterTopAdjustValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterTopAdjustValue_Tgl @ 0x302c;
    reg {
        name="PreCounterTopValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterTopValue_Tgl @ 0x3030;
    reg {
        name="BaseCounterTopValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BaseCounterTopValue_Tgl @ 0x3034;
    reg {
        name="WrapCounterTopValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } WrapCounterTopValue_Tgl @ 0x3038;
    reg {
        name="Timeout0Counter_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0Counter_Tgl @ 0x303c;
    reg {
        name="Timeout0CounterTop_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0CounterTop_Tgl @ 0x3040;
    reg {
        name="Timeout0Compare_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout0Compare_Tgl @ 0x3044;
    reg {
        name="Timeout1Counter_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1Counter_Tgl @ 0x3048;
    reg {
        name="Timeout1CounterTop_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1CounterTop_Tgl @ 0x304c;
    reg {
        name="Timeout1Compare_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Timeout1Compare_Tgl @ 0x3050;
    reg {
        name="ListenBeforeTalkWaitControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkWaitControl_Tgl @ 0x3054;
    reg {
        name="ListenBeforeTalkPrescalerChannelSelection_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkPrescalerChannelSelection_Tgl @ 0x3058;
    reg {
        name="ListenBeforeTalkState_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkState_Tgl @ 0x305c;
    reg {
        name="PseudoRandomGeneratorValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PseudoRandomGeneratorValue_Tgl @ 0x3060;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x3064;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x3070;
    reg {
        name="RxControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxControl_Tgl @ 0x3074;
    reg {
        name="TxControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxControl_Tgl @ 0x3078;
    reg {
        name="ListenBeforeTalkETSIStandardSupport_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkETSIStandardSupport_Tgl @ 0x307c;
    reg {
        name="ListenBeforeTalkState1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ListenBeforeTalkState1_Tgl @ 0x3080;
    reg {
        name="LinearRandomValueGeneratedByFirmware0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware0_Tgl @ 0x3084;
    reg {
        name="LinearRandomValueGeneratedByFirmware1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware1_Tgl @ 0x3088;
    reg {
        name="LinearRandomValueGeneratedByFirmware2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LinearRandomValueGeneratedByFirmware2_Tgl @ 0x308c;
    reg {
        name="SequencerInterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Tgl @ 0x3090;
    reg {
        name="SequencerInterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Tgl @ 0x3094;
    reg {
        name="CaptureCompareChannel0Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0Control_Tgl @ 0x3100;
    reg {
        name="CaptureCompareChannel0PreValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0PreValue_Tgl @ 0x3104;
    reg {
        name="CaptureCompareChannel0BaseValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0BaseValue_Tgl @ 0x3108;
    reg {
        name="CaptureCompareChannel0WrapValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel0WrapValue_Tgl @ 0x310c;
    reg {
        name="CaptureCompareChannel1Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1Control_Tgl @ 0x3110;
    reg {
        name="CaptureCompareChannel1PreValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1PreValue_Tgl @ 0x3114;
    reg {
        name="CaptureCompareChannel1BaseValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1BaseValue_Tgl @ 0x3118;
    reg {
        name="CaptureCompareChannel1WrapValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel1WrapValue_Tgl @ 0x311c;
    reg {
        name="CaptureCompareChannel2Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2Control_Tgl @ 0x3120;
    reg {
        name="CaptureCompareChannel2PreValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2PreValue_Tgl @ 0x3124;
    reg {
        name="CaptureCompareChannel2BaseValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2BaseValue_Tgl @ 0x3128;
    reg {
        name="CaptureCompareChannel2WrapValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel2WrapValue_Tgl @ 0x312c;
    reg {
        name="CaptureCompareChannel3Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3Control_Tgl @ 0x3130;
    reg {
        name="CaptureCompareChannel3PreValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3PreValue_Tgl @ 0x3134;
    reg {
        name="CaptureCompareChannel3BaseValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3BaseValue_Tgl @ 0x3138;
    reg {
        name="CaptureCompareChannel3WrapValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel3WrapValue_Tgl @ 0x313c;
    reg {
        name="CaptureCompareChannel4Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4Control_Tgl @ 0x3140;
    reg {
        name="CaptureCompareChannel4PreValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4PreValue_Tgl @ 0x3144;
    reg {
        name="CaptureCompareChannel4BaseValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4BaseValue_Tgl @ 0x3148;
    reg {
        name="CaptureCompareChannel4WrapValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel4WrapValue_Tgl @ 0x314c;
    reg {
        name="CaptureCompareChannel5Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5Control_Tgl @ 0x3150;
    reg {
        name="CaptureCompareChannel5PreValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5PreValue_Tgl @ 0x3154;
    reg {
        name="CaptureCompareChannel5BaseValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5BaseValue_Tgl @ 0x3158;
    reg {
        name="CaptureCompareChannel5WrapValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel5WrapValue_Tgl @ 0x315c;
    reg {
        name="CaptureCompareChannel6Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6Control_Tgl @ 0x3160;
    reg {
        name="CaptureCompareChannel6PreValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6PreValue_Tgl @ 0x3164;
    reg {
        name="CaptureCompareChannel6BaseValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6BaseValue_Tgl @ 0x3168;
    reg {
        name="CaptureCompareChannel6WrapValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel6WrapValue_Tgl @ 0x316c;
    reg {
        name="CaptureCompareChannel7Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7Control_Tgl @ 0x3170;
    reg {
        name="CaptureCompareChannel7PreValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7PreValue_Tgl @ 0x3174;
    reg {
        name="CaptureCompareChannel7BaseValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7BaseValue_Tgl @ 0x3178;
    reg {
        name="CaptureCompareChannel7WrapValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CaptureCompareChannel7WrapValue_Tgl @ 0x317c;
} ProtocolTimerRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion @ 0x0;
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x4;
    reg {
        name="RXENSourceEnable";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
            } SWRXEN[7:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CHANNELBUSYEN[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TIMDETEN[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PREDETEN[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRAMEDETEN[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEMODRXREQEN[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRSRXEN[13:13];
    } RXENSourceEnable @ 0x8;
    reg {
        name="Status";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RXMASK[15:0];
            field {
                sw = r;
            } FORCESTATEACTIVE[19:19];
            field {
                sw = r;
            } TXAFTERFRAMEPEND[20:20];
            field {
                sw = r;
            } TXAFTERFRAMEACTIVE[21:21];
            field {
                sw = r;
            } SEQSLEEPING[22:22];
            field {
                sw = r;
            } SEQSLEEPDEEP[23:23];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } STATE[27:24];
            field {
                sw = r;
            } SEQACTIVE[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEMODENS[29:29];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } TXENS[30:30];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RXENS[31:31];
    } Status @ 0xc;
    reg {
        name="Command";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } TXEN[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } FORCETX[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXONCCA[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } CLEARTXEN[3:3];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } TXAFTERFRAME[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } TXDIS[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } CLEARRXOVERFLOW[6:6];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } RXCAL[7:7];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } RXDIS[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCWR[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCRD[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PAENSET[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PAENCLEAR[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LNAENSET[14:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LNAENCLEAR[15:15];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEMODENSET[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DEMODENCLEAR[31:31];
    } Command @ 0x10;
    reg {
        name="Control";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } FORCEDISABLE[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRSTXEN[1:1];
            field {
                sw = rw;
            } TXAFTERRX[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRSMODE[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRSCLR[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TXPOSTPONE[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ACTIVEPOL[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PAENPOL[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LNAENPOL[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRSRXDIS[10:10];
            field {
                sw = rw;
            } PRSFORCETX[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SEQRESET[24:24];
            field {
                sw = r;
            } EXITSHUTDOWNDIS[25:25];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } CPUWAITDIS[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SEQCLKDIS[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RXOFDIS[28:28];
    } Control @ 0x14;
    reg {
        name="ForceStateTransition";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } FORCESTATE[2:0];
    } ForceStateTransition @ 0x18;
    reg {
        name="InterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } STATECHANGEIF[0:0];
            field {
                sw = rw;
            } STIMCMPEVIF[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SEQLOCKUPIF[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SEQRESETREQIF[3:3];
            field {
                sw = rw;
            } SEQIF[23:16];
    } InterruptFlags @ 0x1c;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } STATECHANGEIEN[0:0];
            field {
                sw = rw;
            } STIMCMPEVIEN[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SEQLOCKUPIEN[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SEQRESETREQIEN[3:3];
            field {
                sw = rw;
            } SEQIEN[23:16];
    } InterruptEnable @ 0x20;
    reg {
        name="TestControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TestControl @ 0x24;
    reg {
        name="SequencerInterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } STATECHANGESEQIF[0:0];
            field {
                sw = rw;
            } STIMCMPEVSEQIF[1:1];
            field {
                sw = rw;
            } DEMODRXREQCLRSEQIF[2:2];
            field {
                sw = rw;
            } PRSEVENTSEQIF[3:3];
            field {
                sw = rw;
            } STATEOFFIF[16:16];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATERXWARMIF[17:17];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATERXSEARCHIF[18:18];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATERXFRAMEIF[19:19];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATERXPDIF[20:20];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATERX2RXIF[21:21];
            field {
                sw = rw;
            } STATERXOVERFLOWIF[22:22];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATERX2TXIF[23:23];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATETXWARMIF[24:24];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATETXIF[25:25];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATETXPDIF[26:26];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATETX2RXIF[27:27];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } STATETX2TXIF[28:28];
            field {
                sw = rw;
            } STATESHUTDOWNIF[29:29];
    } SequencerInterruptFlags @ 0x28;
    reg {
        name="SequencerInterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } STATECHANGESEQIEN[0:0];
            field {
                sw = rw;
            } STIMCMPEVSEQIEN[1:1];
            field {
                sw = rw;
            } DEMODRXREQCLRSEQIEN[2:2];
            field {
                sw = rw;
            } PRSEVENTSEQIEN[3:3];
            field {
                sw = rw;
            } STATEOFFIEN[16:16];
            field {
                sw = rw;
            } STATERXWARMIEN[17:17];
            field {
                sw = rw;
            } STATERXSEARCHIEN[18:18];
            field {
                sw = rw;
            } STATERXFRAMEIEN[19:19];
            field {
                sw = rw;
            } STATERXPDIEN[20:20];
            field {
                sw = rw;
            } STATERX2RXIEN[21:21];
            field {
                sw = rw;
            } STATERXOVERFLOWIEN[22:22];
            field {
                sw = rw;
            } STATERX2TXIEN[23:23];
            field {
                sw = rw;
            } STATETXWARMIEN[24:24];
            field {
                sw = rw;
            } STATETXIEN[25:25];
            field {
                sw = rw;
            } STATETXPDIEN[26:26];
            field {
                sw = rw;
            } STATETX2RXIEN[27:27];
            field {
                sw = rw;
            } STATETX2TXIEN[28:28];
            field {
                sw = rw;
            } STATESHUTDOWNIEN[29:29];
    } SequencerInterruptEnable @ 0x2c;
    reg {
        name="Status1";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } TXMASK[7:0];
    } Status1 @ 0x30;
    reg {
        name="SequencerTimerValue";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } STIMER[15:0];
    } SequencerTimerValue @ 0x34;
    reg {
        name="SequencerTimerCompareValue";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } STIMERCOMP[14:0];
    } SequencerTimerCompareValue @ 0x38;
    reg {
        name="SequencerControl";
        regwidth=0x20;
            field {
                sw = rw;
            } COMPACT[0:0];
            field {
                sw = rw;
            } COMPINVALMODE[2:1];
            field {
                sw = rw;
            } RELATIVE[3:3];
            field {
                sw = rw;
            } STIMERALWAYSRUN[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } STIMERDEBUGRUN[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } STATEDEBUGRUN[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SWIRQ[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SWIRQ_[25:25];
    } SequencerControl @ 0x3c;
    reg {
        name="SequencerPrescaler";
        regwidth=0x20;
            field {
                sw = rw;
                reset=7'b111;
            } STIMERPRESC[6:0];
    } SequencerPrescaler @ 0x40;
    reg {
        name="Storage0";
        regwidth=0x20;
            field {
                sw = rw;
            } SR0[31:0];
    } Storage0 @ 0x44;
    reg {
        name="Storage1";
        regwidth=0x20;
            field {
                sw = rw;
            } SR1[31:0];
    } Storage1 @ 0x48;
    reg {
        name="Storage2";
        regwidth=0x20;
            field {
                sw = rw;
            } SR2[31:0];
    } Storage2 @ 0x4c;
    reg {
        name="Storage3";
        regwidth=0x20;
            field {
                sw = rw;
            } SR3[31:0];
    } Storage3 @ 0x50;
    reg {
        name="SystemTickTimerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTickTimerControl @ 0x54;
    reg {
        name="FrameControlWordBufferWrite";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlWordBufferWrite @ 0x58;
    reg {
        name="FrameControlWordBufferRead";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlWordBufferRead @ 0x5c;
    reg {
        name="Em1pControlAndStatus";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
                onwrite = woset;
            } RADIOEM1PMODE[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RADIOEM1PMODE_[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MCUEM1PMODE[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MCUEM1PDISSWREQ[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RADIOEM1PREQ[16:16];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RADIOEM1PACK[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RADIOEM1PHWREQ[18:18];
    } Em1pControlAndStatus @ 0x60;
    reg {
        name="SynthesizerEnableControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynthesizerEnableControl @ 0x98;
    reg {
        name="SynthesizerRegulatorEnableControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynthesizerRegulatorEnableControl @ 0x9c;
    reg {
        name="VoltageControlledOscillatorControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorControl @ 0xa0;
    reg {
        name="ChargePumpControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpControl @ 0xa4;
    reg {
        name="RadioFrequencyStatus";
        regwidth=0x20;
            field {
                sw = r;
            } MODRAMPUPDONE[0:0];
    } RadioFrequencyStatus @ 0xac;
    reg {
        name="Status2";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } PREVSTATE1[3:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } PREVSTATE2[7:4];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } PREVSTATE3[11:8];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } CURRSTATE[15:12];
    } Status2 @ 0xb0;
    reg {
        name="IntermediateFrequencyProgrammableGainAmplifierControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyProgrammableGainAmplifierControl @ 0xb4;
    reg {
        name="PowerAmplifierEnableControl";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } PARAMP[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } INVRAMPCLK[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DIV2RAMPCLK[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RSTDIV2RAMPCLK[18:18];
    } PowerAmplifierEnableControl @ 0xb8;
    reg {
        name="AutomaticPowerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticPowerControl @ 0xbc;
    reg {
        name="AntennaDiversity";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversity @ 0xc0;
    reg {
        name="AuxiliaryAnalogToDigitalConverterTrim";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterTrim @ 0xc4;
    reg {
        name="AuxiliaryAnalogToDigitalConverterEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterEnable @ 0xc8;
    reg {
        name="AuxiliaryAnalogToDigitalConverterControl0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterControl0 @ 0xcc;
    reg {
        name="AuxiliaryAnalogToDigitalConverterControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterControl1 @ 0xd0;
    reg {
        name="AuxiliaryAnalogToDigitalConverterDigitalOutput";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterDigitalOutput @ 0xd4;
    reg {
        name="ClockMultEnable0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultEnable0 @ 0xd8;
    reg {
        name="ClockMultEnable1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultEnable1 @ 0xdc;
    reg {
        name="ClockMultControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultControl @ 0xe0;
    reg {
        name="ClockMultStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultStatus @ 0xe4;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterDebug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterDebug @ 0xe8;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterTrim0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterTrim0 @ 0xec;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterTrim1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterTrim1 @ 0xf0;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterCalibration @ 0xf4;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterStatus @ 0xf8;
    reg {
        name="LowNoiseAmplifierMixerDebug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerDebug @ 0xfc;
    reg {
        name="LowNoiseAmplifierMixerTrim0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim0 @ 0x100;
    reg {
        name="LowNoiseAmplifierMixerTrim1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim1 @ 0x104;
    reg {
        name="LowNoiseAmplifierMixerTrim2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim2 @ 0x108;
    reg {
        name="LowNoiseAmplifierMixerTrim3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim3 @ 0x10c;
    reg {
        name="LowNoiseAmplifierMixerTrim4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim4 @ 0x110;
    reg {
        name="LowNoiseAmplifierMixerCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerCalibration @ 0x114;
    reg {
        name="LowNoiseAmplifierMixerEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerEnable @ 0x118;
    reg {
        name="PreCounterOverflow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterOverflow @ 0x11c;
    reg {
        name="PowerAmplifierTrim0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim0 @ 0x120;
    reg {
        name="PowerAmplifierTrim1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim1 @ 0x124;
    reg {
        name="PowerAmplifierTrim2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim2 @ 0x128;
    reg {
        name="PowerAmplifierTrim3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim3 @ 0x12c;
    reg {
        name="PowerAmplifierTrim4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim4 @ 0x130;
    reg {
        name="PowerAmplifierTrim5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim5 @ 0x134;
    reg {
        name="TxPower";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxPower @ 0x13c;
    reg {
        name="TxRamp";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxRamp @ 0x140;
    reg {
        name="ProgrammableGainAmplifierTrim";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierTrim @ 0x148;
    reg {
        name="ProgrammableGainAmplifierCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierCalibration @ 0x14c;
    reg {
        name="ProgrammableGainAmplifierControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierControl @ 0x150;
    reg {
        name="RadioFrequencyBiasCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyBiasCalibration @ 0x154;
    reg {
        name="RadioFrequencyBiasControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyBiasControl @ 0x158;
    reg {
        name="RadioEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioEnable @ 0x15c;
    reg {
        name="RadioFrequencyPathEnable0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyPathEnable0 @ 0x160;
    reg {
        name="RadioFrequencyPathEnable1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyPathEnable1 @ 0x164;
    reg {
        name="Rx";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rx @ 0x168;
    reg {
        name="Tx";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Tx @ 0x16c;
    reg {
        name="SyDebug";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyDebug @ 0x170;
    reg {
        name="SyTrim0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyTrim0 @ 0x174;
    reg {
        name="SyTrim1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyTrim1 @ 0x178;
    reg {
        name="SyCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyCalibration @ 0x17c;
    reg {
        name="SyEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyEnable @ 0x180;
    reg {
        name="SyloEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyloEnable @ 0x184;
    reg {
        name="SymmControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SymmControl @ 0x188;
    reg {
        name="DigitalClockRetimeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalClockRetimeControl @ 0x190;
    reg {
        name="DigitalClockRetimeStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalClockRetimeStatus @ 0x194;
    reg {
        name="XoRetimeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XoRetimeControl @ 0x198;
    reg {
        name="XoRetimeStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XoRetimeStatus @ 0x19c;
    reg {
        name="AutomaticGainControlOverwrite0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite0 @ 0x1a0;
    reg {
        name="AutomaticGainControlOverwrite1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite1 @ 0x1a4;
    reg {
        name="AutomaticGainControlOverwrite2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite2 @ 0x1a8;
    reg {
        name="Spare";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare @ 0x1c4;
    reg {
        name="PowerAmplifierControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierControl @ 0x1c8;
    reg {
        name="FeNotch0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotch0 @ 0x1cc;
    reg {
        name="FeNotch1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotch1 @ 0x1d0;
    reg {
        name="Scratch0";
        regwidth=0x20;
            field {
                sw = rw;
            } SCRATCH0[31:0];
    } Scratch0 @ 0x3e0;
    reg {
        name="Scratch1";
        regwidth=0x20;
            field {
                sw = rw;
            } SCRATCH1[31:0];
    } Scratch1 @ 0x3e4;
    reg {
        name="Scratch2";
        regwidth=0x20;
            field {
                sw = rw;
            } SCRATCH2[31:0];
    } Scratch2 @ 0x3e8;
    reg {
        name="Scratch3";
        regwidth=0x20;
            field {
                sw = rw;
            } SCRATCH3[31:0];
    } Scratch3 @ 0x3ec;
    reg {
        name="Scratch4";
        regwidth=0x20;
            field {
                sw = rw;
            } SCRATCH4[31:0];
    } Scratch4 @ 0x3f0;
    reg {
        name="Scratch5";
        regwidth=0x20;
            field {
                sw = rw;
            } SCRATCH5[31:0];
    } Scratch5 @ 0x3f4;
    reg {
        name="Scratch6";
        regwidth=0x20;
            field {
                sw = rw;
            } SCRATCH6[31:0];
    } Scratch6 @ 0x3f8;
    reg {
        name="Scratch7";
        regwidth=0x20;
            field {
                sw = rw;
            } SCRATCH7[31:0];
    } Scratch7 @ 0x3fc;
    reg {
        name="ThermisterControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ThermisterControl @ 0x7e8;
    reg {
        name="DiagaAlternateEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateEnable @ 0x7ec;
    reg {
        name="DiagaAlternateRfBlocksAndTpSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateRfBlocksAndTpSelect @ 0x7f0;
    reg {
        name="DiagaAlternateBridgeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateBridgeControl @ 0x7f4;
    reg {
        name="RadioFrequencyLock0";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SYNTHLODIVFREQCTRL[9:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RACIFPGAEN[16:16];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } RACTX0DBM[17:17];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } RACTX10DBM[18:18];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } RACTX20DBM[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMHADM[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCCONVMODE[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCPAUSING[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMANTSWENABLE[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMLRBLE[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMDSSS[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMDEC1[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMMODFORMAT[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMDUALSYNC[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMANTDIVMODE[30:30];
            field {
                sw = rw;
                reset=1'b1;
            } UNLOCKED[31:31];
    } RadioFrequencyLock0 @ 0x7f8;
    reg {
        name="RadioFrequencyLock1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyLock1 @ 0x7fc;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Enable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Set @ 0x1004;
    reg {
        name="RXENSourceEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RXENSourceEnable_Set @ 0x1008;
    reg {
        name="Status0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status0_Set @ 0x100c;
    reg {
        name="Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Set @ 0x1010;
    reg {
        name="Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Set @ 0x1014;
    reg {
        name="ForceStateTransition_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ForceStateTransition_Set @ 0x1018;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x101c;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x1020;
    reg {
        name="TestControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TestControl_Set @ 0x1024;
    reg {
        name="SequencerInterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Set @ 0x1028;
    reg {
        name="SequencerInterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Set @ 0x102c;
    reg {
        name="Status1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status1_Set @ 0x1030;
    reg {
        name="SequencerTimerValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerTimerValue_Set @ 0x1034;
    reg {
        name="SequencerTimerCompareValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerTimerCompareValue_Set @ 0x1038;
    reg {
        name="SequencerControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerControl_Set @ 0x103c;
    reg {
        name="SequencerPrescaler_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerPrescaler_Set @ 0x1040;
    reg {
        name="Storage0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage0_Set @ 0x1044;
    reg {
        name="Storage1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage1_Set @ 0x1048;
    reg {
        name="Storage2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage2_Set @ 0x104c;
    reg {
        name="Storage3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage3_Set @ 0x1050;
    reg {
        name="SystemTickTimerControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTickTimerControl_Set @ 0x1054;
    reg {
        name="FrameControlWordBufferWrite_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlWordBufferWrite_Set @ 0x1058;
    reg {
        name="FrameControlWordBufferRead_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlWordBufferRead_Set @ 0x105c;
    reg {
        name="Em1pControlAndStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em1pControlAndStatus_Set @ 0x1060;
    reg {
        name="SynthesizerEnableControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynthesizerEnableControl_Set @ 0x1098;
    reg {
        name="SynthesizerRegulatorEnableControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynthesizerRegulatorEnableControl_Set @ 0x109c;
    reg {
        name="VoltageControlledOscillatorControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorControl_Set @ 0x10a0;
    reg {
        name="ChargePumpControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpControl_Set @ 0x10a4;
    reg {
        name="RadioFrequencyStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyStatus_Set @ 0x10ac;
    reg {
        name="Status2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Set @ 0x10b0;
    reg {
        name="IntermediateFrequencyProgrammableGainAmplifierControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyProgrammableGainAmplifierControl_Set @ 0x10b4;
    reg {
        name="PowerAmplifierEnableControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierEnableControl_Set @ 0x10b8;
    reg {
        name="AutomaticPowerControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticPowerControl_Set @ 0x10bc;
    reg {
        name="AntennaDiversity_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversity_Set @ 0x10c0;
    reg {
        name="AuxiliaryAnalogToDigitalConverterTrim_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterTrim_Set @ 0x10c4;
    reg {
        name="AuxiliaryAnalogToDigitalConverterEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterEnable_Set @ 0x10c8;
    reg {
        name="AuxiliaryAnalogToDigitalConverterControl0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterControl0_Set @ 0x10cc;
    reg {
        name="AuxiliaryAnalogToDigitalConverterControl1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterControl1_Set @ 0x10d0;
    reg {
        name="AuxiliaryAnalogToDigitalConverterDigitalOutput_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterDigitalOutput_Set @ 0x10d4;
    reg {
        name="ClockMultEnable0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultEnable0_Set @ 0x10d8;
    reg {
        name="ClockMultEnable1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultEnable1_Set @ 0x10dc;
    reg {
        name="ClockMultControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultControl_Set @ 0x10e0;
    reg {
        name="ClockMultStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultStatus_Set @ 0x10e4;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterDebug_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterDebug_Set @ 0x10e8;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterTrim0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterTrim0_Set @ 0x10ec;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterTrim1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterTrim1_Set @ 0x10f0;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterCalibration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterCalibration_Set @ 0x10f4;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterStatus_Set @ 0x10f8;
    reg {
        name="LowNoiseAmplifierMixerDebug_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerDebug_Set @ 0x10fc;
    reg {
        name="LowNoiseAmplifierMixerTrim0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim0_Set @ 0x1100;
    reg {
        name="LowNoiseAmplifierMixerTrim1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim1_Set @ 0x1104;
    reg {
        name="LowNoiseAmplifierMixerTrim2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim2_Set @ 0x1108;
    reg {
        name="LowNoiseAmplifierMixerTrim3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim3_Set @ 0x110c;
    reg {
        name="LowNoiseAmplifierMixerTrim4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim4_Set @ 0x1110;
    reg {
        name="LowNoiseAmplifierMixerCalibration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerCalibration_Set @ 0x1114;
    reg {
        name="LowNoiseAmplifierMixerEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerEnable_Set @ 0x1118;
    reg {
        name="PreCounterOverflow_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterOverflow_Set @ 0x111c;
    reg {
        name="PowerAmplifierTrim0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim0_Set @ 0x1120;
    reg {
        name="PowerAmplifierTrim1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim1_Set @ 0x1124;
    reg {
        name="PowerAmplifierTrim2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim2_Set @ 0x1128;
    reg {
        name="PowerAmplifierTrim3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim3_Set @ 0x112c;
    reg {
        name="PowerAmplifierTrim4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim4_Set @ 0x1130;
    reg {
        name="PowerAmplifierTrim5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim5_Set @ 0x1134;
    reg {
        name="TxPower_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxPower_Set @ 0x113c;
    reg {
        name="TxRamp_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxRamp_Set @ 0x1140;
    reg {
        name="ProgrammableGainAmplifierTrim_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierTrim_Set @ 0x1148;
    reg {
        name="ProgrammableGainAmplifierCalibration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierCalibration_Set @ 0x114c;
    reg {
        name="ProgrammableGainAmplifierControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierControl_Set @ 0x1150;
    reg {
        name="RadioFrequencyBiasCalibration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyBiasCalibration_Set @ 0x1154;
    reg {
        name="RadioFrequencyBiasControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyBiasControl_Set @ 0x1158;
    reg {
        name="RadioEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioEnable_Set @ 0x115c;
    reg {
        name="RadioFrequencyPathEnable0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyPathEnable0_Set @ 0x1160;
    reg {
        name="RadioFrequencyPathEnable1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyPathEnable1_Set @ 0x1164;
    reg {
        name="Rx_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rx_Set @ 0x1168;
    reg {
        name="Tx_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Tx_Set @ 0x116c;
    reg {
        name="SyDebug_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyDebug_Set @ 0x1170;
    reg {
        name="SyTrim0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyTrim0_Set @ 0x1174;
    reg {
        name="SyTrim1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyTrim1_Set @ 0x1178;
    reg {
        name="SyCalibration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyCalibration_Set @ 0x117c;
    reg {
        name="SyEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyEnable_Set @ 0x1180;
    reg {
        name="SyloEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyloEnable_Set @ 0x1184;
    reg {
        name="SymmControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SymmControl_Set @ 0x1188;
    reg {
        name="DigitalClockRetimeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalClockRetimeControl_Set @ 0x1190;
    reg {
        name="DigitalClockRetimeStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalClockRetimeStatus_Set @ 0x1194;
    reg {
        name="XoRetimeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XoRetimeControl_Set @ 0x1198;
    reg {
        name="XoRetimeStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XoRetimeStatus_Set @ 0x119c;
    reg {
        name="AutomaticGainControlOverwrite0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite0_Set @ 0x11a0;
    reg {
        name="AutomaticGainControlOverwrite1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite1_Set @ 0x11a4;
    reg {
        name="AutomaticGainControlOverwrite2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite2_Set @ 0x11a8;
    reg {
        name="Spare_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Set @ 0x11c4;
    reg {
        name="PowerAmplifierControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierControl_Set @ 0x11c8;
    reg {
        name="FeNotch0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotch0_Set @ 0x11cc;
    reg {
        name="FeNotch1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotch1_Set @ 0x11d0;
    reg {
        name="Scratch0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch0_Set @ 0x13e0;
    reg {
        name="Scratch1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch1_Set @ 0x13e4;
    reg {
        name="Scratch2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch2_Set @ 0x13e8;
    reg {
        name="Scratch3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch3_Set @ 0x13ec;
    reg {
        name="Scratch4_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch4_Set @ 0x13f0;
    reg {
        name="Scratch5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch5_Set @ 0x13f4;
    reg {
        name="Scratch6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch6_Set @ 0x13f8;
    reg {
        name="Scratch7_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch7_Set @ 0x13fc;
    reg {
        name="ThermisterControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ThermisterControl_Set @ 0x17e8;
    reg {
        name="DiagaAlternateEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateEnable_Set @ 0x17ec;
    reg {
        name="DiagaAlternateRfBlocksAndTpSelect_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateRfBlocksAndTpSelect_Set @ 0x17f0;
    reg {
        name="DiagaAlternateBridgeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateBridgeControl_Set @ 0x17f4;
    reg {
        name="RadioFrequencyLock0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyLock0_Set @ 0x17f8;
    reg {
        name="RadioFrequencyLock1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyLock1_Set @ 0x17fc;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Enable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Clr @ 0x2004;
    reg {
        name="RXENSourceEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RXENSourceEnable_Clr @ 0x2008;
    reg {
        name="Status0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status0_Clr @ 0x200c;
    reg {
        name="Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Clr @ 0x2010;
    reg {
        name="Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Clr @ 0x2014;
    reg {
        name="ForceStateTransition_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ForceStateTransition_Clr @ 0x2018;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x201c;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x2020;
    reg {
        name="TestControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TestControl_Clr @ 0x2024;
    reg {
        name="SequencerInterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Clr @ 0x2028;
    reg {
        name="SequencerInterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Clr @ 0x202c;
    reg {
        name="Status1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status1_Clr @ 0x2030;
    reg {
        name="SequencerTimerValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerTimerValue_Clr @ 0x2034;
    reg {
        name="SequencerTimerCompareValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerTimerCompareValue_Clr @ 0x2038;
    reg {
        name="SequencerControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerControl_Clr @ 0x203c;
    reg {
        name="SequencerPrescaler_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerPrescaler_Clr @ 0x2040;
    reg {
        name="Storage0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage0_Clr @ 0x2044;
    reg {
        name="Storage1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage1_Clr @ 0x2048;
    reg {
        name="Storage2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage2_Clr @ 0x204c;
    reg {
        name="Storage3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage3_Clr @ 0x2050;
    reg {
        name="SystemTickTimerControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTickTimerControl_Clr @ 0x2054;
    reg {
        name="FrameControlWordBufferWrite_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlWordBufferWrite_Clr @ 0x2058;
    reg {
        name="FrameControlWordBufferRead_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlWordBufferRead_Clr @ 0x205c;
    reg {
        name="Em1pControlAndStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em1pControlAndStatus_Clr @ 0x2060;
    reg {
        name="SynthesizerEnableControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynthesizerEnableControl_Clr @ 0x2098;
    reg {
        name="SynthesizerRegulatorEnableControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynthesizerRegulatorEnableControl_Clr @ 0x209c;
    reg {
        name="VoltageControlledOscillatorControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorControl_Clr @ 0x20a0;
    reg {
        name="ChargePumpControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpControl_Clr @ 0x20a4;
    reg {
        name="RadioFrequencyStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyStatus_Clr @ 0x20ac;
    reg {
        name="Status2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Clr @ 0x20b0;
    reg {
        name="IntermediateFrequencyProgrammableGainAmplifierControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyProgrammableGainAmplifierControl_Clr @ 0x20b4;
    reg {
        name="PowerAmplifierEnableControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierEnableControl_Clr @ 0x20b8;
    reg {
        name="AutomaticPowerControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticPowerControl_Clr @ 0x20bc;
    reg {
        name="AntennaDiversity_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversity_Clr @ 0x20c0;
    reg {
        name="AuxiliaryAnalogToDigitalConverterTrim_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterTrim_Clr @ 0x20c4;
    reg {
        name="AuxiliaryAnalogToDigitalConverterEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterEnable_Clr @ 0x20c8;
    reg {
        name="AuxiliaryAnalogToDigitalConverterControl0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterControl0_Clr @ 0x20cc;
    reg {
        name="AuxiliaryAnalogToDigitalConverterControl1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterControl1_Clr @ 0x20d0;
    reg {
        name="AuxiliaryAnalogToDigitalConverterDigitalOutput_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterDigitalOutput_Clr @ 0x20d4;
    reg {
        name="ClockMultEnable0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultEnable0_Clr @ 0x20d8;
    reg {
        name="ClockMultEnable1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultEnable1_Clr @ 0x20dc;
    reg {
        name="ClockMultControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultControl_Clr @ 0x20e0;
    reg {
        name="ClockMultStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultStatus_Clr @ 0x20e4;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterDebug_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterDebug_Clr @ 0x20e8;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterTrim0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterTrim0_Clr @ 0x20ec;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterTrim1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterTrim1_Clr @ 0x20f0;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterCalibration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterCalibration_Clr @ 0x20f4;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterStatus_Clr @ 0x20f8;
    reg {
        name="LowNoiseAmplifierMixerDebug_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerDebug_Clr @ 0x20fc;
    reg {
        name="LowNoiseAmplifierMixerTrim0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim0_Clr @ 0x2100;
    reg {
        name="LowNoiseAmplifierMixerTrim1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim1_Clr @ 0x2104;
    reg {
        name="LowNoiseAmplifierMixerTrim2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim2_Clr @ 0x2108;
    reg {
        name="LowNoiseAmplifierMixerTrim3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim3_Clr @ 0x210c;
    reg {
        name="LowNoiseAmplifierMixerTrim4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim4_Clr @ 0x2110;
    reg {
        name="LowNoiseAmplifierMixerCalibration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerCalibration_Clr @ 0x2114;
    reg {
        name="LowNoiseAmplifierMixerEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerEnable_Clr @ 0x2118;
    reg {
        name="PreCounterOverflow_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterOverflow_Clr @ 0x211c;
    reg {
        name="PowerAmplifierTrim0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim0_Clr @ 0x2120;
    reg {
        name="PowerAmplifierTrim1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim1_Clr @ 0x2124;
    reg {
        name="PowerAmplifierTrim2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim2_Clr @ 0x2128;
    reg {
        name="PowerAmplifierTrim3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim3_Clr @ 0x212c;
    reg {
        name="PowerAmplifierTrim4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim4_Clr @ 0x2130;
    reg {
        name="PowerAmplifierTrim5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim5_Clr @ 0x2134;
    reg {
        name="TxPower_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxPower_Clr @ 0x213c;
    reg {
        name="TxRamp_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxRamp_Clr @ 0x2140;
    reg {
        name="ProgrammableGainAmplifierTrim_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierTrim_Clr @ 0x2148;
    reg {
        name="ProgrammableGainAmplifierCalibration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierCalibration_Clr @ 0x214c;
    reg {
        name="ProgrammableGainAmplifierControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierControl_Clr @ 0x2150;
    reg {
        name="RadioFrequencyBiasCalibration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyBiasCalibration_Clr @ 0x2154;
    reg {
        name="RadioFrequencyBiasControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyBiasControl_Clr @ 0x2158;
    reg {
        name="RadioEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioEnable_Clr @ 0x215c;
    reg {
        name="RadioFrequencyPathEnable0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyPathEnable0_Clr @ 0x2160;
    reg {
        name="RadioFrequencyPathEnable1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyPathEnable1_Clr @ 0x2164;
    reg {
        name="Rx_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rx_Clr @ 0x2168;
    reg {
        name="Tx_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Tx_Clr @ 0x216c;
    reg {
        name="SyDebug_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyDebug_Clr @ 0x2170;
    reg {
        name="SyTrim0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyTrim0_Clr @ 0x2174;
    reg {
        name="SyTrim1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyTrim1_Clr @ 0x2178;
    reg {
        name="SyCalibration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyCalibration_Clr @ 0x217c;
    reg {
        name="SyEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyEnable_Clr @ 0x2180;
    reg {
        name="SyloEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyloEnable_Clr @ 0x2184;
    reg {
        name="SymmControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SymmControl_Clr @ 0x2188;
    reg {
        name="DigitalClockRetimeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalClockRetimeControl_Clr @ 0x2190;
    reg {
        name="DigitalClockRetimeStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalClockRetimeStatus_Clr @ 0x2194;
    reg {
        name="XoRetimeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XoRetimeControl_Clr @ 0x2198;
    reg {
        name="XoRetimeStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XoRetimeStatus_Clr @ 0x219c;
    reg {
        name="AutomaticGainControlOverwrite0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite0_Clr @ 0x21a0;
    reg {
        name="AutomaticGainControlOverwrite1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite1_Clr @ 0x21a4;
    reg {
        name="AutomaticGainControlOverwrite2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite2_Clr @ 0x21a8;
    reg {
        name="Spare_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Clr @ 0x21c4;
    reg {
        name="PowerAmplifierControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierControl_Clr @ 0x21c8;
    reg {
        name="FeNotch0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotch0_Clr @ 0x21cc;
    reg {
        name="FeNotch1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotch1_Clr @ 0x21d0;
    reg {
        name="Scratch0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch0_Clr @ 0x23e0;
    reg {
        name="Scratch1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch1_Clr @ 0x23e4;
    reg {
        name="Scratch2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch2_Clr @ 0x23e8;
    reg {
        name="Scratch3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch3_Clr @ 0x23ec;
    reg {
        name="Scratch4_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch4_Clr @ 0x23f0;
    reg {
        name="Scratch5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch5_Clr @ 0x23f4;
    reg {
        name="Scratch6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch6_Clr @ 0x23f8;
    reg {
        name="Scratch7_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch7_Clr @ 0x23fc;
    reg {
        name="ThermisterControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ThermisterControl_Clr @ 0x27e8;
    reg {
        name="DiagaAlternateEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateEnable_Clr @ 0x27ec;
    reg {
        name="DiagaAlternateRfBlocksAndTpSelect_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateRfBlocksAndTpSelect_Clr @ 0x27f0;
    reg {
        name="DiagaAlternateBridgeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateBridgeControl_Clr @ 0x27f4;
    reg {
        name="RadioFrequencyLock0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyLock0_Clr @ 0x27f8;
    reg {
        name="RadioFrequencyLock1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyLock1_Clr @ 0x27fc;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Enable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Tgl @ 0x3004;
    reg {
        name="RXENSourceEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RXENSourceEnable_Tgl @ 0x3008;
    reg {
        name="Status0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status0_Tgl @ 0x300c;
    reg {
        name="Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Tgl @ 0x3010;
    reg {
        name="Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Tgl @ 0x3014;
    reg {
        name="ForceStateTransition_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ForceStateTransition_Tgl @ 0x3018;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x301c;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x3020;
    reg {
        name="TestControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TestControl_Tgl @ 0x3024;
    reg {
        name="SequencerInterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Tgl @ 0x3028;
    reg {
        name="SequencerInterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Tgl @ 0x302c;
    reg {
        name="Status1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status1_Tgl @ 0x3030;
    reg {
        name="SequencerTimerValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerTimerValue_Tgl @ 0x3034;
    reg {
        name="SequencerTimerCompareValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerTimerCompareValue_Tgl @ 0x3038;
    reg {
        name="SequencerControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerControl_Tgl @ 0x303c;
    reg {
        name="SequencerPrescaler_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerPrescaler_Tgl @ 0x3040;
    reg {
        name="Storage0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage0_Tgl @ 0x3044;
    reg {
        name="Storage1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage1_Tgl @ 0x3048;
    reg {
        name="Storage2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage2_Tgl @ 0x304c;
    reg {
        name="Storage3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Storage3_Tgl @ 0x3050;
    reg {
        name="SystemTickTimerControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SystemTickTimerControl_Tgl @ 0x3054;
    reg {
        name="FrameControlWordBufferWrite_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlWordBufferWrite_Tgl @ 0x3058;
    reg {
        name="FrameControlWordBufferRead_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrameControlWordBufferRead_Tgl @ 0x305c;
    reg {
        name="Em1pControlAndStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Em1pControlAndStatus_Tgl @ 0x3060;
    reg {
        name="SynthesizerEnableControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynthesizerEnableControl_Tgl @ 0x3098;
    reg {
        name="SynthesizerRegulatorEnableControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynthesizerRegulatorEnableControl_Tgl @ 0x309c;
    reg {
        name="VoltageControlledOscillatorControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorControl_Tgl @ 0x30a0;
    reg {
        name="ChargePumpControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpControl_Tgl @ 0x30a4;
    reg {
        name="RadioFrequencyStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyStatus_Tgl @ 0x30ac;
    reg {
        name="Status2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status2_Tgl @ 0x30b0;
    reg {
        name="IntermediateFrequencyProgrammableGainAmplifierControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyProgrammableGainAmplifierControl_Tgl @ 0x30b4;
    reg {
        name="PowerAmplifierEnableControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierEnableControl_Tgl @ 0x30b8;
    reg {
        name="AutomaticPowerControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticPowerControl_Tgl @ 0x30bc;
    reg {
        name="AntennaDiversity_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AntennaDiversity_Tgl @ 0x30c0;
    reg {
        name="AuxiliaryAnalogToDigitalConverterTrim_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterTrim_Tgl @ 0x30c4;
    reg {
        name="AuxiliaryAnalogToDigitalConverterEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterEnable_Tgl @ 0x30c8;
    reg {
        name="AuxiliaryAnalogToDigitalConverterControl0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterControl0_Tgl @ 0x30cc;
    reg {
        name="AuxiliaryAnalogToDigitalConverterControl1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterControl1_Tgl @ 0x30d0;
    reg {
        name="AuxiliaryAnalogToDigitalConverterDigitalOutput_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryAnalogToDigitalConverterDigitalOutput_Tgl @ 0x30d4;
    reg {
        name="ClockMultEnable0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultEnable0_Tgl @ 0x30d8;
    reg {
        name="ClockMultEnable1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultEnable1_Tgl @ 0x30dc;
    reg {
        name="ClockMultControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultControl_Tgl @ 0x30e0;
    reg {
        name="ClockMultStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockMultStatus_Tgl @ 0x30e4;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterDebug_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterDebug_Tgl @ 0x30e8;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterTrim0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterTrim0_Tgl @ 0x30ec;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterTrim1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterTrim1_Tgl @ 0x30f0;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterCalibration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterCalibration_Tgl @ 0x30f4;
    reg {
        name="IntermediateFrequencyAnalogToDigitalConverterStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAnalogToDigitalConverterStatus_Tgl @ 0x30f8;
    reg {
        name="LowNoiseAmplifierMixerDebug_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerDebug_Tgl @ 0x30fc;
    reg {
        name="LowNoiseAmplifierMixerTrim0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim0_Tgl @ 0x3100;
    reg {
        name="LowNoiseAmplifierMixerTrim1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim1_Tgl @ 0x3104;
    reg {
        name="LowNoiseAmplifierMixerTrim2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim2_Tgl @ 0x3108;
    reg {
        name="LowNoiseAmplifierMixerTrim3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim3_Tgl @ 0x310c;
    reg {
        name="LowNoiseAmplifierMixerTrim4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerTrim4_Tgl @ 0x3110;
    reg {
        name="LowNoiseAmplifierMixerCalibration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerCalibration_Tgl @ 0x3114;
    reg {
        name="LowNoiseAmplifierMixerEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifierMixerEnable_Tgl @ 0x3118;
    reg {
        name="PreCounterOverflow_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreCounterOverflow_Tgl @ 0x311c;
    reg {
        name="PowerAmplifierTrim0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim0_Tgl @ 0x3120;
    reg {
        name="PowerAmplifierTrim1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim1_Tgl @ 0x3124;
    reg {
        name="PowerAmplifierTrim2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim2_Tgl @ 0x3128;
    reg {
        name="PowerAmplifierTrim3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim3_Tgl @ 0x312c;
    reg {
        name="PowerAmplifierTrim4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim4_Tgl @ 0x3130;
    reg {
        name="PowerAmplifierTrim5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierTrim5_Tgl @ 0x3134;
    reg {
        name="TxPower_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxPower_Tgl @ 0x313c;
    reg {
        name="TxRamp_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxRamp_Tgl @ 0x3140;
    reg {
        name="ProgrammableGainAmplifierTrim_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierTrim_Tgl @ 0x3148;
    reg {
        name="ProgrammableGainAmplifierCalibration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierCalibration_Tgl @ 0x314c;
    reg {
        name="ProgrammableGainAmplifierControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ProgrammableGainAmplifierControl_Tgl @ 0x3150;
    reg {
        name="RadioFrequencyBiasCalibration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyBiasCalibration_Tgl @ 0x3154;
    reg {
        name="RadioFrequencyBiasControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyBiasControl_Tgl @ 0x3158;
    reg {
        name="RadioEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioEnable_Tgl @ 0x315c;
    reg {
        name="RadioFrequencyPathEnable0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyPathEnable0_Tgl @ 0x3160;
    reg {
        name="RadioFrequencyPathEnable1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyPathEnable1_Tgl @ 0x3164;
    reg {
        name="Rx_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Rx_Tgl @ 0x3168;
    reg {
        name="Tx_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Tx_Tgl @ 0x316c;
    reg {
        name="SyDebug_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyDebug_Tgl @ 0x3170;
    reg {
        name="SyTrim0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyTrim0_Tgl @ 0x3174;
    reg {
        name="SyTrim1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyTrim1_Tgl @ 0x3178;
    reg {
        name="SyCalibration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyCalibration_Tgl @ 0x317c;
    reg {
        name="SyEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyEnable_Tgl @ 0x3180;
    reg {
        name="SyloEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyloEnable_Tgl @ 0x3184;
    reg {
        name="SymmControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SymmControl_Tgl @ 0x3188;
    reg {
        name="DigitalClockRetimeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalClockRetimeControl_Tgl @ 0x3190;
    reg {
        name="DigitalClockRetimeStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalClockRetimeStatus_Tgl @ 0x3194;
    reg {
        name="XoRetimeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XoRetimeControl_Tgl @ 0x3198;
    reg {
        name="XoRetimeStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } XoRetimeStatus_Tgl @ 0x319c;
    reg {
        name="AutomaticGainControlOverwrite0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite0_Tgl @ 0x31a0;
    reg {
        name="AutomaticGainControlOverwrite1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite1_Tgl @ 0x31a4;
    reg {
        name="AutomaticGainControlOverwrite2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControlOverwrite2_Tgl @ 0x31a8;
    reg {
        name="Spare_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Spare_Tgl @ 0x31c4;
    reg {
        name="PowerAmplifierControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierControl_Tgl @ 0x31c8;
    reg {
        name="FeNotch0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotch0_Tgl @ 0x31cc;
    reg {
        name="FeNotch1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FeNotch1_Tgl @ 0x31d0;
    reg {
        name="Scratch0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch0_Tgl @ 0x33e0;
    reg {
        name="Scratch1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch1_Tgl @ 0x33e4;
    reg {
        name="Scratch2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch2_Tgl @ 0x33e8;
    reg {
        name="Scratch3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch3_Tgl @ 0x33ec;
    reg {
        name="Scratch4_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch4_Tgl @ 0x33f0;
    reg {
        name="Scratch5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch5_Tgl @ 0x33f4;
    reg {
        name="Scratch6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch6_Tgl @ 0x33f8;
    reg {
        name="Scratch7_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Scratch7_Tgl @ 0x33fc;
    reg {
        name="ThermisterControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ThermisterControl_Tgl @ 0x37e8;
    reg {
        name="DiagaAlternateEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateEnable_Tgl @ 0x37ec;
    reg {
        name="DiagaAlternateRfBlocksAndTpSelect_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateRfBlocksAndTpSelect_Tgl @ 0x37f0;
    reg {
        name="DiagaAlternateBridgeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DiagaAlternateBridgeControl_Tgl @ 0x37f4;
    reg {
        name="RadioFrequencyLock0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyLock0_Tgl @ 0x37f8;
    reg {
        name="RadioFrequencyLock1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RadioFrequencyLock1_Tgl @ 0x37fc;
} RadioControllerRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion @ 0x0;
    reg {
        name="Enable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable @ 0x4;
    reg {
        name="Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status @ 0x8;
    reg {
        name="Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command @ 0xc;
    reg {
        name="Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control @ 0x10;
    reg {
        name="CalibrationControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationControl @ 0x14;
    reg {
        name="VCDACControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VCDACControl @ 0x2c;
    reg {
        name="Frequency";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Frequency @ 0x34;
    reg {
        name="IntermediateFrequency";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequency @ 0x38;
    reg {
        name="FrequencyDivisionControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyDivisionControl @ 0x3c;
    reg {
        name="ChannelControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelControl @ 0x40;
    reg {
        name="ChannelSpacing";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } CHSP[15:0];
    } ChannelSpacing @ 0x44;
    reg {
        name="CalibrationOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationOffset @ 0x48;
    reg {
        name="VoltageControlledOscillatorFrequencyTuning";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorFrequencyTuning @ 0x4c;
    reg {
        name="VoltageControlledOscillatorFrequencyRangeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorFrequencyRangeControl @ 0x54;
    reg {
        name="VoltageControlledOscillatorGainCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorGainCalibration @ 0x58;
    reg {
        name="ChargePumpDigitalToAnalogConverterControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpDigitalToAnalogConverterControl @ 0x68;
    reg {
        name="CapacitorArrayCalibrationCycleCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CapacitorArrayCalibrationCycleCount @ 0x6c;
    reg {
        name="VoltageControlledOscillatorForceCalibrationCycleCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorForceCalibrationCycleCount @ 0x70;
    reg {
        name="InterruptFlags";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags @ 0x78;
    reg {
        name="InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable @ 0x84;
    reg {
        name="LoCounterControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterControl @ 0x88;
    reg {
        name="LoCounterStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterStatus @ 0x8c;
    reg {
        name="LoCounterTargetValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterTargetValue @ 0x90;
    reg {
        name="MmdDenominatorInitialValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MmdDenominatorInitialValue @ 0x94;
    reg {
        name="ChargePumpDigitalToAnalogConverterInitialValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpDigitalToAnalogConverterInitialValue @ 0x98;
    reg {
        name="LowPassFilterCalModeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterCalModeControl @ 0x9c;
    reg {
        name="LowPassFilterRxModeControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterRxModeControl1 @ 0xa0;
    reg {
        name="LowPassFilterTxModeControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterTxModeControl1 @ 0xa4;
    reg {
        name="LowPassFilterRxModeControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterRxModeControl2 @ 0xa8;
    reg {
        name="LowPassFilterTxModeControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterTxModeControl2 @ 0xac;
    reg {
        name="DsmRxModeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DsmRxModeControl @ 0xb0;
    reg {
        name="DsmTxModeControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DsmTxModeControl @ 0xb4;
    reg {
        name="SequencerInterruptFlags";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags @ 0xb8;
    reg {
        name="SequencerInterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable @ 0xbc;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Enable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Set @ 0x1004;
    reg {
        name="Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Set @ 0x1008;
    reg {
        name="Command_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Set @ 0x100c;
    reg {
        name="Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Set @ 0x1010;
    reg {
        name="CalibrationControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationControl_Set @ 0x1014;
    reg {
        name="VCDACControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VCDACControl_Set @ 0x102c;
    reg {
        name="Frequency_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Frequency_Set @ 0x1034;
    reg {
        name="IntermediateFrequency_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequency_Set @ 0x1038;
    reg {
        name="FrequencyDivisionControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyDivisionControl_Set @ 0x103c;
    reg {
        name="ChannelControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelControl_Set @ 0x1040;
    reg {
        name="ChannelSpacing_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelSpacing_Set @ 0x1044;
    reg {
        name="CalibrationOffset_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationOffset_Set @ 0x1048;
    reg {
        name="VoltageControlledOscillatorFrequencyTuning_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorFrequencyTuning_Set @ 0x104c;
    reg {
        name="VoltageControlledOscillatorFrequencyRangeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorFrequencyRangeControl_Set @ 0x1054;
    reg {
        name="VoltageControlledOscillatorGainCalibration_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorGainCalibration_Set @ 0x1058;
    reg {
        name="ChargePumpDigitalToAnalogConverterControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpDigitalToAnalogConverterControl_Set @ 0x1068;
    reg {
        name="CapacitorArrayCalibrationCycleCount_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CapacitorArrayCalibrationCycleCount_Set @ 0x106c;
    reg {
        name="VoltageControlledOscillatorForceCalibrationCycleCount_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorForceCalibrationCycleCount_Set @ 0x1070;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x1078;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x1084;
    reg {
        name="LoCounterControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterControl_Set @ 0x1088;
    reg {
        name="LoCounterStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterStatus_Set @ 0x108c;
    reg {
        name="LoCounterTargetValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterTargetValue_Set @ 0x1090;
    reg {
        name="MmdDenominatorInitialValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MmdDenominatorInitialValue_Set @ 0x1094;
    reg {
        name="ChargePumpDigitalToAnalogConverterInitialValue_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpDigitalToAnalogConverterInitialValue_Set @ 0x1098;
    reg {
        name="LowPassFilterCalModeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterCalModeControl_Set @ 0x109c;
    reg {
        name="LowPassFilterRxModeControl1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterRxModeControl1_Set @ 0x10a0;
    reg {
        name="LowPassFilterTxModeControl1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterTxModeControl1_Set @ 0x10a4;
    reg {
        name="LowPassFilterRxModeControl2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterRxModeControl2_Set @ 0x10a8;
    reg {
        name="LowPassFilterTxModeControl2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterTxModeControl2_Set @ 0x10ac;
    reg {
        name="DsmRxModeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DsmRxModeControl_Set @ 0x10b0;
    reg {
        name="DsmTxModeControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DsmTxModeControl_Set @ 0x10b4;
    reg {
        name="SequencerInterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Set @ 0x10b8;
    reg {
        name="SequencerInterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Set @ 0x10bc;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Enable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Clr @ 0x2004;
    reg {
        name="Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Clr @ 0x2008;
    reg {
        name="Command_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Clr @ 0x200c;
    reg {
        name="Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Clr @ 0x2010;
    reg {
        name="CalibrationControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationControl_Clr @ 0x2014;
    reg {
        name="VCDACControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VCDACControl_Clr @ 0x202c;
    reg {
        name="Frequency_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Frequency_Clr @ 0x2034;
    reg {
        name="IntermediateFrequency_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequency_Clr @ 0x2038;
    reg {
        name="FrequencyDivisionControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyDivisionControl_Clr @ 0x203c;
    reg {
        name="ChannelControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelControl_Clr @ 0x2040;
    reg {
        name="ChannelSpacing_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelSpacing_Clr @ 0x2044;
    reg {
        name="CalibrationOffset_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationOffset_Clr @ 0x2048;
    reg {
        name="VoltageControlledOscillatorFrequencyTuning_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorFrequencyTuning_Clr @ 0x204c;
    reg {
        name="VoltageControlledOscillatorFrequencyRangeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorFrequencyRangeControl_Clr @ 0x2054;
    reg {
        name="VoltageControlledOscillatorGainCalibration_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorGainCalibration_Clr @ 0x2058;
    reg {
        name="ChargePumpDigitalToAnalogConverterControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpDigitalToAnalogConverterControl_Clr @ 0x2068;
    reg {
        name="CapacitorArrayCalibrationCycleCount_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CapacitorArrayCalibrationCycleCount_Clr @ 0x206c;
    reg {
        name="VoltageControlledOscillatorForceCalibrationCycleCount_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorForceCalibrationCycleCount_Clr @ 0x2070;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x2078;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x2084;
    reg {
        name="LoCounterControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterControl_Clr @ 0x2088;
    reg {
        name="LoCounterStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterStatus_Clr @ 0x208c;
    reg {
        name="LoCounterTargetValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterTargetValue_Clr @ 0x2090;
    reg {
        name="MmdDenominatorInitialValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MmdDenominatorInitialValue_Clr @ 0x2094;
    reg {
        name="ChargePumpDigitalToAnalogConverterInitialValue_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpDigitalToAnalogConverterInitialValue_Clr @ 0x2098;
    reg {
        name="LowPassFilterCalModeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterCalModeControl_Clr @ 0x209c;
    reg {
        name="LowPassFilterRxModeControl1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterRxModeControl1_Clr @ 0x20a0;
    reg {
        name="LowPassFilterTxModeControl1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterTxModeControl1_Clr @ 0x20a4;
    reg {
        name="LowPassFilterRxModeControl2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterRxModeControl2_Clr @ 0x20a8;
    reg {
        name="LowPassFilterTxModeControl2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterTxModeControl2_Clr @ 0x20ac;
    reg {
        name="DsmRxModeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DsmRxModeControl_Clr @ 0x20b0;
    reg {
        name="DsmTxModeControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DsmTxModeControl_Clr @ 0x20b4;
    reg {
        name="SequencerInterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Clr @ 0x20b8;
    reg {
        name="SequencerInterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Clr @ 0x20bc;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Enable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Enable_Tgl @ 0x3004;
    reg {
        name="Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Tgl @ 0x3008;
    reg {
        name="Command_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command_Tgl @ 0x300c;
    reg {
        name="Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control_Tgl @ 0x3010;
    reg {
        name="CalibrationControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationControl_Tgl @ 0x3014;
    reg {
        name="VCDACControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VCDACControl_Tgl @ 0x302c;
    reg {
        name="Frequency_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Frequency_Tgl @ 0x3034;
    reg {
        name="IntermediateFrequency_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequency_Tgl @ 0x3038;
    reg {
        name="FrequencyDivisionControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyDivisionControl_Tgl @ 0x303c;
    reg {
        name="ChannelControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelControl_Tgl @ 0x3040;
    reg {
        name="ChannelSpacing_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelSpacing_Tgl @ 0x3044;
    reg {
        name="CalibrationOffset_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationOffset_Tgl @ 0x3048;
    reg {
        name="VoltageControlledOscillatorFrequencyTuning_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorFrequencyTuning_Tgl @ 0x304c;
    reg {
        name="VoltageControlledOscillatorFrequencyRangeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorFrequencyRangeControl_Tgl @ 0x3054;
    reg {
        name="VoltageControlledOscillatorGainCalibration_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorGainCalibration_Tgl @ 0x3058;
    reg {
        name="ChargePumpDigitalToAnalogConverterControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpDigitalToAnalogConverterControl_Tgl @ 0x3068;
    reg {
        name="CapacitorArrayCalibrationCycleCount_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CapacitorArrayCalibrationCycleCount_Tgl @ 0x306c;
    reg {
        name="VoltageControlledOscillatorForceCalibrationCycleCount_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } VoltageControlledOscillatorForceCalibrationCycleCount_Tgl @ 0x3070;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x3078;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x3084;
    reg {
        name="LoCounterControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterControl_Tgl @ 0x3088;
    reg {
        name="LoCounterStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterStatus_Tgl @ 0x308c;
    reg {
        name="LoCounterTargetValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LoCounterTargetValue_Tgl @ 0x3090;
    reg {
        name="MmdDenominatorInitialValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MmdDenominatorInitialValue_Tgl @ 0x3094;
    reg {
        name="ChargePumpDigitalToAnalogConverterInitialValue_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChargePumpDigitalToAnalogConverterInitialValue_Tgl @ 0x3098;
    reg {
        name="LowPassFilterCalModeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterCalModeControl_Tgl @ 0x309c;
    reg {
        name="LowPassFilterRxModeControl1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterRxModeControl1_Tgl @ 0x30a0;
    reg {
        name="LowPassFilterTxModeControl1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterTxModeControl1_Tgl @ 0x30a4;
    reg {
        name="LowPassFilterRxModeControl2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterRxModeControl2_Tgl @ 0x30a8;
    reg {
        name="LowPassFilterTxModeControl2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowPassFilterTxModeControl2_Tgl @ 0x30ac;
    reg {
        name="DsmRxModeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DsmRxModeControl_Tgl @ 0x30b0;
    reg {
        name="DsmTxModeControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DsmTxModeControl_Tgl @ 0x30b4;
    reg {
        name="SequencerInterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptFlags_Tgl @ 0x30b8;
    reg {
        name="SequencerInterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SequencerInterruptEnable_Tgl @ 0x30bc;
} SynthesizerRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="MessagePointer0";
        regwidth=0x20;
            field {
                sw = rw;
            } MSGPTR0[31:0];
    } MessagePointer0 @ 0x0;
    reg {
        name="MessagePointer1";
        regwidth=0x20;
            field {
                sw = rw;
            } MSGPTR1[31:0];
    } MessagePointer1 @ 0x4;
    reg {
        name="MessagePointer2";
        regwidth=0x20;
            field {
                sw = rw;
            } MSGPTR2[31:0];
    } MessagePointer2 @ 0x8;
    reg {
        name="MessagePointer3";
        regwidth=0x20;
            field {
                sw = rw;
            } MSGPTR3[31:0];
    } MessagePointer3 @ 0xc;
    reg {
        name="InterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } MBOXIF0[0:0];
            field {
                sw = rw;
            } MBOXIF1[1:1];
            field {
                sw = rw;
            } MBOXIF2[2:2];
            field {
                sw = rw;
            } MBOXIF3[3:3];
    } InterruptFlags @ 0x40;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
        `ifdef VARIANT0
            field {
                sw = rw;
            } MBOXIEN0[0:0];
            field {
                sw = rw;
            } MBOXIEN1[1:1];
            field {
                sw = rw;
            } MBOXIEN2[2:2];
            field {
                sw = rw;
            } MBOXIEN3[3:3];
        `elsif VARIANT5
            /* Conversion error: Field "MBOXIEN0_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
            } MBOXIEN0_[0:0];
            */
            /* Conversion error: Field "MBOXIEN1_" overlaps another field at the same offset (0x1) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
            } MBOXIEN1_[1:1];
            */
            /* Conversion error: Field "MBOXIEN2_" overlaps another field at the same offset (0x2) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
            } MBOXIEN2_[2:2];
            */
            /* Conversion error: Field "MBOXIEN3_" overlaps another field at the same offset (0x3) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
            } MBOXIEN3_[3:3];
            */
        `endif

    } InterruptEnable @ 0x44;
    reg {
        name="MessagePointer0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer0_Set @ 0x1000;
    reg {
        name="MessagePointer1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer1_Set @ 0x1004;
    reg {
        name="MessagePointer2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer2_Set @ 0x1008;
    reg {
        name="MessagePointer3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer3_Set @ 0x100c;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x1040;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x1044;
    reg {
        name="MessagePointer0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer0_Clr @ 0x2000;
    reg {
        name="MessagePointer1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer1_Clr @ 0x2004;
    reg {
        name="MessagePointer2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer2_Clr @ 0x2008;
    reg {
        name="MessagePointer3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer3_Clr @ 0x200c;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x2040;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x2044;
    reg {
        name="MessagePointer0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer0_Tgl @ 0x3000;
    reg {
        name="MessagePointer1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer1_Tgl @ 0x3004;
    reg {
        name="MessagePointer2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer2_Tgl @ 0x3008;
    reg {
        name="MessagePointer3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer3_Tgl @ 0x300c;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x3040;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x3044;
} HostMailboxRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="MessagePointer0";
        regwidth=0x20;
            field {
                sw = rw;
            } MSGPTR0[31:0];
    } MessagePointer0 @ 0x0;
    reg {
        name="MessagePointer1";
        regwidth=0x20;
            field {
                sw = rw;
            } MSGPTR1[31:0];
    } MessagePointer1 @ 0x4;
    reg {
        name="MessagePointer2";
        regwidth=0x20;
            field {
                sw = rw;
            } MSGPTR2[31:0];
    } MessagePointer2 @ 0x8;
    reg {
        name="MessagePointer3";
        regwidth=0x20;
            field {
                sw = rw;
            } MSGPTR3[31:0];
    } MessagePointer3 @ 0xc;
    reg {
        name="InterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } MBOXIF0[0:0];
            field {
                sw = rw;
            } MBOXIF1[1:1];
            field {
                sw = rw;
            } MBOXIF2[2:2];
            field {
                sw = rw;
            } MBOXIF3[3:3];
    } InterruptFlags @ 0x40;
    reg {
        name="InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable @ 0x44;
    reg {
        name="MessagePointer0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer0_Set @ 0x1000;
    reg {
        name="MessagePointer1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer1_Set @ 0x1004;
    reg {
        name="MessagePointer2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer2_Set @ 0x1008;
    reg {
        name="MessagePointer3_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer3_Set @ 0x100c;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x1040;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x1044;
    reg {
        name="MessagePointer0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer0_Clr @ 0x2000;
    reg {
        name="MessagePointer1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer1_Clr @ 0x2004;
    reg {
        name="MessagePointer2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer2_Clr @ 0x2008;
    reg {
        name="MessagePointer3_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer3_Clr @ 0x200c;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x2040;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x2044;
    reg {
        name="MessagePointer0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer0_Tgl @ 0x3000;
    reg {
        name="MessagePointer1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer1_Tgl @ 0x3004;
    reg {
        name="MessagePointer2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer2_Tgl @ 0x3008;
    reg {
        name="MessagePointer3_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MessagePointer3_Tgl @ 0x300c;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x3040;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x3044;
} RadioMailboxRegisters_addrmap;


};