addrmap CC1200 {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="GPIO3Pin";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO3_ATRAN[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO3_INV[6:6];
            field {
                sw = rw;
                reset=6'b110;
            } No_name_1[5:0];
    } GPIO3Pin @ 0x0;
    reg {
        name="GPIO2Pin";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO2_ATRAN[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO2_INV[6:6];
            field {
                sw = rw;
                reset=6'b111;
            } No_name_2[5:0];
    } GPIO2Pin @ 0x1;
    reg {
        name="GPIO1Pin";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO1_ATRAN[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO1_INV[6:6];
            field {
                sw = rw;
                reset=6'b110000;
            } No_name_3[5:0];
    } GPIO1Pin @ 0x2;
    reg {
        name="GPIO0Pin";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO0_ATRAN[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO0_INV[6:6];
            field {
                sw = rw;
                reset=6'b111100;
            } No_name_4[5:0];
    } GPIO0Pin @ 0x3;
    reg {
        name="Sync3Word";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b10010011;
            } No_name_5[7:0];
    } Sync3Word @ 0x4;
    reg {
        name="Sync2Word";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b1011;
            } No_name_6[7:0];
    } Sync2Word @ 0x5;
    reg {
        name="Sync1Word";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b1010001;
            } No_name_7[7:0];
    } Sync1Word @ 0x6;
    reg {
        name="Sync0Word";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b11011110;
            } No_name_8[7:0];
    } Sync0Word @ 0x7;
    reg {
        name="SyncWord1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWord1 @ 0x8;
    reg {
        name="SyncWord0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SyncWord0 @ 0x9;
    reg {
        name="FrequencyDeviation";
        regwidth=0x8;
            field {
                sw = rw;
                reset=8'b110;
            } No_name_9[7:0];
    } FrequencyDeviation @ 0xa;
    reg {
        name="ModulationFormatAndFrequencyDeviation";
        regwidth=0x8;
            field {
                sw = rw;
                reset=3'b11;
            } DEV_E[2:0];
            field {
                sw = rw;
            } MOD_FORMAT[5:3];
            field {
                sw = rw;
            } MODEM_MODE[7:6];
    } ModulationFormatAndFrequencyDeviation @ 0xb;
    reg {
        name="DigitalDCRemoval";
        regwidth=0x8;
            field {
                sw = rw;
                reset=3'b100;
            } DCFILT_BW[2:0];
            field {
                sw = rw;
                reset=3'b1;
            } DCFILT_BW_SETTLE[5:3];
            field {
                sw = rw;
                reset=1'b1;
            } DCFILT_FREEZE_COEFF[6:6];
    } DigitalDCRemoval @ 0xc;
    reg {
        name="Preamble1";
        regwidth=0x8;
            field {
                sw = rw;
            } PREAMBLE_WORD[1:0];
            field {
                sw = rw;
                reset=4'b101;
            } NUM_PREAMBLE[5:2];
    } Preamble1 @ 0xd;
    reg {
        name="Preamble0";
        regwidth=0x8;
            field {
                sw = rw;
                reset=4'b1010;
            } PQT[3:0];
            field {
                sw = rw;
                reset=3'b101;
            } PQT_VALID_TIMEOUT[6:4];
            field {
                sw = rw;
                reset=1'b1;
            } PQT_EN[7:7];
    } Preamble0 @ 0xe;
    reg {
        name="DigitalImageChannelCompensation";
        regwidth=0x8;
            field {
                sw = rw;
            } IQIC_IMGCH_LEVEL_THR[1:0];
            field {
                sw = rw;
                reset=2'b1;
            } IQIC_BLEN[3:2];
            field {
                sw = rw;
            } IQIC_BLEN_SETTLE[5:4];
            field {
                sw = rw;
                reset=1'b1;
            } IQIC_UPDATE_COEFF_EN[6:6];
            field {
                sw = rw;
                reset=1'b1;
            } IQIC_EN[7:7];
    } DigitalImageChannelCompensation @ 0xf;
    reg {
        name="ChannelFilter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilter @ 0x10;
    reg {
        name="GeneralModemParameter1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GeneralModemParameter1 @ 0x11;
    reg {
        name="GeneralModemParameter0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GeneralModemParameter0 @ 0x12;
    reg {
        name="SymbolRate2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SymbolRate2 @ 0x13;
    reg {
        name="SymbolRate1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SymbolRate1 @ 0x14;
    reg {
        name="SymbolRate0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SymbolRate0 @ 0x15;
    reg {
        name="AGCReferenceLevel";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AGCReferenceLevel @ 0x16;
    reg {
        name="CarrierSenseThreshold";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CarrierSenseThreshold @ 0x17;
    reg {
        name="RSSIOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RSSIOffset @ 0x18;
    reg {
        name="AutomaticGainControl3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControl3 @ 0x19;
    reg {
        name="AutomaticGainControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControl2 @ 0x1a;
    reg {
        name="AutomaticGainControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControl1 @ 0x1b;
    reg {
        name="AutomaticGainControl0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControl0 @ 0x1c;
    reg {
        name="FIFOConfiguration";
        regwidth=0x8;
            field {
                sw = rw;
            } FIFO_THR[6:0];
            field {
                sw = rw;
                reset=1'b1;
            } CRC_AUTOFLUSH[7:7];
    } FIFOConfiguration @ 0x1d;
    reg {
        name="DeviceAddress";
        regwidth=0x8;
            field {
                sw = rw;
            } DEV_ADDR[7:0];
    } DeviceAddress @ 0x1e;
    reg {
        name="FrequencySynthesizerCalibrationAndSettling";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerCalibrationAndSettling @ 0x1f;
    reg {
        name="FrequencySynthesizerConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerConfiguration @ 0x20;
    reg {
        name="EWORConfiguration1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EWORConfiguration1 @ 0x21;
    reg {
        name="EWORConfiguration0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EWORConfiguration0 @ 0x22;
    reg {
        name="Event0MSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Event0MSB @ 0x23;
    reg {
        name="Event0LSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Event0LSB @ 0x24;
    reg {
        name="RXDutyCycleMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RXDutyCycleMode @ 0x25;
    reg {
        name="PacketConfiguration2";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PKT_FORMAT[1:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=3'b1;
            } CCA_MODE[4:2];
            field {
                sw = rw;
            } FG_MODE_EN[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BYTE_SWAP_EN[6:6];
    } PacketConfiguration2 @ 0x26;
    reg {
        name="PacketConfiguration1";
        regwidth=0x8;
            field {
                sw = rw;
                reset=1'b1;
            } No_name_10[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
                reset=2'b1;
            } CRC_CFG[2:1];
            field {
                sw = rw;
            } ADDR_CHECK_CFG[4:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PN9_SWAP_EN[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WHITE_DATA[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FEC_EN[7:7];
    } PacketConfiguration1 @ 0x27;
    reg {
        name="PacketConfiguration0";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } UART_SWAP_EN[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } UART_MODE_EN[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PKT_BIT_LEN[4:2];
            field {
                sw = rw;
            } LENGTH_CONFIG[6:5];
    } PacketConfiguration0 @ 0x28;
    reg {
        name="RFENDConfiguration1";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RX_TIME_QUAL[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RX_TIME[3:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } RXOFF_MODE[5:4];
    } RFENDConfiguration1 @ 0x29;
    reg {
        name="RFENDConfiguration0";
        regwidth=0x8;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } ANT_DIV_RX_TERM_CFG[2:0];
            field {
                sw = rw;
            } TERM_ON_BAD_PACKET_EN[3:3];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } TXOFF_MODE[5:4];
    } RFENDConfiguration0 @ 0x2a;
    reg {
        name="PowerAmplifier1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifier1 @ 0x2b;
    reg {
        name="PowerAmplifier0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifier0 @ 0x2c;
    reg {
        name="ASKConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ASKConfiguration @ 0x2d;
    reg {
        name="PacketLength";
        regwidth=0x8;
            field {
                sw = rw;
            } PACKET_LENGTH[7:0];
    } PacketLength @ 0x2e;
    reg {
        name="ExtendedAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExtendedAddress @ 0x2f;
    reg {
        name="SRES";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SRES @ 0x30;
    reg {
        name="SFSTXON";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SFSTXON @ 0x31;
    reg {
        name="SXOFF";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SXOFF @ 0x32;
    reg {
        name="SCAL";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SCAL @ 0x33;
    reg {
        name="SRX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SRX @ 0x34;
    reg {
        name="STX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } STX @ 0x35;
    reg {
        name="SIDLE";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SIDLE @ 0x36;
    reg {
        name="SAFC";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SAFC @ 0x37;
    reg {
        name="SWOR";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SWOR @ 0x38;
    reg {
        name="SPWD";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SPWD @ 0x39;
    reg {
        name="SFRX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SFRX @ 0x3a;
    reg {
        name="SFTX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SFTX @ 0x3b;
    reg {
        name="SWORRST";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SWORRST @ 0x3c;
    reg {
        name="SNOP";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SNOP @ 0x3d;
} Registers_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IFMixConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IFMixConfiguration @ 0x0;
    reg {
        name="FrequencyOffsetCorrection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetCorrection @ 0x1;
    reg {
        name="TimingOffsetCorrection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TimingOffsetCorrection @ 0x2;
    reg {
        name="MARCSpare";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MARCSpare @ 0x3;
    reg {
        name="ExternalClockFrequency";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalClockFrequency @ 0x4;
    reg {
        name="GeneralModemParameter2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GeneralModemParameter2 @ 0x5;
    reg {
        name="ExternalControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalControl @ 0x6;
    reg {
        name="RCOscillatorCalibrationFine";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RCOscillatorCalibrationFine @ 0x7;
    reg {
        name="RCOscillatorCalibrationCourse";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RCOscillatorCalibrationCourse @ 0x8;
    reg {
        name="RCOscillatorCalibrationClockOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RCOscillatorCalibrationClockOffset @ 0x9;
    reg {
        name="FrequencyOffsetMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetMSB @ 0xa;
    reg {
        name="FrequencyOffsetLSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetLSB @ 0xb;
    reg {
        name="Frequency2";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_11[7:0];
    } Frequency2 @ 0xc;
    reg {
        name="Frequency1";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_12[7:0];
    } Frequency1 @ 0xd;
    reg {
        name="Frequency0";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } No_name_13[7:0];
    } Frequency0 @ 0xe;
    reg {
        name="ADCConfiguration2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ADCConfiguration2 @ 0xf;
    reg {
        name="ADCConfiguration1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ADCConfiguration1 @ 0x10;
    reg {
        name="ADCConfiguration0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ADCConfiguration0 @ 0x11;
    reg {
        name="FrequencySynthesizerDigital1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerDigital1 @ 0x12;
    reg {
        name="FrequencySynthesizerDigital0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerDigital0 @ 0x13;
    reg {
        name="FrequencySynthesizerCalibration3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerCalibration3 @ 0x14;
    reg {
        name="FrequencySynthesizerCalibration2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerCalibration2 @ 0x15;
    reg {
        name="FrequencySynthesizerCalibration1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerCalibration1 @ 0x16;
    reg {
        name="FrequencySynthesizerCalibration0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerCalibration0 @ 0x17;
    reg {
        name="FrequencySynthesizerChargePump";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerChargePump @ 0x18;
    reg {
        name="FrequencySynthesizerDivideByTwo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerDivideByTwo @ 0x19;
    reg {
        name="DigitalSynthesizerModule1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalSynthesizerModule1 @ 0x1a;
    reg {
        name="DigitalSynthesizerModule0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalSynthesizerModule0 @ 0x1b;
    reg {
        name="FrequencySynthesizerDividerChain1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerDividerChain1 @ 0x1c;
    reg {
        name="FrequencySynthesizerDividerChain0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerDividerChain0 @ 0x1d;
    reg {
        name="FrequencySynthesizerLocalBias";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerLocalBias @ 0x1e;
    reg {
        name="FrequencySynthesizerPhaseFrequencyDetector";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerPhaseFrequencyDetector @ 0x1f;
    reg {
        name="FrequencySynthesizerPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerPrescaler @ 0x20;
    reg {
        name="FrequencySynthesizerDividerRegulator";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerDividerRegulator @ 0x21;
    reg {
        name="FrequencySynthesizerSpare";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerSpare @ 0x22;
    reg {
        name="FrequencySynthesizerVoltageControlOscillator4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerVoltageControlOscillator4 @ 0x23;
    reg {
        name="FrequencySynthesizerVoltageControlOscillator3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerVoltageControlOscillator3 @ 0x24;
    reg {
        name="FrequencySynthesizerVoltageControlOscillator2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerVoltageControlOscillator2 @ 0x25;
    reg {
        name="FrequencySynthesizerVoltageControlOscillator1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerVoltageControlOscillator1 @ 0x26;
    reg {
        name="FrequencySynthesizerVoltageControlOscillator0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerVoltageControlOscillator0 @ 0x27;
    reg {
        name="GlobalBias6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GlobalBias6 @ 0x28;
    reg {
        name="GlobalBias5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GlobalBias5 @ 0x29;
    reg {
        name="GlobalBias4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GlobalBias4 @ 0x2a;
    reg {
        name="GlobalBias3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GlobalBias3 @ 0x2b;
    reg {
        name="GlobalBias2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GlobalBias2 @ 0x2c;
    reg {
        name="GlobalBias1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GlobalBias1 @ 0x2d;
    reg {
        name="GlobalBias0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GlobalBias0 @ 0x2e;
    reg {
        name="IntermediateFrequencyAmplifier";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IntermediateFrequencyAmplifier @ 0x2f;
    reg {
        name="LowNoiseAmplifier";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowNoiseAmplifier @ 0x30;
    reg {
        name="RXMixer";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RXMixer @ 0x31;
    reg {
        name="CrystalOscillator5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CrystalOscillator5 @ 0x32;
    reg {
        name="CrystalOscillator4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CrystalOscillator4 @ 0x33;
    reg {
        name="CrystalOscillator3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CrystalOscillator3 @ 0x34;
    reg {
        name="CrystalOscillator2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CrystalOscillator2 @ 0x35;
    reg {
        name="CrystalOscillator1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CrystalOscillator1 @ 0x36;
    reg {
        name="CrystalOscillator0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CrystalOscillator0 @ 0x37;
    reg {
        name="AnalogSpare";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogSpare @ 0x38;
    reg {
        name="PowerAmplifier3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifier3 @ 0x39;
    reg {
        name="EWORTimerCounterValueMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EWORTimerCounterValueMSB @ 0x64;
    reg {
        name="EWORTimerCounterValueLSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EWORTimerCounterValueLSB @ 0x65;
    reg {
        name="EWORTimerCaptureValueMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EWORTimerCaptureValueMSB @ 0x66;
    reg {
        name="EWORTimerCaptureValueLSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EWORTimerCaptureValueLSB @ 0x67;
    reg {
        name="MARCBuiltInSelfTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MARCBuiltInSelfTest @ 0x68;
    reg {
        name="DCFilterOffsetIMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCFilterOffsetIMSB @ 0x69;
    reg {
        name="DCFilterOffsetILSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCFilterOffsetILSB @ 0x6a;
    reg {
        name="DCFilterOffsetQMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCFilterOffsetQMSB @ 0x6b;
    reg {
        name="DCFilterOffsetQLSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCFilterOffsetQLSB @ 0x6c;
    reg {
        name="IQImbalanceValueIMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IQImbalanceValueIMSB @ 0x6d;
    reg {
        name="IQImbalanceValueILSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IQImbalanceValueILSB @ 0x6e;
    reg {
        name="IQImbalanceValueQMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IQImbalanceValueQMSB @ 0x6f;
    reg {
        name="IQImbalanceValueQLSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IQImbalanceValueQLSB @ 0x70;
    reg {
        name="ReceivedSignalStrengthIndicator1";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RSSI_11_4[7:0];
    } ReceivedSignalStrengthIndicator1 @ 0x71;
    reg {
        name="ReceivedSignalStrengthIndicator0";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RSSI_VALID[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } CARRIER_SENSE_VALID[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } CARRIER_SENSE[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } RSSI_3_0[6:3];
    } ReceivedSignalStrengthIndicator0 @ 0x72;
    reg {
        name="MARCState";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MARCState @ 0x73;
    reg {
        name="LinkQualityIndicator";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } LQI[6:0];
            field {
                sw = r;
            } PKT_CRC_OK[7:7];
    } LinkQualityIndicator @ 0x74;
    reg {
        name="PreambleAndSyncWordError";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PreambleAndSyncWordError @ 0x75;
    reg {
        name="DemodulatorStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DemodulatorStatus @ 0x76;
    reg {
        name="FrequencyOffsetEstimateMSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetEstimateMSB @ 0x77;
    reg {
        name="FrequencyOffsetEstimateLSB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencyOffsetEstimateLSB @ 0x78;
    reg {
        name="AutomaticGainControl3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControl3 @ 0x79;
    reg {
        name="AutomaticGainControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControl2 @ 0x7a;
    reg {
        name="AutomaticGainControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControl1 @ 0x7b;
    reg {
        name="AutomaticGainControl0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AutomaticGainControl0 @ 0x7c;
    reg {
        name="CustomFrequencyModulationRxData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CustomFrequencyModulationRxData @ 0x7d;
    reg {
        name="CustomFrequencyModulationTxData";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CustomFrequencyModulationTxData @ 0x7e;
    reg {
        name="ASKSoftDecisionOutput";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ASKSoftDecisionOutput @ 0x7f;
    reg {
        name="RandomNumberGeneratorValue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RandomNumberGeneratorValue @ 0x80;
    reg {
        name="SignalMagnitudeAfterCORDIC2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalMagnitudeAfterCORDIC2 @ 0x81;
    reg {
        name="SignalMagnitudeAfterCORDIC1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalMagnitudeAfterCORDIC1 @ 0x82;
    reg {
        name="SignalMagnitudeAfterCORDIC0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalMagnitudeAfterCORDIC0 @ 0x83;
    reg {
        name="SignalAngularAfterCORDIC1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalAngularAfterCORDIC1 @ 0x84;
    reg {
        name="SignalAngularAfterCORDIC0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SignalAngularAfterCORDIC0 @ 0x85;
    reg {
        name="ChannelFilterDataI2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterDataI2 @ 0x86;
    reg {
        name="ChannelFilterDataI1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterDataI1 @ 0x87;
    reg {
        name="ChannelFilterDataI0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterDataI0 @ 0x88;
    reg {
        name="ChannelFilterDataQ2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterDataQ2 @ 0x89;
    reg {
        name="ChannelFilterDataQ1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterDataQ1 @ 0x8a;
    reg {
        name="ChannelFilterDataQ0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelFilterDataQ0 @ 0x8b;
    reg {
        name="GPIOStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GPIOStatus @ 0x8c;
    reg {
        name="FrequencySynthesizerCalibration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerCalibration @ 0x8d;
    reg {
        name="FrequencySynthesizerPhaseAdjust";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerPhaseAdjust @ 0x8e;
    reg {
        name="PartNumber";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } No_name_14[7:0];
    } PartNumber @ 0x8f;
    reg {
        name="PartVersion";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PartVersion @ 0x90;
    reg {
        name="SerialStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SerialStatus @ 0x91;
    reg {
        name="ModemStatus1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModemStatus1 @ 0x92;
    reg {
        name="ModemStatus0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModemStatus0 @ 0x93;
    reg {
        name="MARCStatus1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MARCStatus1 @ 0x94;
    reg {
        name="MARCStatus0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MARCStatus0 @ 0x95;
    reg {
        name="PowerAmplifierIntermediateFrequencyAmplifierTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PowerAmplifierIntermediateFrequencyAmplifierTest @ 0x96;
    reg {
        name="FrequencySynthesizerTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerTest @ 0x97;
    reg {
        name="FrequencySynthesizerPrescalerTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerPrescalerTest @ 0x98;
    reg {
        name="FrequencySynthesizerPrescalerOverride";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FrequencySynthesizerPrescalerOverride @ 0x99;
    reg {
        name="AnalogToDigitalConverterTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogToDigitalConverterTest @ 0x9a;
    reg {
        name="DigitalDividerChainTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DigitalDividerChainTest @ 0x9b;
    reg {
        name="AnalogTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogTest @ 0x9c;
    reg {
        name="AnalogTestLVDS";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogTestLVDS @ 0x9d;
    reg {
        name="AnalogTestMode";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AnalogTestMode @ 0x9e;
    reg {
        name="CrystalOscillatorTest1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CrystalOscillatorTest1 @ 0x9f;
    reg {
        name="CrystalOscillatorTest0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CrystalOscillatorTest0 @ 0xa0;
    reg {
        name="AdvancedEncryptionStandardStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardStatus @ 0xa1;
    reg {
        name="ModemTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ModemTest @ 0xa2;
    reg {
        name="RxFIFOPointerFirstEntry";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxFIFOPointerFirstEntry @ 0xd2;
    reg {
        name="TxFIFOPointerFirstEntry";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxFIFOPointerFirstEntry @ 0xd3;
    reg {
        name="RxFIFOPointerLastEntry";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxFIFOPointerLastEntry @ 0xd4;
    reg {
        name="TxFIFOPointerLastEntry";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxFIFOPointerLastEntry @ 0xd5;
    reg {
        name="TxFIFONumberOfBytes";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } FIFO_TXBYTES[3:0];
    } TxFIFONumberOfBytes @ 0xd6;
    reg {
        name="RxFIFONumberOfBytes";
        regwidth=0x8;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } FIFO_RXBYTES[3:0];
    } RxFIFONumberOfBytes @ 0xd7;
    reg {
        name="TxFIFONumberOfFreeEntries";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TxFIFONumberOfFreeEntries @ 0xd8;
    reg {
        name="RxFIFONumberOfFreeEntries";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxFIFONumberOfFreeEntries @ 0xd9;
    reg {
        name="RxFIFOFirstByteWhenEmpty";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RxFIFOFirstByteWhenEmpty @ 0xda;
    reg {
        name="AdvancedEncryptionStandardKey15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey15 @ 0xe0;
    reg {
        name="AdvancedEncryptionStandardKey14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey14 @ 0xe1;
    reg {
        name="AdvancedEncryptionStandardKey13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey13 @ 0xe2;
    reg {
        name="AdvancedEncryptionStandardKey12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey12 @ 0xe3;
    reg {
        name="AdvancedEncryptionStandardKey11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey11 @ 0xe4;
    reg {
        name="AdvancedEncryptionStandardKey10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey10 @ 0xe5;
    reg {
        name="AdvancedEncryptionStandardKey9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey9 @ 0xe6;
    reg {
        name="AdvancedEncryptionStandardKey8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey8 @ 0xe7;
    reg {
        name="AdvancedEncryptionStandardKey7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey7 @ 0xe8;
    reg {
        name="AdvancedEncryptionStandardKey6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey6 @ 0xe9;
    reg {
        name="AdvancedEncryptionStandardKey5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey5 @ 0xea;
    reg {
        name="AdvancedEncryptionStandardKey4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey4 @ 0xeb;
    reg {
        name="AdvancedEncryptionStandardKey3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey3 @ 0xec;
    reg {
        name="AdvancedEncryptionStandardKey2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey2 @ 0xed;
    reg {
        name="AdvancedEncryptionStandardKey1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey1 @ 0xee;
    reg {
        name="AdvancedEncryptionStandardKey0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardKey0 @ 0xef;
    reg {
        name="AdvancedEncryptionStandardBuffer15";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer15 @ 0xf0;
    reg {
        name="AdvancedEncryptionStandardBuffer14";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer14 @ 0xf1;
    reg {
        name="AdvancedEncryptionStandardBuffer13";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer13 @ 0xf2;
    reg {
        name="AdvancedEncryptionStandardBuffer12";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer12 @ 0xf3;
    reg {
        name="AdvancedEncryptionStandardBuffer11";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer11 @ 0xf4;
    reg {
        name="AdvancedEncryptionStandardBuffer10";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer10 @ 0xf5;
    reg {
        name="AdvancedEncryptionStandardBuffer9";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer9 @ 0xf6;
    reg {
        name="AdvancedEncryptionStandardBuffer8";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer8 @ 0xf7;
    reg {
        name="AdvancedEncryptionStandardBuffer7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer7 @ 0xf8;
    reg {
        name="AdvancedEncryptionStandardBuffer6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer6 @ 0xf9;
    reg {
        name="AdvancedEncryptionStandardBuffer5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer5 @ 0xfa;
    reg {
        name="AdvancedEncryptionStandardBuffer4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer4 @ 0xfb;
    reg {
        name="AdvancedEncryptionStandardBuffer3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer3 @ 0xfc;
    reg {
        name="AdvancedEncryptionStandardBuffer2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer2 @ 0xfd;
    reg {
        name="AdvancedEncryptionStandardBuffer1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer1 @ 0xfe;
    reg {
        name="AdvancedEncryptionStandardBuffer0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AdvancedEncryptionStandardBuffer0 @ 0xff;
} ExtendedRegisters_addrmap;


};