addrmap STM32G0DMA {

/* Some conversion errors detected, this might mean that the peripheral's registers structure in this file is incomplete.
 * Please refer to logs and comments in the file for more information.
 * 
 * Field "Transfer complete flag for channel {j} (TCIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "Half transfer flag for channel {j} (HTIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "Transfer error flag for channel {j} (TEIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "Transfer complete flag clear for channel {j} (CTEIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "Half transfer flag clear for channel {j} (CHTIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "Transfer error flag clear for channel {j} (CTEIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 */

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="ChannelConfiguration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelConfiguration @ 0x8;
    reg {
        name="ChannelDataCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelDataCount @ 0xc;
    reg {
        name="ChannelPeripheralAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelPeripheralAddress @ 0x10;
    reg {
        name="ChannelMemoryAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ChannelMemoryAddress @ 0x14;
} ChannelRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="InterruptStatus";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } Global_interrupt_flag_for_channel_j_GIFj[0:0];
            /* Conversion error: Field "Transfer complete flag for channel {j} (TCIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } Transfer_complete_flag_for_channel_j_TCIFj[0:0];
            */
            /* Conversion error: Field "Half transfer flag for channel {j} (HTIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } Half_transfer_flag_for_channel_j_HTIFj[0:0];
            */
            /* Conversion error: Field "Transfer error flag for channel {j} (TEIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Transfer_error_flag_for_channel_j_TEIFj[0:0];
            */
    } InterruptStatus @ 0x0;
    reg {
        name="InterruptFlagClear";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } Global_interrupt_flag_clear_for_channel_j_CGIFj[0:0];
            /* Conversion error: Field "Transfer complete flag clear for channel {j} (CTEIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } Transfer_complete_flag_clear_for_channel_j_CTEIFj[0:0];
            */
            /* Conversion error: Field "Half transfer flag clear for channel {j} (CHTIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } Half_transfer_flag_clear_for_channel_j_CHTIFj[0:0];
            */
            /* Conversion error: Field "Transfer error flag clear for channel {j} (CTEIF{j})" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Transfer_error_flag_clear_for_channel_j_CTEIFj[0:0];
            */
    } InterruptFlagClear @ 0x4;
    reg {
        name="Channel1Configuration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel1Configuration @ 0x8;
    reg {
        name="Channel1DataCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel1DataCount @ 0xc;
    reg {
        name="Channel1PeripheralAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel1PeripheralAddress @ 0x10;
    reg {
        name="Channel1MemoryAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel1MemoryAddress @ 0x14;
    reg {
        name="Channel2Configuration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel2Configuration @ 0x1c;
    reg {
        name="Channel2DataCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel2DataCount @ 0x20;
    reg {
        name="Channel2PeripheralAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel2PeripheralAddress @ 0x24;
    reg {
        name="Channel2MemoryAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel2MemoryAddress @ 0x28;
    reg {
        name="Channel3Configuration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel3Configuration @ 0x30;
    reg {
        name="Channel3DataCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel3DataCount @ 0x34;
    reg {
        name="Channel3PeripheralAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel3PeripheralAddress @ 0x38;
    reg {
        name="Channel3MemoryAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel3MemoryAddress @ 0x3c;
    reg {
        name="Channel4Configuration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel4Configuration @ 0x44;
    reg {
        name="Channel4DataCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel4DataCount @ 0x48;
    reg {
        name="Channel4PeripheralAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel4PeripheralAddress @ 0x4c;
    reg {
        name="Channel4MemoryAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel4MemoryAddress @ 0x50;
    reg {
        name="Channel5Configuration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel5Configuration @ 0x58;
    reg {
        name="Channel5DataCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel5DataCount @ 0x5c;
    reg {
        name="Channel5PeripheralAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel5PeripheralAddress @ 0x60;
    reg {
        name="Channel5MemoryAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel5MemoryAddress @ 0x64;
    reg {
        name="Channel6Configuration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel6Configuration @ 0x6c;
    reg {
        name="Channel6DataCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel6DataCount @ 0x70;
    reg {
        name="Channel6PeripheralAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel6PeripheralAddress @ 0x74;
    reg {
        name="Channel6MemoryAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel6MemoryAddress @ 0x78;
    reg {
        name="Channel7Configuration";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel7Configuration @ 0x80;
    reg {
        name="Channel7DataCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel7DataCount @ 0x84;
    reg {
        name="Channel7PeripheralAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel7PeripheralAddress @ 0x88;
    reg {
        name="Channel7MemoryAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Channel7MemoryAddress @ 0x8c;
    reg {
        name="ChannelSelection";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_channel_7_selection_C7S[27:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_channel_6_selection_C6S[23:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_channel_5_selection_C5S[19:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_channel_4_selection_C4S[15:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_channel_3_selection_C3S[11:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_channel_2_selection_C2S[7:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DMA_channel_1_selection_C1S[3:0];
    } ChannelSelection @ 0xa8;
} Registers_addrmap;


};