addrmap EFR32xG2_GPIO_1 {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="PortAControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAControl @ 0x0;
    reg {
        name="PortAModeLow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAModeLow @ 0x4;
    reg {
        name="PortAModeHigh";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAModeHigh @ 0xc;
    reg {
        name="PortADataOut";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortADataOut @ 0x10;
    reg {
        name="PortADataIn";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortADataIn @ 0x14;
    reg {
        name="PortBControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBControl @ 0x30;
    reg {
        name="PortBModeLow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBModeLow @ 0x34;
    reg {
        name="PortBDataOut";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBDataOut @ 0x40;
    reg {
        name="PortBDataIn";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBDataIn @ 0x44;
    reg {
        name="PortBModeHigh";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBModeHigh @ 0x4c;
    reg {
        name="PortCControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCControl @ 0x60;
    reg {
        name="PortCModeLow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCModeLow @ 0x64;
    reg {
        name="PortCModeHigh";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCModeHigh @ 0x6c;
    reg {
        name="PortCDataOut";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCDataOut @ 0x70;
    reg {
        name="PortCDataIn";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCDataIn @ 0x74;
    reg {
        name="PortDControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDControl @ 0x90;
    reg {
        name="PortDModeLow";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDModeLow @ 0x94;
    reg {
        name="PortDModeHigh";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDModeHigh @ 0x9c;
    reg {
        name="PortDDataOut";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDDataOut @ 0xa0;
    reg {
        name="PortDDataIn";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDDataIn @ 0xa4;
    reg {
        name="Lock";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } LOCKKEY[15:0];
    } Lock @ 0x300;
    reg {
        name="LockStatus";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } LOCK[0:0];
    } LockStatus @ 0x310;
    reg {
        name="ABusAllocation";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ABusAllocation @ 0x320;
    reg {
        name="BBusAllocation";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BBusAllocation @ 0x324;
    reg {
        name="CDBusAllocation";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CDBusAllocation @ 0x328;
    reg {
        name="ExternalInterruptPortSelectLow";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } EXTIPSEL0[1:0];
            field {
                sw = rw;
            } EXTIPSEL1[5:4];
            field {
                sw = rw;
            } EXTIPSEL2[9:8];
            field {
                sw = rw;
            } EXTIPSEL3[13:12];
            field {
                sw = rw;
            } EXTIPSEL4[17:16];
            field {
                sw = rw;
            } EXTIPSEL5[21:20];
            field {
                sw = rw;
            } EXTIPSEL6[25:24];
            field {
                sw = rw;
            } EXTIPSEL7[29:28];
    } ExternalInterruptPortSelectLow @ 0x400;
    reg {
        name="ExternalInterruptPortSelectHigh";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } EXTIPSEL8[1:0];
            field {
                sw = rw;
            } EXTIPSEL9[5:4];
            field {
                sw = rw;
            } EXTIPSEL10[9:8];
            field {
                sw = rw;
            } EXTIPSEL11[13:12];
    } ExternalInterruptPortSelectHigh @ 0x404;
    reg {
        name="ExternalInterruptPinSelectLow";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } EXTIPINSEL0[1:0];
            field {
                sw = rw;
            } EXTIPINSEL1[5:4];
            field {
                sw = rw;
            } EXTIPINSEL2[9:8];
            field {
                sw = rw;
            } EXTIPINSEL3[13:12];
            field {
                sw = rw;
            } EXTIPINSEL4[17:16];
            field {
                sw = rw;
            } EXTIPINSEL5[21:20];
            field {
                sw = rw;
            } EXTIPINSEL6[25:24];
            field {
                sw = rw;
            } EXTIPINSEL7[29:28];
    } ExternalInterruptPinSelectLow @ 0x408;
    reg {
        name="ExternalInterruptPinSelectHigh";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
            } EXTIPINSEL8[1:0];
            field {
                sw = rw;
            } EXTIPINSEL9[5:4];
            field {
                sw = rw;
            } EXTIPINSEL10[9:8];
            field {
                sw = rw;
            } EXTIPINSEL11[13:12];
    } ExternalInterruptPinSelectHigh @ 0x40c;
    reg {
        name="ExternalInterruptRisingEdgeTrigger";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } EXTIRISE[11:0];
    } ExternalInterruptRisingEdgeTrigger @ 0x410;
    reg {
        name="ExternalInterruptFallingEdgeTrigger";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } EXTIFALL[11:0];
    } ExternalInterruptFallingEdgeTrigger @ 0x414;
    reg {
        name="InterruptFlag";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
            } EXTIF0[0:0];
            field {
                sw = rw;
            } EXTIF1[1:1];
            field {
                sw = rw;
            } EXTIF2[2:2];
            field {
                sw = rw;
            } EXTIF3[3:3];
            field {
                sw = rw;
            } EXTIF4[4:4];
            field {
                sw = rw;
            } EXTIF5[5:5];
            field {
                sw = rw;
            } EXTIF6[6:6];
            field {
                sw = rw;
            } EXTIF7[7:7];
            field {
                sw = rw;
            } EXTIF8[8:8];
            field {
                sw = rw;
            } EXTIF9[9:9];
            field {
                sw = rw;
            } EXTIF10[10:10];
            field {
                sw = rw;
            } EXTIF11[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF0[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF1[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF2[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF3[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF4[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF5[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF6[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF7[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF8[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF9[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF10[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIF11[27:27];
    } InterruptFlag @ 0x420;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = rw;
            } EXTIEN0[0:0];
            field {
                sw = rw;
            } EXTIEN1[1:1];
            field {
                sw = rw;
            } EXTIEN2[2:2];
            field {
                sw = rw;
            } EXTIEN3[3:3];
            field {
                sw = rw;
            } EXTIEN4[4:4];
            field {
                sw = rw;
            } EXTIEN5[5:5];
            field {
                sw = rw;
            } EXTIEN6[6:6];
            field {
                sw = rw;
            } EXTIEN7[7:7];
            field {
                sw = rw;
            } EXTIEN8[8:8];
            field {
                sw = rw;
            } EXTIEN9[9:9];
            field {
                sw = rw;
            } EXTIEN10[10:10];
            field {
                sw = rw;
            } EXTIEN11[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN0[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN1[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN2[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN3[19:19];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN4[20:20];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN5[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN6[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN7[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN8[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN9[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN10[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EM4WUIEN11[27:27];
    } InterruptEnable @ 0x424;
    reg {
        name="EM4WakeUpEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EM4WakeUpEnable @ 0x42c;
    reg {
        name="EM4WakeUpPolarity";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EM4WakeUpPolarity @ 0x430;
    reg {
        name="DebugRoutePinEn";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DebugRoutePinEn @ 0x440;
    reg {
        name="TraceRoutePinEn";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TraceRoutePinEn @ 0x444;
    reg {
        name="CMU_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_RouteEnable @ 0x450;
    reg {
        name="CMU_CLKIN0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKIN0_Route @ 0x454;
    reg {
        name="CMU_CLKOUT0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT0_Route @ 0x458;
    reg {
        name="CMU_CLKOUT1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT1_Route @ 0x45c;
    reg {
        name="CMU_CLKOUT2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT2_Route @ 0x460;
    reg {
        name="DCDC_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCDC_RouteEnable @ 0x46c;
    reg {
        name="FRC_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_RouteEnable @ 0x47c;
    reg {
        name="FRC_DCLK_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DCLK_Route @ 0x480;
    reg {
        name="FRC_DFRAME_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DFRAME_Route @ 0x484;
    reg {
        name="FRC_DOUT_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DOUT_Route @ 0x488;
    reg {
        name="I2C0_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_RouteEnable @ 0x490;
    reg {
        name="I2C0_SCL_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_SCL_Route @ 0x494;
    reg {
        name="I2C0_SDA_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_SDA_Route @ 0x498;
    reg {
        name="I2C1_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_RouteEnable @ 0x4a0;
    reg {
        name="I2C1_SCL_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_SCL_Route @ 0x4a4;
    reg {
        name="I2C1_SDA_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_SDA_Route @ 0x4a8;
    reg {
        name="LETIMER_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_RouteEnable @ 0x4b0;
    reg {
        name="LETIMER_OUT0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_OUT0_Route @ 0x4b4;
    reg {
        name="LETIMER_OUT1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_OUT1_Route @ 0x4b8;
    reg {
        name="ESART0_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RouteEnable @ 0x4c0;
    reg {
        name="ESART0_CS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_CS_Route @ 0x4c4;
    reg {
        name="ESART0_CTS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_CTS_Route @ 0x4c8;
    reg {
        name="ESART0_RTS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RTS_Route @ 0x4cc;
    reg {
        name="ESART0_RX_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RX_Route @ 0x4d0;
    reg {
        name="MODEM_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_RouteEnable @ 0x4d8;
    reg {
        name="MODEM_ANT0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANT0_Route @ 0x4dc;
    reg {
        name="MODEM_ANT1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANT1_Route @ 0x4e0;
    reg {
        name="MODEM_ANTROLLOVER_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTROLLOVER_Route @ 0x4e4;
    reg {
        name="MODEM_ANTRR0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR0_Route @ 0x4e8;
    reg {
        name="MODEM_ANTRR1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR1_Route @ 0x4ec;
    reg {
        name="MODEM_ANTRR2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR2_Route @ 0x4f0;
    reg {
        name="MODEM_ANTRR3_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR3_Route @ 0x4f4;
    reg {
        name="MODEM_ANTRR4_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR4_Route @ 0x4f8;
    reg {
        name="MODEM_ANTRR5_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR5_Route @ 0x4fc;
    reg {
        name="MODEM_ANTSWEN_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTSWEN_Route @ 0x500;
    reg {
        name="MODEM_ANTSWUS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTSWUS_Route @ 0x504;
    reg {
        name="MODEM_ANTTRIG_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTTRIG_Route @ 0x508;
    reg {
        name="MODEM_ANTTRIGSTOP_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTTRIGSTOP_Route @ 0x50c;
    reg {
        name="MODEM_DCLK_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DCLK_Route @ 0x510;
    reg {
        name="MODEM_DIN_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DIN_Route @ 0x514;
    reg {
        name="MODEM_DOUT_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DOUT_Route @ 0x518;
    reg {
        name="PDM_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_RouteEnable @ 0x520;
    reg {
        name="PDM_CLK_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_CLK_Route @ 0x524;
    reg {
        name="PDM_DAT0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_DAT0_Route @ 0x528;
    reg {
        name="PDM_DAT1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_DAT1_Route @ 0x52c;
    reg {
        name="PRS0_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_RouteEnable @ 0x534;
    reg {
        name="PRS0_ASYNCH0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH0_Route @ 0x538;
    reg {
        name="PRS0_ASYNCH1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH1_Route @ 0x53c;
    reg {
        name="PRS0_ASYNCH2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH2_Route @ 0x540;
    reg {
        name="PRS0_ASYNCH3_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH3_Route @ 0x544;
    reg {
        name="PRS0_ASYNCH4_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH4_Route @ 0x548;
    reg {
        name="PRS0_ASYNCH5_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH5_Route @ 0x54c;
    reg {
        name="PRS0_ASYNCH6_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH6_Route @ 0x550;
    reg {
        name="PRS0_ASYNCH7_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH7_Route @ 0x554;
    reg {
        name="PRS0_ASYNCH8_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH8_Route @ 0x558;
    reg {
        name="PRS0_ASYNCH9_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH9_Route @ 0x55c;
    reg {
        name="PRS0_ASYNCH10_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH10_Route @ 0x560;
    reg {
        name="PRS0_ASYNCH11_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH11_Route @ 0x564;
    reg {
        name="PRS0_SYNCH0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH0_Route @ 0x568;
    reg {
        name="PRS0_SYNCH1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH1_Route @ 0x56c;
    reg {
        name="PRS0_SYNCH2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH2_Route @ 0x570;
    reg {
        name="PRS0_SYNCH3_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH3_Route @ 0x574;
    reg {
        name="TIMER0_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_RouteEnable @ 0x57c;
    reg {
        name="TIMER0_CC0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC0_Route @ 0x580;
    reg {
        name="TIMER0_CC1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC1_Route @ 0x584;
    reg {
        name="TIMER0_CC2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC2_Route @ 0x588;
    reg {
        name="TIMER0_CDTI0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI0_Route @ 0x58c;
    reg {
        name="TIMER0_CDTI1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI1_Route @ 0x590;
    reg {
        name="TIMER0_CDTI2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI2_Route @ 0x594;
    reg {
        name="TIMER1_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_RouteEnable @ 0x59c;
    reg {
        name="TIMER1_CC0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC0_Route @ 0x5a0;
    reg {
        name="TIMER1_CC1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC1_Route @ 0x5a4;
    reg {
        name="TIMER1_CC2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC2_Route @ 0x5a8;
    reg {
        name="TIMER1_CDTI0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI0_Route @ 0x5ac;
    reg {
        name="TIMER1_CDTI1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI1_Route @ 0x5b0;
    reg {
        name="TIMER1_CDTI2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI2_Route @ 0x5b4;
    reg {
        name="TIMER2_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_RouteEnable @ 0x5bc;
    reg {
        name="TIMER2_CC0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC0_Route @ 0x5c0;
    reg {
        name="TIMER2_CC1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC1_Route @ 0x5c4;
    reg {
        name="TIMER2_CC2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC2_Route @ 0x5c8;
    reg {
        name="TIMER2_CDTI0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI0_Route @ 0x5cc;
    reg {
        name="TIMER2_CDTI1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI1_Route @ 0x5d0;
    reg {
        name="TIMER2_CDTI2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI2_Route @ 0x5d4;
    reg {
        name="TIMER3_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_RouteEnable @ 0x5dc;
    reg {
        name="TIMER3_CC0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC0_Route @ 0x5e0;
    reg {
        name="TIMER3_CC1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC1_Route @ 0x5e4;
    reg {
        name="TIMER3_CC2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC2_Route @ 0x5e8;
    reg {
        name="TIMER3_CDTI0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI0_Route @ 0x5ec;
    reg {
        name="TIMER3_CDTI1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI1_Route @ 0x5f0;
    reg {
        name="TIMER3_CDTI2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI2_Route @ 0x5f4;
    reg {
        name="TIMER4_RouteEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_RouteEnable @ 0x5fc;
    reg {
        name="TIMER4_CC0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC0_Route @ 0x600;
    reg {
        name="TIMER4_CC1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC1_Route @ 0x604;
    reg {
        name="TIMER4_CC2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC2_Route @ 0x608;
    reg {
        name="TIMER4_CDTI0_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI0_Route @ 0x60c;
    reg {
        name="TIMER4_CDTI1_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI1_Route @ 0x610;
    reg {
        name="TIMER4_CDTI2_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI2_Route @ 0x614;
    reg {
        name="USART0_RouteEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } CSPEN[0:0];
            field {
                sw = rw;
            } RTSPEN[1:1];
            field {
                sw = rw;
            } RXPEN[2:2];
            field {
                sw = rw;
            } SCLKPEN[3:3];
            field {
                sw = rw;
            } TXPEN[4:4];
    } USART0_RouteEnable @ 0x61c;
    reg {
        name="USART0_CS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CS_Route @ 0x620;
    reg {
        name="USART0_CTS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CTS_Route @ 0x624;
    reg {
        name="USART0_RTS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RTS_Route @ 0x628;
    reg {
        name="USART0_RX_Route";
        regwidth=0x20;
            field {
                sw = rw;
            } PORT[1:0];
            field {
                sw = rw;
            } PIN[19:16];
    } USART0_RX_Route @ 0x62c;
    reg {
        name="USART0_CLK_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CLK_Route @ 0x630;
    reg {
        name="USART0_TX_Route";
        regwidth=0x20;
            field {
                sw = rw;
            } PORT[1:0];
            field {
                sw = rw;
            } PIN[19:16];
    } USART0_TX_Route @ 0x634;
    reg {
        name="USART1_RouteEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } CSPEN[0:0];
            field {
                sw = rw;
            } RTSPEN[1:1];
            field {
                sw = rw;
            } RXPEN[2:2];
            field {
                sw = rw;
            } SCLKPEN[3:3];
            field {
                sw = rw;
            } TXPEN[4:4];
    } USART1_RouteEnable @ 0x63c;
    reg {
        name="USART1_CS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CS_Route @ 0x640;
    reg {
        name="USART1_CTS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CTS_Route @ 0x644;
    reg {
        name="USART1_RTS_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RTS_Route @ 0x648;
    reg {
        name="USART1_RX_Route";
        regwidth=0x20;
            field {
                sw = rw;
            } PORT[1:0];
            field {
                sw = rw;
            } PIN[19:16];
    } USART1_RX_Route @ 0x64c;
    reg {
        name="USART1_CLK_Route";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CLK_Route @ 0x650;
    reg {
        name="USART1_TX_Route";
        regwidth=0x20;
            field {
                sw = rw;
            } PORT[1:0];
            field {
                sw = rw;
            } PIN[19:16];
    } USART1_TX_Route @ 0x654;
    reg {
        name="PortAControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAControl_Set @ 0x1000;
    reg {
        name="PortAModeLow_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAModeLow_Set @ 0x1004;
    reg {
        name="PortAModeHigh_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAModeHigh_Set @ 0x100c;
    reg {
        name="PortADataOut_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortADataOut_Set @ 0x1010;
    reg {
        name="PortADataIn_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortADataIn_Set @ 0x1014;
    reg {
        name="PortBControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBControl_Set @ 0x1030;
    reg {
        name="PortBModeLow_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBModeLow_Set @ 0x1034;
    reg {
        name="PortBDataOut_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBDataOut_Set @ 0x1040;
    reg {
        name="PortBDataIn_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBDataIn_Set @ 0x1044;
    reg {
        name="PortBModeHigh_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBModeHigh_Set @ 0x104c;
    reg {
        name="PortCControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCControl_Set @ 0x1060;
    reg {
        name="PortCModeLow_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCModeLow_Set @ 0x1064;
    reg {
        name="PortCModeHigh_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCModeHigh_Set @ 0x106c;
    reg {
        name="PortCDataOut_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCDataOut_Set @ 0x1070;
    reg {
        name="PortCDataIn_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCDataIn_Set @ 0x1074;
    reg {
        name="PortDControl_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDControl_Set @ 0x1090;
    reg {
        name="PortDModeLow_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDModeLow_Set @ 0x1094;
    reg {
        name="PortDModeHigh_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDModeHigh_Set @ 0x109c;
    reg {
        name="PortDDataOut_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDDataOut_Set @ 0x10a0;
    reg {
        name="PortDDataIn_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDDataIn_Set @ 0x10a4;
    reg {
        name="Lock_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_Set @ 0x1300;
    reg {
        name="LockStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LockStatus_Set @ 0x1310;
    reg {
        name="ABusAllocation_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ABusAllocation_Set @ 0x1320;
    reg {
        name="BBusAllocation_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BBusAllocation_Set @ 0x1324;
    reg {
        name="CDBusAllocation_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CDBusAllocation_Set @ 0x1328;
    reg {
        name="ExternalInterruptPortSelectLow_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPortSelectLow_Set @ 0x1400;
    reg {
        name="ExternalInterruptPortSelectHigh_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPortSelectHigh_Set @ 0x1404;
    reg {
        name="ExternalInterruptPinSelectLow_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPinSelectLow_Set @ 0x1408;
    reg {
        name="ExternalInterruptPinSelectHigh_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPinSelectHigh_Set @ 0x140c;
    reg {
        name="ExternalInterruptRisingEdgeTrigger_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptRisingEdgeTrigger_Set @ 0x1410;
    reg {
        name="ExternalInterruptFallingEdgeTrigger_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptFallingEdgeTrigger_Set @ 0x1414;
    reg {
        name="InterruptFlag_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlag_Set @ 0x1420;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x1424;
    reg {
        name="EM4WakeUpEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EM4WakeUpEnable_Set @ 0x142c;
    reg {
        name="EM4WakeUpPolarity_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EM4WakeUpPolarity_Set @ 0x1430;
    reg {
        name="DebugRoutePinEn_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DebugRoutePinEn_Set @ 0x1440;
    reg {
        name="TraceRoutePinEn_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TraceRoutePinEn_Set @ 0x1444;
    reg {
        name="CMU_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_RouteEnable_Set @ 0x1450;
    reg {
        name="CMU_CLKIN0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKIN0_Route_Set @ 0x1454;
    reg {
        name="CMU_CLKOUT0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT0_Route_Set @ 0x1458;
    reg {
        name="CMU_CLKOUT1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT1_Route_Set @ 0x145c;
    reg {
        name="CMU_CLKOUT2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT2_Route_Set @ 0x1460;
    reg {
        name="DCDC_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCDC_RouteEnable_Set @ 0x146c;
    reg {
        name="FRC_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_RouteEnable_Set @ 0x147c;
    reg {
        name="FRC_DCLK_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DCLK_Route_Set @ 0x1480;
    reg {
        name="FRC_DFRAME_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DFRAME_Route_Set @ 0x1484;
    reg {
        name="FRC_DOUT_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DOUT_Route_Set @ 0x1488;
    reg {
        name="I2C0_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_RouteEnable_Set @ 0x1490;
    reg {
        name="I2C0_SCL_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_SCL_Route_Set @ 0x1494;
    reg {
        name="I2C0_SDA_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_SDA_Route_Set @ 0x1498;
    reg {
        name="I2C1_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_RouteEnable_Set @ 0x14a0;
    reg {
        name="I2C1_SCL_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_SCL_Route_Set @ 0x14a4;
    reg {
        name="I2C1_SDA_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_SDA_Route_Set @ 0x14a8;
    reg {
        name="LETIMER_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_RouteEnable_Set @ 0x14b0;
    reg {
        name="LETIMER_OUT0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_OUT0_Route_Set @ 0x14b4;
    reg {
        name="LETIMER_OUT1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_OUT1_Route_Set @ 0x14b8;
    reg {
        name="ESART0_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RouteEnable_Set @ 0x14c0;
    reg {
        name="ESART0_CS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_CS_Route_Set @ 0x14c4;
    reg {
        name="ESART0_CTS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_CTS_Route_Set @ 0x14c8;
    reg {
        name="ESART0_RTS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RTS_Route_Set @ 0x14cc;
    reg {
        name="ESART0_RX_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RX_Route_Set @ 0x14d0;
    reg {
        name="MODEM_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_RouteEnable_Set @ 0x14d8;
    reg {
        name="MODEM_ANT0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANT0_Route_Set @ 0x14dc;
    reg {
        name="MODEM_ANT1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANT1_Route_Set @ 0x14e0;
    reg {
        name="MODEM_ANTROLLOVER_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTROLLOVER_Route_Set @ 0x14e4;
    reg {
        name="MODEM_ANTRR0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR0_Route_Set @ 0x14e8;
    reg {
        name="MODEM_ANTRR1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR1_Route_Set @ 0x14ec;
    reg {
        name="MODEM_ANTRR2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR2_Route_Set @ 0x14f0;
    reg {
        name="MODEM_ANTRR3_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR3_Route_Set @ 0x14f4;
    reg {
        name="MODEM_ANTRR4_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR4_Route_Set @ 0x14f8;
    reg {
        name="MODEM_ANTRR5_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR5_Route_Set @ 0x14fc;
    reg {
        name="MODEM_ANTSWEN_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTSWEN_Route_Set @ 0x1500;
    reg {
        name="MODEM_ANTSWUS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTSWUS_Route_Set @ 0x1504;
    reg {
        name="MODEM_ANTTRIG_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTTRIG_Route_Set @ 0x1508;
    reg {
        name="MODEM_ANTTRIGSTOP_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTTRIGSTOP_Route_Set @ 0x150c;
    reg {
        name="MODEM_DCLK_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DCLK_Route_Set @ 0x1510;
    reg {
        name="MODEM_DIN_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DIN_Route_Set @ 0x1514;
    reg {
        name="MODEM_DOUT_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DOUT_Route_Set @ 0x1518;
    reg {
        name="PDM_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_RouteEnable_Set @ 0x1520;
    reg {
        name="PDM_CLK_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_CLK_Route_Set @ 0x1524;
    reg {
        name="PDM_DAT0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_DAT0_Route_Set @ 0x1528;
    reg {
        name="PDM_DAT1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_DAT1_Route_Set @ 0x152c;
    reg {
        name="PRS0_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_RouteEnable_Set @ 0x1534;
    reg {
        name="PRS0_ASYNCH0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH0_Route_Set @ 0x1538;
    reg {
        name="PRS0_ASYNCH1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH1_Route_Set @ 0x153c;
    reg {
        name="PRS0_ASYNCH2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH2_Route_Set @ 0x1540;
    reg {
        name="PRS0_ASYNCH3_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH3_Route_Set @ 0x1544;
    reg {
        name="PRS0_ASYNCH4_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH4_Route_Set @ 0x1548;
    reg {
        name="PRS0_ASYNCH5_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH5_Route_Set @ 0x154c;
    reg {
        name="PRS0_ASYNCH6_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH6_Route_Set @ 0x1550;
    reg {
        name="PRS0_ASYNCH7_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH7_Route_Set @ 0x1554;
    reg {
        name="PRS0_ASYNCH8_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH8_Route_Set @ 0x1558;
    reg {
        name="PRS0_ASYNCH9_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH9_Route_Set @ 0x155c;
    reg {
        name="PRS0_ASYNCH10_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH10_Route_Set @ 0x1560;
    reg {
        name="PRS0_ASYNCH11_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH11_Route_Set @ 0x1564;
    reg {
        name="PRS0_SYNCH0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH0_Route_Set @ 0x1568;
    reg {
        name="PRS0_SYNCH1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH1_Route_Set @ 0x156c;
    reg {
        name="PRS0_SYNCH2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH2_Route_Set @ 0x1570;
    reg {
        name="PRS0_SYNCH3_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH3_Route_Set @ 0x1574;
    reg {
        name="TIMER0_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_RouteEnable_Set @ 0x157c;
    reg {
        name="TIMER0_CC0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC0_Route_Set @ 0x1580;
    reg {
        name="TIMER0_CC1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC1_Route_Set @ 0x1584;
    reg {
        name="TIMER0_CC2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC2_Route_Set @ 0x1588;
    reg {
        name="TIMER0_CDTI0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI0_Route_Set @ 0x158c;
    reg {
        name="TIMER0_CDTI1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI1_Route_Set @ 0x1590;
    reg {
        name="TIMER0_CDTI2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI2_Route_Set @ 0x1594;
    reg {
        name="TIMER1_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_RouteEnable_Set @ 0x159c;
    reg {
        name="TIMER1_CC0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC0_Route_Set @ 0x15a0;
    reg {
        name="TIMER1_CC1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC1_Route_Set @ 0x15a4;
    reg {
        name="TIMER1_CC2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC2_Route_Set @ 0x15a8;
    reg {
        name="TIMER1_CDTI0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI0_Route_Set @ 0x15ac;
    reg {
        name="TIMER1_CDTI1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI1_Route_Set @ 0x15b0;
    reg {
        name="TIMER1_CDTI2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI2_Route_Set @ 0x15b4;
    reg {
        name="TIMER2_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_RouteEnable_Set @ 0x15bc;
    reg {
        name="TIMER2_CC0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC0_Route_Set @ 0x15c0;
    reg {
        name="TIMER2_CC1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC1_Route_Set @ 0x15c4;
    reg {
        name="TIMER2_CC2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC2_Route_Set @ 0x15c8;
    reg {
        name="TIMER2_CDTI0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI0_Route_Set @ 0x15cc;
    reg {
        name="TIMER2_CDTI1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI1_Route_Set @ 0x15d0;
    reg {
        name="TIMER2_CDTI2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI2_Route_Set @ 0x15d4;
    reg {
        name="TIMER3_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_RouteEnable_Set @ 0x15dc;
    reg {
        name="TIMER3_CC0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC0_Route_Set @ 0x15e0;
    reg {
        name="TIMER3_CC1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC1_Route_Set @ 0x15e4;
    reg {
        name="TIMER3_CC2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC2_Route_Set @ 0x15e8;
    reg {
        name="TIMER3_CDTI0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI0_Route_Set @ 0x15ec;
    reg {
        name="TIMER3_CDTI1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI1_Route_Set @ 0x15f0;
    reg {
        name="TIMER3_CDTI2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI2_Route_Set @ 0x15f4;
    reg {
        name="TIMER4_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_RouteEnable_Set @ 0x15fc;
    reg {
        name="TIMER4_CC0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC0_Route_Set @ 0x1600;
    reg {
        name="TIMER4_CC1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC1_Route_Set @ 0x1604;
    reg {
        name="TIMER4_CC2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC2_Route_Set @ 0x1608;
    reg {
        name="TIMER4_CDTI0_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI0_Route_Set @ 0x160c;
    reg {
        name="TIMER4_CDTI1_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI1_Route_Set @ 0x1610;
    reg {
        name="TIMER4_CDTI2_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI2_Route_Set @ 0x1614;
    reg {
        name="USART0_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RouteEnable_Set @ 0x161c;
    reg {
        name="USART0_CS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CS_Route_Set @ 0x1620;
    reg {
        name="USART0_CTS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CTS_Route_Set @ 0x1624;
    reg {
        name="USART0_RTS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RTS_Route_Set @ 0x1628;
    reg {
        name="USART0_RX_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RX_Route_Set @ 0x162c;
    reg {
        name="USART0_CLK_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CLK_Route_Set @ 0x1630;
    reg {
        name="USART0_TX_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_TX_Route_Set @ 0x1634;
    reg {
        name="USART1_RouteEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RouteEnable_Set @ 0x163c;
    reg {
        name="USART1_CS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CS_Route_Set @ 0x1640;
    reg {
        name="USART1_CTS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CTS_Route_Set @ 0x1644;
    reg {
        name="USART1_RTS_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RTS_Route_Set @ 0x1648;
    reg {
        name="USART1_RX_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RX_Route_Set @ 0x164c;
    reg {
        name="USART1_CLK_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CLK_Route_Set @ 0x1650;
    reg {
        name="USART1_TX_Route_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_TX_Route_Set @ 0x1654;
    reg {
        name="PortAControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAControl_Clr @ 0x2000;
    reg {
        name="PortAModeLow_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAModeLow_Clr @ 0x2004;
    reg {
        name="PortAModeHigh_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAModeHigh_Clr @ 0x200c;
    reg {
        name="PortADataOut_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortADataOut_Clr @ 0x2010;
    reg {
        name="PortADataIn_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortADataIn_Clr @ 0x2014;
    reg {
        name="PortBControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBControl_Clr @ 0x2030;
    reg {
        name="PortBModeLow_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBModeLow_Clr @ 0x2034;
    reg {
        name="PortBDataOut_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBDataOut_Clr @ 0x2040;
    reg {
        name="PortBDataIn_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBDataIn_Clr @ 0x2044;
    reg {
        name="PortBModeHigh_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBModeHigh_Clr @ 0x204c;
    reg {
        name="PortCControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCControl_Clr @ 0x2060;
    reg {
        name="PortCModeLow_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCModeLow_Clr @ 0x2064;
    reg {
        name="PortCModeHigh_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCModeHigh_Clr @ 0x206c;
    reg {
        name="PortCDataOut_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCDataOut_Clr @ 0x2070;
    reg {
        name="PortCDataIn_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCDataIn_Clr @ 0x2074;
    reg {
        name="PortDControl_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDControl_Clr @ 0x2090;
    reg {
        name="PortDModeLow_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDModeLow_Clr @ 0x2094;
    reg {
        name="PortDModeHigh_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDModeHigh_Clr @ 0x209c;
    reg {
        name="PortDDataOut_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDDataOut_Clr @ 0x20a0;
    reg {
        name="PortDDataIn_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDDataIn_Clr @ 0x20a4;
    reg {
        name="Lock_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_Clr @ 0x2300;
    reg {
        name="LockStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LockStatus_Clr @ 0x2310;
    reg {
        name="ABusAllocation_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ABusAllocation_Clr @ 0x2320;
    reg {
        name="BBusAllocation_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BBusAllocation_Clr @ 0x2324;
    reg {
        name="CDBusAllocation_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CDBusAllocation_Clr @ 0x2328;
    reg {
        name="ExternalInterruptPortSelectLow_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPortSelectLow_Clr @ 0x2400;
    reg {
        name="ExternalInterruptPortSelectHigh_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPortSelectHigh_Clr @ 0x2404;
    reg {
        name="ExternalInterruptPinSelectLow_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPinSelectLow_Clr @ 0x2408;
    reg {
        name="ExternalInterruptPinSelectHigh_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPinSelectHigh_Clr @ 0x240c;
    reg {
        name="ExternalInterruptRisingEdgeTrigger_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptRisingEdgeTrigger_Clr @ 0x2410;
    reg {
        name="ExternalInterruptFallingEdgeTrigger_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptFallingEdgeTrigger_Clr @ 0x2414;
    reg {
        name="InterruptFlag_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlag_Clr @ 0x2420;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x2424;
    reg {
        name="EM4WakeUpEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EM4WakeUpEnable_Clr @ 0x242c;
    reg {
        name="EM4WakeUpPolarity_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EM4WakeUpPolarity_Clr @ 0x2430;
    reg {
        name="DebugRoutePinEn_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DebugRoutePinEn_Clr @ 0x2440;
    reg {
        name="TraceRoutePinEn_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TraceRoutePinEn_Clr @ 0x2444;
    reg {
        name="CMU_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_RouteEnable_Clr @ 0x2450;
    reg {
        name="CMU_CLKIN0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKIN0_Route_Clr @ 0x2454;
    reg {
        name="CMU_CLKOUT0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT0_Route_Clr @ 0x2458;
    reg {
        name="CMU_CLKOUT1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT1_Route_Clr @ 0x245c;
    reg {
        name="CMU_CLKOUT2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT2_Route_Clr @ 0x2460;
    reg {
        name="DCDC_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCDC_RouteEnable_Clr @ 0x246c;
    reg {
        name="FRC_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_RouteEnable_Clr @ 0x247c;
    reg {
        name="FRC_DCLK_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DCLK_Route_Clr @ 0x2480;
    reg {
        name="FRC_DFRAME_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DFRAME_Route_Clr @ 0x2484;
    reg {
        name="FRC_DOUT_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DOUT_Route_Clr @ 0x2488;
    reg {
        name="I2C0_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_RouteEnable_Clr @ 0x2490;
    reg {
        name="I2C0_SCL_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_SCL_Route_Clr @ 0x2494;
    reg {
        name="I2C0_SDA_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_SDA_Route_Clr @ 0x2498;
    reg {
        name="I2C1_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_RouteEnable_Clr @ 0x24a0;
    reg {
        name="I2C1_SCL_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_SCL_Route_Clr @ 0x24a4;
    reg {
        name="I2C1_SDA_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_SDA_Route_Clr @ 0x24a8;
    reg {
        name="LETIMER_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_RouteEnable_Clr @ 0x24b0;
    reg {
        name="LETIMER_OUT0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_OUT0_Route_Clr @ 0x24b4;
    reg {
        name="LETIMER_OUT1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_OUT1_Route_Clr @ 0x24b8;
    reg {
        name="ESART0_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RouteEnable_Clr @ 0x24c0;
    reg {
        name="ESART0_CS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_CS_Route_Clr @ 0x24c4;
    reg {
        name="ESART0_CTS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_CTS_Route_Clr @ 0x24c8;
    reg {
        name="ESART0_RTS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RTS_Route_Clr @ 0x24cc;
    reg {
        name="ESART0_RX_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RX_Route_Clr @ 0x24d0;
    reg {
        name="MODEM_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_RouteEnable_Clr @ 0x24d8;
    reg {
        name="MODEM_ANT0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANT0_Route_Clr @ 0x24dc;
    reg {
        name="MODEM_ANT1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANT1_Route_Clr @ 0x24e0;
    reg {
        name="MODEM_ANTROLLOVER_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTROLLOVER_Route_Clr @ 0x24e4;
    reg {
        name="MODEM_ANTRR0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR0_Route_Clr @ 0x24e8;
    reg {
        name="MODEM_ANTRR1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR1_Route_Clr @ 0x24ec;
    reg {
        name="MODEM_ANTRR2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR2_Route_Clr @ 0x24f0;
    reg {
        name="MODEM_ANTRR3_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR3_Route_Clr @ 0x24f4;
    reg {
        name="MODEM_ANTRR4_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR4_Route_Clr @ 0x24f8;
    reg {
        name="MODEM_ANTRR5_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR5_Route_Clr @ 0x24fc;
    reg {
        name="MODEM_ANTSWEN_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTSWEN_Route_Clr @ 0x2500;
    reg {
        name="MODEM_ANTSWUS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTSWUS_Route_Clr @ 0x2504;
    reg {
        name="MODEM_ANTTRIG_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTTRIG_Route_Clr @ 0x2508;
    reg {
        name="MODEM_ANTTRIGSTOP_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTTRIGSTOP_Route_Clr @ 0x250c;
    reg {
        name="MODEM_DCLK_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DCLK_Route_Clr @ 0x2510;
    reg {
        name="MODEM_DIN_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DIN_Route_Clr @ 0x2514;
    reg {
        name="MODEM_DOUT_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DOUT_Route_Clr @ 0x2518;
    reg {
        name="PDM_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_RouteEnable_Clr @ 0x2520;
    reg {
        name="PDM_CLK_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_CLK_Route_Clr @ 0x2524;
    reg {
        name="PDM_DAT0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_DAT0_Route_Clr @ 0x2528;
    reg {
        name="PDM_DAT1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_DAT1_Route_Clr @ 0x252c;
    reg {
        name="PRS0_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_RouteEnable_Clr @ 0x2534;
    reg {
        name="PRS0_ASYNCH0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH0_Route_Clr @ 0x2538;
    reg {
        name="PRS0_ASYNCH1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH1_Route_Clr @ 0x253c;
    reg {
        name="PRS0_ASYNCH2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH2_Route_Clr @ 0x2540;
    reg {
        name="PRS0_ASYNCH3_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH3_Route_Clr @ 0x2544;
    reg {
        name="PRS0_ASYNCH4_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH4_Route_Clr @ 0x2548;
    reg {
        name="PRS0_ASYNCH5_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH5_Route_Clr @ 0x254c;
    reg {
        name="PRS0_ASYNCH6_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH6_Route_Clr @ 0x2550;
    reg {
        name="PRS0_ASYNCH7_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH7_Route_Clr @ 0x2554;
    reg {
        name="PRS0_ASYNCH8_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH8_Route_Clr @ 0x2558;
    reg {
        name="PRS0_ASYNCH9_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH9_Route_Clr @ 0x255c;
    reg {
        name="PRS0_ASYNCH10_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH10_Route_Clr @ 0x2560;
    reg {
        name="PRS0_ASYNCH11_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH11_Route_Clr @ 0x2564;
    reg {
        name="PRS0_SYNCH0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH0_Route_Clr @ 0x2568;
    reg {
        name="PRS0_SYNCH1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH1_Route_Clr @ 0x256c;
    reg {
        name="PRS0_SYNCH2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH2_Route_Clr @ 0x2570;
    reg {
        name="PRS0_SYNCH3_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH3_Route_Clr @ 0x2574;
    reg {
        name="TIMER0_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_RouteEnable_Clr @ 0x257c;
    reg {
        name="TIMER0_CC0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC0_Route_Clr @ 0x2580;
    reg {
        name="TIMER0_CC1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC1_Route_Clr @ 0x2584;
    reg {
        name="TIMER0_CC2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC2_Route_Clr @ 0x2588;
    reg {
        name="TIMER0_CDTI0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI0_Route_Clr @ 0x258c;
    reg {
        name="TIMER0_CDTI1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI1_Route_Clr @ 0x2590;
    reg {
        name="TIMER0_CDTI2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI2_Route_Clr @ 0x2594;
    reg {
        name="TIMER1_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_RouteEnable_Clr @ 0x259c;
    reg {
        name="TIMER1_CC0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC0_Route_Clr @ 0x25a0;
    reg {
        name="TIMER1_CC1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC1_Route_Clr @ 0x25a4;
    reg {
        name="TIMER1_CC2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC2_Route_Clr @ 0x25a8;
    reg {
        name="TIMER1_CDTI0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI0_Route_Clr @ 0x25ac;
    reg {
        name="TIMER1_CDTI1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI1_Route_Clr @ 0x25b0;
    reg {
        name="TIMER1_CDTI2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI2_Route_Clr @ 0x25b4;
    reg {
        name="TIMER2_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_RouteEnable_Clr @ 0x25bc;
    reg {
        name="TIMER2_CC0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC0_Route_Clr @ 0x25c0;
    reg {
        name="TIMER2_CC1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC1_Route_Clr @ 0x25c4;
    reg {
        name="TIMER2_CC2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC2_Route_Clr @ 0x25c8;
    reg {
        name="TIMER2_CDTI0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI0_Route_Clr @ 0x25cc;
    reg {
        name="TIMER2_CDTI1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI1_Route_Clr @ 0x25d0;
    reg {
        name="TIMER2_CDTI2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI2_Route_Clr @ 0x25d4;
    reg {
        name="TIMER3_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_RouteEnable_Clr @ 0x25dc;
    reg {
        name="TIMER3_CC0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC0_Route_Clr @ 0x25e0;
    reg {
        name="TIMER3_CC1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC1_Route_Clr @ 0x25e4;
    reg {
        name="TIMER3_CC2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC2_Route_Clr @ 0x25e8;
    reg {
        name="TIMER3_CDTI0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI0_Route_Clr @ 0x25ec;
    reg {
        name="TIMER3_CDTI1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI1_Route_Clr @ 0x25f0;
    reg {
        name="TIMER3_CDTI2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI2_Route_Clr @ 0x25f4;
    reg {
        name="TIMER4_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_RouteEnable_Clr @ 0x25fc;
    reg {
        name="TIMER4_CC0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC0_Route_Clr @ 0x2600;
    reg {
        name="TIMER4_CC1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC1_Route_Clr @ 0x2604;
    reg {
        name="TIMER4_CC2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC2_Route_Clr @ 0x2608;
    reg {
        name="TIMER4_CDTI0_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI0_Route_Clr @ 0x260c;
    reg {
        name="TIMER4_CDTI1_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI1_Route_Clr @ 0x2610;
    reg {
        name="TIMER4_CDTI2_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI2_Route_Clr @ 0x2614;
    reg {
        name="USART0_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RouteEnable_Clr @ 0x261c;
    reg {
        name="USART0_CS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CS_Route_Clr @ 0x2620;
    reg {
        name="USART0_CTS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CTS_Route_Clr @ 0x2624;
    reg {
        name="USART0_RTS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RTS_Route_Clr @ 0x2628;
    reg {
        name="USART0_RX_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RX_Route_Clr @ 0x262c;
    reg {
        name="USART0_CLK_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CLK_Route_Clr @ 0x2630;
    reg {
        name="USART0_TX_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_TX_Route_Clr @ 0x2634;
    reg {
        name="USART1_RouteEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RouteEnable_Clr @ 0x263c;
    reg {
        name="USART1_CS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CS_Route_Clr @ 0x2640;
    reg {
        name="USART1_CTS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CTS_Route_Clr @ 0x2644;
    reg {
        name="USART1_RTS_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RTS_Route_Clr @ 0x2648;
    reg {
        name="USART1_RX_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RX_Route_Clr @ 0x264c;
    reg {
        name="USART1_CLK_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CLK_Route_Clr @ 0x2650;
    reg {
        name="USART1_TX_Route_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_TX_Route_Clr @ 0x2654;
    reg {
        name="PortAControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAControl_Tgl @ 0x3000;
    reg {
        name="PortAModeLow_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAModeLow_Tgl @ 0x3004;
    reg {
        name="PortAModeHigh_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortAModeHigh_Tgl @ 0x300c;
    reg {
        name="PortADataOut_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortADataOut_Tgl @ 0x3010;
    reg {
        name="PortADataIn_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortADataIn_Tgl @ 0x3014;
    reg {
        name="PortBControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBControl_Tgl @ 0x3030;
    reg {
        name="PortBModeLow_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBModeLow_Tgl @ 0x3034;
    reg {
        name="PortBDataOut_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBDataOut_Tgl @ 0x3040;
    reg {
        name="PortBDataIn_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBDataIn_Tgl @ 0x3044;
    reg {
        name="PortBModeHigh_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortBModeHigh_Tgl @ 0x304c;
    reg {
        name="PortCControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCControl_Tgl @ 0x3060;
    reg {
        name="PortCModeLow_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCModeLow_Tgl @ 0x3064;
    reg {
        name="PortCModeHigh_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCModeHigh_Tgl @ 0x306c;
    reg {
        name="PortCDataOut_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCDataOut_Tgl @ 0x3070;
    reg {
        name="PortCDataIn_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortCDataIn_Tgl @ 0x3074;
    reg {
        name="PortDControl_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDControl_Tgl @ 0x3090;
    reg {
        name="PortDModeLow_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDModeLow_Tgl @ 0x3094;
    reg {
        name="PortDModeHigh_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDModeHigh_Tgl @ 0x309c;
    reg {
        name="PortDDataOut_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDDataOut_Tgl @ 0x30a0;
    reg {
        name="PortDDataIn_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PortDDataIn_Tgl @ 0x30a4;
    reg {
        name="Lock_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_Tgl @ 0x3300;
    reg {
        name="LockStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LockStatus_Tgl @ 0x3310;
    reg {
        name="ABusAllocation_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ABusAllocation_Tgl @ 0x3320;
    reg {
        name="BBusAllocation_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BBusAllocation_Tgl @ 0x3324;
    reg {
        name="CDBusAllocation_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CDBusAllocation_Tgl @ 0x3328;
    reg {
        name="ExternalInterruptPortSelectLow_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPortSelectLow_Tgl @ 0x3400;
    reg {
        name="ExternalInterruptPortSelectHigh_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPortSelectHigh_Tgl @ 0x3404;
    reg {
        name="ExternalInterruptPinSelectLow_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPinSelectLow_Tgl @ 0x3408;
    reg {
        name="ExternalInterruptPinSelectHigh_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptPinSelectHigh_Tgl @ 0x340c;
    reg {
        name="ExternalInterruptRisingEdgeTrigger_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptRisingEdgeTrigger_Tgl @ 0x3410;
    reg {
        name="ExternalInterruptFallingEdgeTrigger_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExternalInterruptFallingEdgeTrigger_Tgl @ 0x3414;
    reg {
        name="InterruptFlag_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlag_Tgl @ 0x3420;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x3424;
    reg {
        name="EM4WakeUpEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EM4WakeUpEnable_Tgl @ 0x342c;
    reg {
        name="EM4WakeUpPolarity_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EM4WakeUpPolarity_Tgl @ 0x3430;
    reg {
        name="DebugRoutePinEn_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DebugRoutePinEn_Tgl @ 0x3440;
    reg {
        name="TraceRoutePinEn_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TraceRoutePinEn_Tgl @ 0x3444;
    reg {
        name="CMU_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_RouteEnable_Tgl @ 0x3450;
    reg {
        name="CMU_CLKIN0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKIN0_Route_Tgl @ 0x3454;
    reg {
        name="CMU_CLKOUT0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT0_Route_Tgl @ 0x3458;
    reg {
        name="CMU_CLKOUT1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT1_Route_Tgl @ 0x345c;
    reg {
        name="CMU_CLKOUT2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CMU_CLKOUT2_Route_Tgl @ 0x3460;
    reg {
        name="DCDC_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DCDC_RouteEnable_Tgl @ 0x346c;
    reg {
        name="FRC_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_RouteEnable_Tgl @ 0x347c;
    reg {
        name="FRC_DCLK_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DCLK_Route_Tgl @ 0x3480;
    reg {
        name="FRC_DFRAME_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DFRAME_Route_Tgl @ 0x3484;
    reg {
        name="FRC_DOUT_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FRC_DOUT_Route_Tgl @ 0x3488;
    reg {
        name="I2C0_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_RouteEnable_Tgl @ 0x3490;
    reg {
        name="I2C0_SCL_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_SCL_Route_Tgl @ 0x3494;
    reg {
        name="I2C0_SDA_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C0_SDA_Route_Tgl @ 0x3498;
    reg {
        name="I2C1_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_RouteEnable_Tgl @ 0x34a0;
    reg {
        name="I2C1_SCL_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_SCL_Route_Tgl @ 0x34a4;
    reg {
        name="I2C1_SDA_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } I2C1_SDA_Route_Tgl @ 0x34a8;
    reg {
        name="LETIMER_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_RouteEnable_Tgl @ 0x34b0;
    reg {
        name="LETIMER_OUT0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_OUT0_Route_Tgl @ 0x34b4;
    reg {
        name="LETIMER_OUT1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LETIMER_OUT1_Route_Tgl @ 0x34b8;
    reg {
        name="ESART0_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RouteEnable_Tgl @ 0x34c0;
    reg {
        name="ESART0_CS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_CS_Route_Tgl @ 0x34c4;
    reg {
        name="ESART0_CTS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_CTS_Route_Tgl @ 0x34c8;
    reg {
        name="ESART0_RTS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RTS_Route_Tgl @ 0x34cc;
    reg {
        name="ESART0_RX_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESART0_RX_Route_Tgl @ 0x34d0;
    reg {
        name="MODEM_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_RouteEnable_Tgl @ 0x34d8;
    reg {
        name="MODEM_ANT0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANT0_Route_Tgl @ 0x34dc;
    reg {
        name="MODEM_ANT1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANT1_Route_Tgl @ 0x34e0;
    reg {
        name="MODEM_ANTROLLOVER_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTROLLOVER_Route_Tgl @ 0x34e4;
    reg {
        name="MODEM_ANTRR0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR0_Route_Tgl @ 0x34e8;
    reg {
        name="MODEM_ANTRR1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR1_Route_Tgl @ 0x34ec;
    reg {
        name="MODEM_ANTRR2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR2_Route_Tgl @ 0x34f0;
    reg {
        name="MODEM_ANTRR3_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR3_Route_Tgl @ 0x34f4;
    reg {
        name="MODEM_ANTRR4_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR4_Route_Tgl @ 0x34f8;
    reg {
        name="MODEM_ANTRR5_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTRR5_Route_Tgl @ 0x34fc;
    reg {
        name="MODEM_ANTSWEN_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTSWEN_Route_Tgl @ 0x3500;
    reg {
        name="MODEM_ANTSWUS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTSWUS_Route_Tgl @ 0x3504;
    reg {
        name="MODEM_ANTTRIG_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTTRIG_Route_Tgl @ 0x3508;
    reg {
        name="MODEM_ANTTRIGSTOP_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_ANTTRIGSTOP_Route_Tgl @ 0x350c;
    reg {
        name="MODEM_DCLK_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DCLK_Route_Tgl @ 0x3510;
    reg {
        name="MODEM_DIN_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DIN_Route_Tgl @ 0x3514;
    reg {
        name="MODEM_DOUT_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MODEM_DOUT_Route_Tgl @ 0x3518;
    reg {
        name="PDM_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_RouteEnable_Tgl @ 0x3520;
    reg {
        name="PDM_CLK_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_CLK_Route_Tgl @ 0x3524;
    reg {
        name="PDM_DAT0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_DAT0_Route_Tgl @ 0x3528;
    reg {
        name="PDM_DAT1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PDM_DAT1_Route_Tgl @ 0x352c;
    reg {
        name="PRS0_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_RouteEnable_Tgl @ 0x3534;
    reg {
        name="PRS0_ASYNCH0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH0_Route_Tgl @ 0x3538;
    reg {
        name="PRS0_ASYNCH1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH1_Route_Tgl @ 0x353c;
    reg {
        name="PRS0_ASYNCH2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH2_Route_Tgl @ 0x3540;
    reg {
        name="PRS0_ASYNCH3_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH3_Route_Tgl @ 0x3544;
    reg {
        name="PRS0_ASYNCH4_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH4_Route_Tgl @ 0x3548;
    reg {
        name="PRS0_ASYNCH5_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH5_Route_Tgl @ 0x354c;
    reg {
        name="PRS0_ASYNCH6_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH6_Route_Tgl @ 0x3550;
    reg {
        name="PRS0_ASYNCH7_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH7_Route_Tgl @ 0x3554;
    reg {
        name="PRS0_ASYNCH8_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH8_Route_Tgl @ 0x3558;
    reg {
        name="PRS0_ASYNCH9_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH9_Route_Tgl @ 0x355c;
    reg {
        name="PRS0_ASYNCH10_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH10_Route_Tgl @ 0x3560;
    reg {
        name="PRS0_ASYNCH11_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_ASYNCH11_Route_Tgl @ 0x3564;
    reg {
        name="PRS0_SYNCH0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH0_Route_Tgl @ 0x3568;
    reg {
        name="PRS0_SYNCH1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH1_Route_Tgl @ 0x356c;
    reg {
        name="PRS0_SYNCH2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH2_Route_Tgl @ 0x3570;
    reg {
        name="PRS0_SYNCH3_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PRS0_SYNCH3_Route_Tgl @ 0x3574;
    reg {
        name="TIMER0_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_RouteEnable_Tgl @ 0x357c;
    reg {
        name="TIMER0_CC0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC0_Route_Tgl @ 0x3580;
    reg {
        name="TIMER0_CC1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC1_Route_Tgl @ 0x3584;
    reg {
        name="TIMER0_CC2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CC2_Route_Tgl @ 0x3588;
    reg {
        name="TIMER0_CDTI0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI0_Route_Tgl @ 0x358c;
    reg {
        name="TIMER0_CDTI1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI1_Route_Tgl @ 0x3590;
    reg {
        name="TIMER0_CDTI2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER0_CDTI2_Route_Tgl @ 0x3594;
    reg {
        name="TIMER1_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_RouteEnable_Tgl @ 0x359c;
    reg {
        name="TIMER1_CC0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC0_Route_Tgl @ 0x35a0;
    reg {
        name="TIMER1_CC1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC1_Route_Tgl @ 0x35a4;
    reg {
        name="TIMER1_CC2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CC2_Route_Tgl @ 0x35a8;
    reg {
        name="TIMER1_CDTI0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI0_Route_Tgl @ 0x35ac;
    reg {
        name="TIMER1_CDTI1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI1_Route_Tgl @ 0x35b0;
    reg {
        name="TIMER1_CDTI2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER1_CDTI2_Route_Tgl @ 0x35b4;
    reg {
        name="TIMER2_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_RouteEnable_Tgl @ 0x35bc;
    reg {
        name="TIMER2_CC0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC0_Route_Tgl @ 0x35c0;
    reg {
        name="TIMER2_CC1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC1_Route_Tgl @ 0x35c4;
    reg {
        name="TIMER2_CC2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CC2_Route_Tgl @ 0x35c8;
    reg {
        name="TIMER2_CDTI0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI0_Route_Tgl @ 0x35cc;
    reg {
        name="TIMER2_CDTI1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI1_Route_Tgl @ 0x35d0;
    reg {
        name="TIMER2_CDTI2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER2_CDTI2_Route_Tgl @ 0x35d4;
    reg {
        name="TIMER3_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_RouteEnable_Tgl @ 0x35dc;
    reg {
        name="TIMER3_CC0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC0_Route_Tgl @ 0x35e0;
    reg {
        name="TIMER3_CC1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC1_Route_Tgl @ 0x35e4;
    reg {
        name="TIMER3_CC2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CC2_Route_Tgl @ 0x35e8;
    reg {
        name="TIMER3_CDTI0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI0_Route_Tgl @ 0x35ec;
    reg {
        name="TIMER3_CDTI1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI1_Route_Tgl @ 0x35f0;
    reg {
        name="TIMER3_CDTI2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER3_CDTI2_Route_Tgl @ 0x35f4;
    reg {
        name="TIMER4_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_RouteEnable_Tgl @ 0x35fc;
    reg {
        name="TIMER4_CC0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC0_Route_Tgl @ 0x3600;
    reg {
        name="TIMER4_CC1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC1_Route_Tgl @ 0x3604;
    reg {
        name="TIMER4_CC2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CC2_Route_Tgl @ 0x3608;
    reg {
        name="TIMER4_CDTI0_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI0_Route_Tgl @ 0x360c;
    reg {
        name="TIMER4_CDTI1_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI1_Route_Tgl @ 0x3610;
    reg {
        name="TIMER4_CDTI2_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } TIMER4_CDTI2_Route_Tgl @ 0x3614;
    reg {
        name="USART0_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RouteEnable_Tgl @ 0x361c;
    reg {
        name="USART0_CS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CS_Route_Tgl @ 0x3620;
    reg {
        name="USART0_CTS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CTS_Route_Tgl @ 0x3624;
    reg {
        name="USART0_RTS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RTS_Route_Tgl @ 0x3628;
    reg {
        name="USART0_RX_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_RX_Route_Tgl @ 0x362c;
    reg {
        name="USART0_CLK_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_CLK_Route_Tgl @ 0x3630;
    reg {
        name="USART0_TX_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART0_TX_Route_Tgl @ 0x3634;
    reg {
        name="USART1_RouteEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RouteEnable_Tgl @ 0x363c;
    reg {
        name="USART1_CS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CS_Route_Tgl @ 0x3640;
    reg {
        name="USART1_CTS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CTS_Route_Tgl @ 0x3644;
    reg {
        name="USART1_RTS_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RTS_Route_Tgl @ 0x3648;
    reg {
        name="USART1_RX_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_RX_Route_Tgl @ 0x364c;
    reg {
        name="USART1_CLK_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_CLK_Route_Tgl @ 0x3650;
    reg {
        name="USART1_TX_Route_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } USART1_TX_Route_Tgl @ 0x3654;
} Registers_addrmap;


};