addrmap EOSS3_FlexibleFusionEngine {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="WishboneAddress";
        regwidth=0x20;
            field {
                sw = rw;
            } Addr[2:0];
            field {
                sw = rw;
            } slave_sel[7:6];
    } WishboneAddress @ 0x0;
    reg {
        name="WriteData";
        regwidth=0x20;
            field {
                sw = rw;
            } WDATA[7:0];
    } WriteData @ 0x4;
    reg {
        name="ControlAndStatus";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x20;
            field {
                sw = w;
                onwrite = woset;
            } wb_ms_start[0:0];
            field {
                sw = rw;
            } wb_ms_wen[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } mux_wb_sn[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } BUSY[3:3];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } OVFL[4:4];
            field {
                sw = rw;
            } mux_sel[7:5];
    } ControlAndStatus @ 0x8;
    reg {
        name="ReadData";
        regwidth=0x20;
            field {
                sw = r;
            } RDATA[7:0];
    } ReadData @ 0xc;
    reg {
        name="SRAMTest1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SRAMTest1 @ 0x14;
    reg {
        name="SRAMTest2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SRAMTest2 @ 0x18;
    reg {
        name="FFEControlAndStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFEControlAndStatus @ 0x20;
    reg {
        name="FFEDebugCombined";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFEDebugCombined @ 0x38;
    reg {
        name="Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command @ 0x100;
    reg {
        name="Interrupt";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Interrupt @ 0x108;
    reg {
        name="InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable @ 0x10c;
    reg {
        name="Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status @ 0x110;
    reg {
        name="MailboxToFFE0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MailboxToFFE0 @ 0x114;
    reg {
        name="SMRuntimeAddress";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SMRuntimeAddress @ 0x120;
    reg {
        name="SM0RuntimeAddressControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM0RuntimeAddressControl @ 0x124;
    reg {
        name="SM1RuntimeAddressControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM1RuntimeAddressControl @ 0x128;
    reg {
        name="SM0RuntimeAddressCurrent";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM0RuntimeAddressCurrent @ 0x12c;
    reg {
        name="SM1RuntimeAddressCurrent";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM1RuntimeAddressCurrent @ 0x130;
    reg {
        name="SM0DebugSelection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM0DebugSelection @ 0x140;
    reg {
        name="SM1DebugSelection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SM1DebugSelection @ 0x144;
    reg {
        name="FFEDebugSelection";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFEDebugSelection @ 0x148;
    reg {
        name="FFE0BreakpointConfig";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFE0BreakpointConfig @ 0x150;
    reg {
        name="FFE0BreakPointContinue";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFE0BreakPointContinue @ 0x154;
    reg {
        name="FFE0BreakPointStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFE0BreakPointStatus @ 0x158;
    reg {
        name="FFE0BreakpointProgramCounter0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFE0BreakpointProgramCounter0 @ 0x160;
    reg {
        name="FFE0BreakpointProgramCounter1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFE0BreakpointProgramCounter1 @ 0x164;
    reg {
        name="FFE0BreakpointProgramCounter2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFE0BreakpointProgramCounter2 @ 0x168;
    reg {
        name="FFE0BreakpointProgramCounter3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FFE0BreakpointProgramCounter3 @ 0x16c;
} Registers_addrmap;


};