addrmap EFR32xG2_SMU_1 {

/* Some conversion errors detected, this might mean that the peripheral's registers structure in this file is incomplete.
 * Please refer to logs and comments in the file for more information.
 * 
 * Field "SMULOCK_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "SMUPRGERR_" overlaps another field at the same offset (0x1) and will be skipped, as it is illegal in SystemRDL.
 * Field "SMULOCKKEY_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "PPUNSPRIVIF" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "PPUNSINSTIF" overlaps another field at the same offset (0x2) and will be skipped, as it is illegal in SystemRDL.
 * Field "PPUNSPRIVIEN" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 * Field "PPUNSINSTIEN" overlaps another field at the same offset (0x2) and will be skipped, as it is illegal in SystemRDL.
 * Field "PPUFSPERIPHID_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
 */

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="IpVersion";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
                reset=32'b1;
            } IPVERSION[31:0];
    } IpVersion @ 0x0;
    reg {
        name="Status";
        regwidth=0x20;
        `ifdef VARIANT0
            field {
                sw = r;
            } SMULOCK[0:0];
            field {
                sw = r;
            } SMUPRGERR[1:1];
        `elsif VARIANT3
            /* Conversion error: Field "SMULOCK_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = r;
            } SMULOCK_[0:0];
            */
            /* Conversion error: Field "SMUPRGERR_" overlaps another field at the same offset (0x1) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = r;
            } SMUPRGERR_[1:1];
            */
        `endif

    } Status @ 0x4;
    reg {
        name="Lock";
        regwidth=0x20;
        `ifdef VARIANT0
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } SMULOCKKEY[23:0];
        `elsif VARIANT2
            /* Conversion error: Field "SMULOCKKEY_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } SMULOCKKEY_[23:0];
            */
        `endif

    } Lock @ 0x8;
    reg {
        name="InterruptFlags";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
        `ifdef VARIANT0
            field {
                sw = rw;
            } PPUPRIVIF[0:0];
            field {
                sw = rw;
            } PPUINSTIF[2:2];
            field {
                sw = rw;
            } PPUSECIF[16:16];
            field {
                sw = rw;
            } BMPUSECIF[17:17];
        `elsif VARIANT7
            /* Conversion error: Field "PPUNSPRIVIF" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
            } PPUNSPRIVIF[0:0];
            */
            /* Conversion error: Field "PPUNSINSTIF" overlaps another field at the same offset (0x2) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
            } PPUNSINSTIF[2:2];
            */
        `endif

    } InterruptFlags @ 0xc;
    reg {
        name="InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
        `ifdef VARIANT0
            field {
                sw = rw;
            } PPUPRIVIEN[0:0];
            field {
                sw = rw;
            } PPUINSTIEN[2:2];
            field {
                sw = rw;
            } PPUSECIEN[16:16];
            field {
                sw = rw;
            } BMPUSECIEN[17:17];
        `elsif VARIANT7
            /* Conversion error: Field "PPUNSPRIVIEN" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
            } PPUNSPRIVIEN[0:0];
            */
            /* Conversion error: Field "PPUNSINSTIEN" overlaps another field at the same offset (0x2) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = rw;
            } PPUNSINSTIEN[2:2];
            */
        `endif

    } InterruptEnable @ 0x10;
    reg {
        name="M33Control";
        regwidth=0x20;
            field {
                sw = rw;
            } LOCKSAU[0:0];
            field {
                sw = rw;
            } LOCKNSMPU[1:1];
            field {
                sw = rw;
            } LOCKSMPU[2:2];
            field {
                sw = rw;
            } LOCKNSVTOR[3:3];
            field {
                sw = rw;
            } LOCKSVTAIRCR[4:4];
    } M33Control @ 0x20;
    reg {
        name="M33InitNsVector";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TBLOFF[31:7];
    } M33InitNsVector @ 0x24;
    reg {
        name="M33InitSVector";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } TBLOFF[31:7];
    } M33InitSVector @ 0x28;
    reg {
        name="PPU_PriviledgedAttribute0";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
                reset=32'b11111111111111111111111111111111;
            } DUMMY[31:0];
    } PPU_PriviledgedAttribute0 @ 0x40;
    reg {
        name="PPU_PriviledgedAttribute1";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
                reset=32'b11111111111111111111111111111111;
            } DUMMY[31:0];
    } PPU_PriviledgedAttribute1 @ 0x44;
    reg {
        name="PPU_SecureAttribute0";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
                reset=32'b11111111111111111111111111111111;
            } DUMMY[31:0];
    } PPU_SecureAttribute0 @ 0x60;
    reg {
        name="PPU_SecureAttribute1";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
                reset=32'b11111111111111111111111111111111;
            } DUMMY[31:0];
    } PPU_SecureAttribute1 @ 0x64;
    reg {
        name="PPU_Disable0";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } PPU_Disable0 @ 0x120;
    reg {
        name="PPU_Disable1";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } PPU_Disable1 @ 0x124;
    reg {
        name="PPU_FaultStatus";
        regwidth=0x20;
        `ifdef VARIANT0
            field {
                sw = r;
            } PPUFSPERIPHID[7:0];
        `elsif VARIANT2
            /* Conversion error: Field "PPUFSPERIPHID_" overlaps another field at the same offset (0x0) and will be skipped, as it is illegal in SystemRDL.
            field {
                sw = r;
            } PPUFSPERIPHID_[7:0];
            */
        `endif

    } PPU_FaultStatus @ 0x140;
    reg {
        name="BMPU_PriviledgedAttribute0";
        regwidth=0x20;
            field {
                sw = rw;
                reset=1'b1;
            } BMPUPATD0[0:0];
            field {
                sw = rw;
                reset=1'b1;
            } BMPUPATD1[1:1];
            field {
                sw = rw;
                reset=1'b1;
            } BMPUPATD2[2:2];
            field {
                sw = rw;
                reset=1'b1;
            } BMPUPATD3[3:3];
            field {
                sw = rw;
                reset=1'b1;
            } BMPUPATD4[4:4];
    } BMPU_PriviledgedAttribute0 @ 0x150;
    reg {
        name="BMPU_SecureAttribute0";
        regwidth=0x20;
            field {
                sw = rw;
                reset=1'b1;
            } BMPUSATD0[0:0];
            field {
                sw = rw;
                reset=1'b1;
            } BMPUSATD1[1:1];
            field {
                sw = rw;
                reset=1'b1;
            } BMPUSATD2[2:2];
            field {
                sw = rw;
                reset=1'b1;
            } BMPUSATD3[3:3];
            field {
                sw = rw;
                reset=1'b1;
            } BMPUSATD4[4:4];
    } BMPU_SecureAttribute0 @ 0x170;
    reg {
        name="BMPU_FaultStatus";
        regwidth=0x20;
            field {
                sw = r;
            } BMPUFSMASTERID[7:0];
    } BMPU_FaultStatus @ 0x250;
    reg {
        name="BMPU_FaultStatusAddress";
        regwidth=0x20;
            field {
                sw = r;
            } BMPUFSMASTERID[31:0];
    } BMPU_FaultStatusAddress @ 0x254;
    reg {
        name="ESAU_RegionTypes0";
        regwidth=0x20;
            field {
                sw = rw;
            } ESAUR3NS[12:12];
    } ESAU_RegionTypes0 @ 0x260;
    reg {
        name="ESAU_RegionTypes1";
        regwidth=0x20;
            field {
                sw = rw;
            } ESAUR11NS[12:12];
    } ESAU_RegionTypes1 @ 0x264;
    reg {
        name="ESAU_MovableRegionBoundary0_1";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
                reset=16'b10000000000000;
            } ESAUMRB01[27:12];
    } ESAU_MovableRegionBoundary0_1 @ 0x270;
    reg {
        name="ESAU_MovableRegionBoundary1_2";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
                reset=16'b100000000000000;
            } ESAUMRB12[27:12];
    } ESAU_MovableRegionBoundary1_2 @ 0x274;
    reg {
        name="ESAU_MovableRegionBoundary4_5";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
                reset=16'b10000000000000;
            } ESAUMRB45[27:12];
    } ESAU_MovableRegionBoundary4_5 @ 0x280;
    reg {
        name="ESAU_MovableRegionBoundary5_6";
        desc = "This register has the following custom Renode callbacks: Change";
        regwidth=0x20;
            field {
                sw = rw;
                reset=16'b100000000000000;
            } ESAUMRB56[27:12];
    } ESAU_MovableRegionBoundary5_6 @ 0x284;
    reg {
        name="IpVersion_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Set @ 0x1000;
    reg {
        name="Status_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Set @ 0x1004;
    reg {
        name="Lock_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_Set @ 0x1008;
    reg {
        name="InterruptFlags_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Set @ 0x100c;
    reg {
        name="InterruptEnable_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Set @ 0x1010;
    reg {
        name="M33Control_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33Control_Set @ 0x1020;
    reg {
        name="M33InitNsVector_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33InitNsVector_Set @ 0x1024;
    reg {
        name="M33InitSVector_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33InitSVector_Set @ 0x1028;
    reg {
        name="PPU_PriviledgedAttribute0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_PriviledgedAttribute0_Set @ 0x1040;
    reg {
        name="PPU_PriviledgedAttribute1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_PriviledgedAttribute1_Set @ 0x1044;
    reg {
        name="PPU_SecureAttribute0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_SecureAttribute0_Set @ 0x1060;
    reg {
        name="PPU_SecureAttribute1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_SecureAttribute1_Set @ 0x1064;
    reg {
        name="PPU_Disable0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_Disable0_Set @ 0x1120;
    reg {
        name="PPU_Disable1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_Disable1_Set @ 0x1124;
    reg {
        name="PPU_FaultStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_FaultStatus_Set @ 0x1140;
    reg {
        name="BMPU_PriviledgedAttribute0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_PriviledgedAttribute0_Set @ 0x1150;
    reg {
        name="BMPU_SecureAttribute0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_SecureAttribute0_Set @ 0x1170;
    reg {
        name="BMPU_FaultStatus_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_FaultStatus_Set @ 0x1250;
    reg {
        name="BMPU_FaultStatusAddress_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_FaultStatusAddress_Set @ 0x1254;
    reg {
        name="ESAU_RegionTypes0_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_RegionTypes0_Set @ 0x1260;
    reg {
        name="ESAU_RegionTypes1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_RegionTypes1_Set @ 0x1264;
    reg {
        name="ESAU_MovableRegionBoundary0_1_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary0_1_Set @ 0x1270;
    reg {
        name="ESAU_MovableRegionBoundary1_2_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary1_2_Set @ 0x1274;
    reg {
        name="ESAU_MovableRegionBoundary4_5_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary4_5_Set @ 0x1280;
    reg {
        name="ESAU_MovableRegionBoundary5_6_Set";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary5_6_Set @ 0x1284;
    reg {
        name="IpVersion_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Clr @ 0x2000;
    reg {
        name="Status_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Clr @ 0x2004;
    reg {
        name="Lock_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_Clr @ 0x2008;
    reg {
        name="InterruptFlags_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Clr @ 0x200c;
    reg {
        name="InterruptEnable_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Clr @ 0x2010;
    reg {
        name="M33Control_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33Control_Clr @ 0x2020;
    reg {
        name="M33InitNsVector_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33InitNsVector_Clr @ 0x2024;
    reg {
        name="M33InitSVector_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33InitSVector_Clr @ 0x2028;
    reg {
        name="PPU_PriviledgedAttribute0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_PriviledgedAttribute0_Clr @ 0x2040;
    reg {
        name="PPU_PriviledgedAttribute1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_PriviledgedAttribute1_Clr @ 0x2044;
    reg {
        name="PPU_SecureAttribute0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_SecureAttribute0_Clr @ 0x2060;
    reg {
        name="PPU_SecureAttribute1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_SecureAttribute1_Clr @ 0x2064;
    reg {
        name="PPU_Disable0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_Disable0_Clr @ 0x2120;
    reg {
        name="PPU_Disable1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_Disable1_Clr @ 0x2124;
    reg {
        name="PPU_FaultStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_FaultStatus_Clr @ 0x2140;
    reg {
        name="BMPU_PriviledgedAttribute0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_PriviledgedAttribute0_Clr @ 0x2150;
    reg {
        name="BMPU_SecureAttribute0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_SecureAttribute0_Clr @ 0x2170;
    reg {
        name="BMPU_FaultStatus_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_FaultStatus_Clr @ 0x2250;
    reg {
        name="BMPU_FaultStatusAddress_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_FaultStatusAddress_Clr @ 0x2254;
    reg {
        name="ESAU_RegionTypes0_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_RegionTypes0_Clr @ 0x2260;
    reg {
        name="ESAU_RegionTypes1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_RegionTypes1_Clr @ 0x2264;
    reg {
        name="ESAU_MovableRegionBoundary0_1_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary0_1_Clr @ 0x2270;
    reg {
        name="ESAU_MovableRegionBoundary1_2_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary1_2_Clr @ 0x2274;
    reg {
        name="ESAU_MovableRegionBoundary4_5_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary4_5_Clr @ 0x2280;
    reg {
        name="ESAU_MovableRegionBoundary5_6_Clr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary5_6_Clr @ 0x2284;
    reg {
        name="IpVersion_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } IpVersion_Tgl @ 0x3000;
    reg {
        name="Status_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status_Tgl @ 0x3004;
    reg {
        name="Lock_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Lock_Tgl @ 0x3008;
    reg {
        name="InterruptFlags_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlags_Tgl @ 0x300c;
    reg {
        name="InterruptEnable_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable_Tgl @ 0x3010;
    reg {
        name="M33Control_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33Control_Tgl @ 0x3020;
    reg {
        name="M33InitNsVector_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33InitNsVector_Tgl @ 0x3024;
    reg {
        name="M33InitSVector_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } M33InitSVector_Tgl @ 0x3028;
    reg {
        name="PPU_PriviledgedAttribute0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_PriviledgedAttribute0_Tgl @ 0x3040;
    reg {
        name="PPU_PriviledgedAttribute1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_PriviledgedAttribute1_Tgl @ 0x3044;
    reg {
        name="PPU_SecureAttribute0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_SecureAttribute0_Tgl @ 0x3060;
    reg {
        name="PPU_SecureAttribute1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_SecureAttribute1_Tgl @ 0x3064;
    reg {
        name="PPU_Disable0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_Disable0_Tgl @ 0x3120;
    reg {
        name="PPU_Disable1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_Disable1_Tgl @ 0x3124;
    reg {
        name="PPU_FaultStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PPU_FaultStatus_Tgl @ 0x3140;
    reg {
        name="BMPU_PriviledgedAttribute0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_PriviledgedAttribute0_Tgl @ 0x3150;
    reg {
        name="BMPU_SecureAttribute0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_SecureAttribute0_Tgl @ 0x3170;
    reg {
        name="BMPU_FaultStatus_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_FaultStatus_Tgl @ 0x3250;
    reg {
        name="BMPU_FaultStatusAddress_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } BMPU_FaultStatusAddress_Tgl @ 0x3254;
    reg {
        name="ESAU_RegionTypes0_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_RegionTypes0_Tgl @ 0x3260;
    reg {
        name="ESAU_RegionTypes1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_RegionTypes1_Tgl @ 0x3264;
    reg {
        name="ESAU_MovableRegionBoundary0_1_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary0_1_Tgl @ 0x3270;
    reg {
        name="ESAU_MovableRegionBoundary1_2_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary1_2_Tgl @ 0x3274;
    reg {
        name="ESAU_MovableRegionBoundary4_5_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary4_5_Tgl @ 0x3280;
    reg {
        name="ESAU_MovableRegionBoundary5_6_Tgl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ESAU_MovableRegionBoundary5_6_Tgl @ 0x3284;
} Registers_addrmap;


};