addrmap STM32F4_RCC {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="ClockControl";
        regwidth=0x20;
            field {
                sw = rw;
                reset=1'b1;
            } HSION[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
                reset=1'b1;
            } HSIRDY[1:1];
            field {
                sw = rw;
                reset=5'b10000;
            } HSITRIM[7:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=8'b100;
            } HSICAL[15:8];
            field {
                sw = rw;
            } HSEON[16:16];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } HSERDY[17:17];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HSEBYP[18:18];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CSSON[19:19];
            field {
                sw = rw;
            } PLLON[24:24];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } PLLRDY[25:25];
            field {
                sw = rw;
            } PLLI2SON[26:26];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } PLLI2SRDY[27:27];
            field {
                sw = rw;
            } PLLSAION[28:28];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } PLLSAIRDY[29:29];
    } ClockControl @ 0x0;
    reg {
        name="PLLConfiguration";
        regwidth=0x20;
            field {
                sw = rw;
                reset=6'b10000;
            } PLLM[5:0];
            field {
                sw = rw;
                reset=9'b11000000;
            } PLLN[14:6];
            field {
                sw = rw;
            } PLLP[17:16];
            field {
                sw = rw;
            } PLLSRC[22:22];
            field {
                sw = rw;
                reset=4'b100;
            } PLLQ[27:24];
    } PLLConfiguration @ 0x4;
    reg {
        name="ClockConfiguration";
        regwidth=0x20;
            field {
                sw = rw;
            } SW[1:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } SWS[3:2];
            field {
                sw = rw;
            } HPRE[7:4];
            field {
                sw = rw;
            } PPRE1[12:10];
            field {
                sw = rw;
            } PPRE2[15:13];
            field {
                sw = rw;
            } RTCPRE[20:16];
            field {
                sw = rw;
            } MCO1[22:21];
            field {
                sw = rw;
            } I2SSCR[23:23];
            field {
                sw = rw;
            } MCO1PRE[26:24];
            field {
                sw = rw;
            } MCO2PRE[29:27];
            field {
                sw = rw;
            } MCO2[31:30];
    } ClockConfiguration @ 0x8;
    reg {
        name="ClockInterrupt";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ClockInterrupt @ 0xc;
    reg {
        name="AHB1PeripheralReset";
        regwidth=0x20;
            field {
                sw = rw;
            } GPIOxRST[10:0];
            field {
                sw = rw;
            } CRCRST[12:12];
            field {
                sw = rw;
            } DMAxRST[23:21];
            field {
                sw = rw;
            } ETHMACRST[25:25];
            field {
                sw = rw;
            } OTGHSRST[29:29];
    } AHB1PeripheralReset @ 0x10;
    reg {
        name="AHB2PeripheralReset";
        regwidth=0x20;
            field {
                sw = rw;
            } DCMIRST[0:0];
            field {
                sw = rw;
            } CRYPRST[4:4];
            field {
                sw = rw;
            } HASHRST[5:5];
            field {
                sw = rw;
            } RNGRST[6:6];
            field {
                sw = rw;
            } OTGFSRST[7:7];
    } AHB2PeripheralReset @ 0x14;
    reg {
        name="AHB3PeripheralReset";
        regwidth=0x20;
            field {
                sw = rw;
            } FMCRST[0:0];
    } AHB3PeripheralReset @ 0x18;
    reg {
        name="APB1PeripheralReset";
        regwidth=0x20;
            field {
                sw = rw;
            } TIMxRST[8:0];
            field {
                sw = rw;
            } WWDGRST[11:11];
            field {
                sw = rw;
            } SPIxRST[15:14];
            field {
                sw = rw;
            } UARTxRST[20:17];
            field {
                sw = rw;
            } I2CxRST[23:21];
            field {
                sw = rw;
            } CANxRST[26:25];
            field {
                sw = rw;
            } PWRRST[28:28];
            field {
                sw = rw;
            } DACRST[29:29];
            field {
                sw = rw;
            } UARTxRST_[31:30];
    } APB1PeripheralReset @ 0x20;
    reg {
        name="APB2PeripheralReset";
        regwidth=0x20;
            field {
                sw = rw;
            } TIMxRST[1:0];
            field {
                sw = rw;
            } USARTxRST[5:4];
            field {
                sw = rw;
            } ADCRST[8:8];
            field {
                sw = rw;
            } SDIORST[11:11];
            field {
                sw = rw;
            } SPIxRST[13:12];
            field {
                sw = rw;
            } SYSCFGRST[14:14];
            field {
                desc = "This field has the following custom Renode callbacks: Change.";
                sw = rw;
            } TIM9RST[16:16];
            field {
                sw = rw;
            } TIMxRST_[18:17];
            field {
                sw = rw;
            } SPIxRST_[21:20];
            field {
                sw = rw;
            } SAI1RST[22:22];
            field {
                sw = rw;
            } LTDCRST[26:26];
    } APB2PeripheralReset @ 0x24;
    reg {
        name="AHB1PeripheralClockEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } GPIOxEN[10:0];
            field {
                sw = rw;
            } CRCEN[12:12];
            field {
                sw = rw;
            } BKPSRAMEN[18:18];
            field {
                sw = rw;
            } CCMDATARAMEN[20:20];
            field {
                sw = rw;
            } DMAxEN[23:21];
            field {
                sw = rw;
            } ETHMACxEN[28:25];
            field {
                sw = rw;
            } OTGHSxEN[30:29];
    } AHB1PeripheralClockEnable @ 0x30;
    reg {
        name="AHB2PeripheralClockEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } DCMIEN[0:0];
            field {
                sw = rw;
            } CRYPEN[4:4];
            field {
                sw = rw;
            } HASHEN[5:5];
            field {
                sw = rw;
            } RNGEN[6:6];
            field {
                sw = rw;
            } OTGFSEN[7:7];
    } AHB2PeripheralClockEnable @ 0x34;
    reg {
        name="AHB3PeripheralClockEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } FMCEN[0:0];
    } AHB3PeripheralClockEnable @ 0x38;
    reg {
        name="APB1PeripheralClockEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } TIMxEN[8:0];
            field {
                sw = rw;
            } WWDGEN[11:11];
            field {
                sw = rw;
            } SPIxEN[15:14];
            field {
                sw = rw;
            } UARTxEN[20:17];
            field {
                sw = rw;
            } I2CxEN[23:21];
            field {
                sw = rw;
            } CANxEN[26:25];
            field {
                sw = rw;
            } PWREN[28:28];
            field {
                sw = rw;
            } DACEN[29:29];
            field {
                sw = rw;
            } UARTxEN_[31:30];
    } APB1PeripheralClockEnable @ 0x40;
    reg {
        name="APB2PeripheralClockEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } TIMxEN[1:0];
            field {
                sw = rw;
            } USARTxEN[5:4];
            field {
                sw = rw;
            } ADCxEN[10:8];
            field {
                sw = rw;
            } SDIOEN[11:11];
            field {
                sw = rw;
            } SPIxEN[13:12];
            field {
                sw = rw;
            } SYSCFGEN[14:14];
            field {
                sw = rw;
            } TIMxEN_[18:16];
            field {
                sw = rw;
            } SPIxEN_[21:20];
            field {
                sw = rw;
            } SAI1EN[22:22];
            field {
                sw = rw;
            } LTDCEN[26:26];
    } APB2PeripheralClockEnable @ 0x44;
    reg {
        name="AHB1PeripheralClockEnableInLowPowerMode";
        regwidth=0x20;
            field {
                sw = rw;
            } GPIOxLPEN[10:0];
            field {
                sw = rw;
            } CRCLPEN[12:12];
            field {
                sw = rw;
            } FLITFLPEN[15:15];
            field {
                sw = rw;
            } SRAMxLPEN[17:16];
            field {
                sw = rw;
            } BKPSRAMLPEN[18:18];
            field {
                sw = rw;
            } SRAM3LPEN[19:19];
            field {
                sw = rw;
            } DMAxLPEN[23:21];
            field {
                sw = rw;
            } ETHMACxLPEN[28:25];
            field {
                sw = rw;
            } OTGHSxLPEN[30:29];
    } AHB1PeripheralClockEnableInLowPowerMode @ 0x50;
    reg {
        name="AHB2PeripheralClockEnableInLowPowerMode";
        regwidth=0x20;
            field {
                sw = rw;
            } DCMILPEN[0:0];
            field {
                sw = rw;
            } CRYPLPEN[4:4];
            field {
                sw = rw;
            } HASHLPEN[5:5];
            field {
                sw = rw;
            } RNGLPEN[6:6];
            field {
                sw = rw;
            } OTGFSLPEN[7:7];
    } AHB2PeripheralClockEnableInLowPowerMode @ 0x54;
    reg {
        name="AHB3PeripheralClockEnableInLowPowerMode";
        regwidth=0x20;
            field {
                sw = rw;
            } FMCLPEN[0:0];
    } AHB3PeripheralClockEnableInLowPowerMode @ 0x58;
    reg {
        name="APB1PeripheralClockEnableInLowPowerMode";
        regwidth=0x20;
            field {
                sw = rw;
            } TIMxLPEN[8:0];
            field {
                sw = rw;
            } WWDGLPEN[11:11];
            field {
                sw = rw;
            } SPIxLPEN[15:14];
            field {
                sw = rw;
            } UARTxLPEN[20:17];
            field {
                sw = rw;
            } I2CxLPEN[23:21];
            field {
                sw = rw;
            } CANxLPEN[26:25];
            field {
                sw = rw;
            } PWRLPEN[28:28];
            field {
                sw = rw;
            } DACLPEN[29:29];
            field {
                sw = rw;
            } UARTxLPEN_[31:30];
    } APB1PeripheralClockEnableInLowPowerMode @ 0x60;
    reg {
        name="APB2PeripheralClockEnableInLowPowerMode";
        regwidth=0x20;
            field {
                sw = rw;
            } TIMxLPEN[1:0];
            field {
                sw = rw;
            } USARTxLPEN[5:4];
            field {
                sw = rw;
            } ADCxLPEN[10:8];
            field {
                sw = rw;
            } SDIOLPEN[11:11];
            field {
                sw = rw;
            } SPIxLPEN[13:12];
            field {
                sw = rw;
            } SYSCFGLPEN[14:14];
            field {
                sw = rw;
            } TIMxLPEN_[18:16];
            field {
                sw = rw;
            } SPIxLPEN_[21:20];
            field {
                sw = rw;
            } SAI1LPEN[22:22];
            field {
                sw = rw;
            } LTDCLPEN[26:26];
    } APB2PeripheralClockEnableInLowPowerMode @ 0x64;
    reg {
        name="BackupDomainControl";
        regwidth=0x20;
            field {
                sw = rw;
            } LSEON[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } LSERDY[1:1];
            field {
                sw = rw;
            } LSEBYP[2:2];
            field {
                sw = rw;
            } RTCSEL[9:8];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } RTCEN[15:15];
            field {
                sw = rw;
            } BDRST[16:16];
    } BackupDomainControl @ 0x70;
    reg {
        name="ClockControlAndStatus";
        regwidth=0x20;
            field {
                sw = rw;
            } LSION[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } LSIRDY[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RMVF[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } BORRSTF[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } PINRSTF[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } PORRSTF[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SFTRSTF[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IWDGRSTF[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } WWDGRSTF[30:30];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LPWRRSTF[31:31];
    } ClockControlAndStatus @ 0x74;
    reg {
        name="SpreadSpectrumClockGeneration";
        regwidth=0x20;
            field {
                sw = rw;
            } MODPER[12:0];
            field {
                sw = rw;
            } INCSTEP[27:13];
            field {
                sw = rw;
            } SPREADSEL[30:30];
            field {
                sw = rw;
            } SSCGEN[31:31];
    } SpreadSpectrumClockGeneration @ 0x80;
    reg {
        name="PLLI2SConfiguration";
        regwidth=0x20;
            field {
                sw = rw;
                reset=9'b11000000;
            } PLLI2SNx[14:6];
            field {
                sw = rw;
                reset=4'b100;
            } PLLI2SQ[27:24];
            field {
                sw = rw;
                reset=3'b10;
            } PLLI2SRx[30:28];
    } PLLI2SConfiguration @ 0x84;
    reg {
        name="PLLSAIConfiguration";
        regwidth=0x20;
            field {
                sw = rw;
                reset=9'b11000000;
            } PLLSAIN[14:6];
            field {
                sw = rw;
                reset=4'b100;
            } PLLSAIQ[27:24];
            field {
                sw = rw;
                reset=3'b10;
            } PLLSAIR[30:28];
    } PLLSAIConfiguration @ 0x88;
    reg {
        name="DedicatedClockConfiguration";
        regwidth=0x20;
            field {
                sw = rw;
            } PLLI2SDIVQ[4:0];
            field {
                sw = rw;
            } PLLSAIDIVQ[12:8];
            field {
                sw = rw;
            } PLLSAIDIVR[17:16];
            field {
                sw = rw;
            } SAI1ASRC[21:20];
            field {
                sw = rw;
            } SAI1BSRC[23:22];
            field {
                sw = rw;
            } TIMPRE[24:24];
    } DedicatedClockConfiguration @ 0x8c;
} Registers_addrmap;


};