addrmap EFR32_CMU {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Control @ 0x0;
    reg {
        name="HFRCOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFRCOControl @ 0x10;
    reg {
        name="HFRCOLDOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFRCOLDOControl @ 0x14;
    reg {
        name="AUXHFRCOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AUXHFRCOControl @ 0x18;
    reg {
        name="AuxiliaryHFRCOLDOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AuxiliaryHFRCOLDOControl @ 0x1c;
    reg {
        name="LFRCOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LFRCOControl @ 0x20;
    reg {
        name="HFXOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFXOControl @ 0x24;
    reg {
        name="HFXOSTARTUPControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFXOSTARTUPControl @ 0x2c;
    reg {
        name="HFXOSteadyStateControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFXOSteadyStateControl @ 0x30;
    reg {
        name="HFXOTimeoutControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFXOTimeoutControl @ 0x34;
    reg {
        name="LFXOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LFXOControl @ 0x38;
    reg {
        name="ULFRCOControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ULFRCOControl @ 0x3c;
    reg {
        name="DPLLControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DPLLControl @ 0x40;
    reg {
        name="DPLLControl1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DPLLControl1 @ 0x44;
    reg {
        name="CalibrationControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibrationControl @ 0x50;
    reg {
        name="CalibartionCounter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CalibartionCounter @ 0x54;
    reg {
        name="OscillatorEnableDisableCommand";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } HFRCOEN[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } HFRCODIS[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } HFXOEN[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } HFXODIS[3:3];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } AUXHRFCOEN[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } AUXHRFCODIS[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } LFRCOEN[6:6];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } LFRCODIS[7:7];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } LFXOEN[8:8];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } LFXODIS[9:9];
    } OscillatorEnableDisableCommand @ 0x60;
    reg {
        name="Command";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Command @ 0x64;
    reg {
        name="DebugTraceClockSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DebugTraceClockSelect @ 0x70;
    reg {
        name="HighFrequencyClockSelectCommand";
        regwidth=0x20;
            field {
                sw = w;
            } HF[2:0];
    } HighFrequencyClockSelectCommand @ 0x74;
    reg {
        name="LowFrequencyAClockSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyAClockSelect @ 0x80;
    reg {
        name="LowFrequencyBClockSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyBClockSelect @ 0x84;
    reg {
        name="LowFrequencyEClockSelect";
        regwidth=0x20;
            field {
                sw = rw;
            } LFE[2:0];
    } LowFrequencyEClockSelect @ 0x88;
    reg {
        name="Status";
        regwidth=0x20;
            field {
                sw = r;
            } HFRCOENS[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } HFRCORDY[1:1];
            field {
                sw = r;
            } HFXOENS[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } HFXORDY[3:3];
            field {
                sw = r;
            } AUXHRFCOENS[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } AUXHRFCORDY[5:5];
            field {
                sw = r;
            } LFRCOENS[6:6];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } LFRCORDY[7:7];
            field {
                sw = r;
            } LFXOENS[8:8];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } LFXORDY[9:9];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } CALRDY[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HFXOREQ[21:21];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } HFXOPEAKDETRDY[22:22];
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = rw;
            } HFXOSHUNTOPTRDY[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HFXOAMPHIGH[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HFXOAMPLOW[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } HFXOREGILOW[26:26];
    } Status @ 0x90;
    reg {
        name="HighFrequencyClockStatus";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Provider.";
                sw = r;
            } SELECTED[2:0];
    } HighFrequencyClockStatus @ 0x94;
    reg {
        name="HFXOTrimStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFXOTrimStatus @ 0x9c;
    reg {
        name="InterruptFlag";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlag @ 0xa0;
    reg {
        name="InterruptFlagSet";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlagSet @ 0xa4;
    reg {
        name="InterruptFlagClear";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptFlagClear @ 0xa8;
    reg {
        name="InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } InterruptEnable @ 0xac;
    reg {
        name="HighFrequencyBusClockEnable";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CRYPTO0[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CRYPTO1[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LE[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPIO[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRS[4:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LDMA[5:5];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } GPCRC[6:6];
    } HighFrequencyBusClockEnable @ 0xb0;
    reg {
        name="HighFrequencyCoreClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyCoreClockEnable @ 0xb8;
    reg {
        name="HighFrequencyPeripheralClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyPeripheralClockEnable @ 0xc0;
    reg {
        name="HighFrequencyRadioPeripheralClockEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } PROTIMER[0:0];
            field {
                sw = rw;
            } RFSENSE[1:1];
            field {
                sw = rw;
            } RAC[2:2];
            field {
                sw = rw;
            } FRC[3:3];
            field {
                sw = rw;
            } CRC[4:4];
            field {
                sw = rw;
            } SYNTH[5:5];
            field {
                sw = rw;
            } MODEM[6:6];
            field {
                sw = rw;
            } AGC[7:7];
    } HighFrequencyRadioPeripheralClockEnable @ 0xc8;
    reg {
        name="HighFrequencyAlternateRadioPeripheralClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyAlternateRadioPeripheralClockEnable @ 0xcc;
    reg {
        name="HighFrequencyUndividedClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyUndividedClockEnable @ 0xd0;
    reg {
        name="LowFrequencyAClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyAClockEnable @ 0xe0;
    reg {
        name="LowFrequencyBClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyBClockEnable @ 0xe8;
    reg {
        name="LowFrequencyEClockEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyEClockEnable @ 0xf0;
    reg {
        name="HighFrequencyClockPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyClockPrescaler @ 0x100;
    reg {
        name="HighFrequencyCoreClockPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyCoreClockPrescaler @ 0x108;
    reg {
        name="HighFrequencyPeripheralClockPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyPeripheralClockPrescaler @ 0x10c;
    reg {
        name="HighFrequencyRadioPeripheralClockPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyRadioPeripheralClockPrescaler @ 0x110;
    reg {
        name="HighFrequencyExportClockPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyExportClockPrescaler @ 0x114;
    reg {
        name="LowFrequencyAPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyAPrescaler @ 0x120;
    reg {
        name="LowFrequencyBPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyBPrescaler @ 0x128;
    reg {
        name="LowFrequencyEPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyEPrescaler @ 0x130;
    reg {
        name="HighFrequencyAlternateRadioPeripheralClockPrescaler";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyAlternateRadioPeripheralClockPrescaler @ 0x138;
    reg {
        name="SynchronizationBusy";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SynchronizationBusy @ 0x140;
    reg {
        name="Freeze";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Freeze @ 0x144;
    reg {
        name="PCNTControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCNTControl @ 0x150;
    reg {
        name="LVDSControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LVDSControl @ 0x158;
    reg {
        name="ADCControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ADCControl @ 0x15c;
    reg {
        name="RoutingPinEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RoutingPinEnable @ 0x170;
    reg {
        name="RoutingLocation0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RoutingLocation0 @ 0x174;
    reg {
        name="RoutingLocation1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RoutingLocation1 @ 0x178;
    reg {
        name="ConfigurationLoc";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigurationLoc @ 0x180;
    reg {
        name="HFRCOSpreadSpectrum";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFRCOSpreadSpectrum @ 0x184;
    reg {
        name="RadioDeFeaturing";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SYNTHLODIVFREQCTRL[8:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RACIFLILTENABLE[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RACAUXPLL[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMDEC1[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMANTDIVMODE[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RACIFPGAENPGA[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=7'b1111100;
            } RACPASLICE[20:14];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } RACSGPAEN[21:21];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RACPAEN[22:22];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RACPAEN0DBM[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCCONVMODE[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FRCPAUSING[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMDSSS[27:27];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMMODFORMAT[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MODEMDUALSYNC[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } UNLOCKED[31:31];
    } RadioDeFeaturing @ 0x188;
    reg {
        name="HighFrequencyBusClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyBusClockLock @ 0x190;
    reg {
        name="HighFrequencyCoreClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyCoreClockLock @ 0x194;
    reg {
        name="HighFrequencyPeripheralClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyPeripheralClockLock @ 0x198;
    reg {
        name="HighFrequencyRadioPeripheralClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyRadioPeripheralClockLock @ 0x1a4;
    reg {
        name="AlternateRadioPeripheralClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AlternateRadioPeripheralClockLock @ 0x1ac;
    reg {
        name="HighFrequencyUndividedClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HighFrequencyUndividedClockLock @ 0x1b0;
    reg {
        name="LowFrequencyAClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyAClockLock @ 0x1b4;
    reg {
        name="LowFrequencyBClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyBClockLock @ 0x1bc;
    reg {
        name="LowFrequencyEClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LowFrequencyEClockLock @ 0x1c4;
    reg {
        name="PCNTClockLock";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PCNTClockLock @ 0x1cc;
    reg {
        name="Test";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Test @ 0x1d0;
    reg {
        name="HFRCOTestControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFRCOTestControl @ 0x1d4;
    reg {
        name="AUXHRCOTestControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AUXHRCOTestControl @ 0x1d8;
    reg {
        name="LFRCOTestControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LFRCOTestControl @ 0x1dc;
    reg {
        name="HFXOTestControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } HFXOTestControl @ 0x1e0;
    reg {
        name="LFXOTestControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } LFXOTestControl @ 0x1e4;
    reg {
        name="DPLLOffset";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DPLLOffset @ 0x1fc;
} Registers_addrmap;


};