addrmap OpenTitan_ROMController {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="AlertTest";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = w;
            } fatal[0:0];
    } AlertTest @ 0x0;
    reg {
        name="FatalAlertCause";
        regwidth=0x20;
            field {
                sw = r;
            } checker_error[0:0];
            field {
                sw = r;
            } integrity_error[1:1];
    } FatalAlertCause @ 0x4;
    reg {
        name="Digest0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Digest0 @ 0x8;
    reg {
        name="Digest1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Digest1 @ 0xc;
    reg {
        name="Digest2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Digest2 @ 0x10;
    reg {
        name="Digest3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Digest3 @ 0x14;
    reg {
        name="Digest4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Digest4 @ 0x18;
    reg {
        name="Digest5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Digest5 @ 0x1c;
    reg {
        name="Digest6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Digest6 @ 0x20;
    reg {
        name="Digest7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Digest7 @ 0x24;
    reg {
        name="ExpectedDigest0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExpectedDigest0 @ 0x28;
    reg {
        name="ExpectedDigest1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExpectedDigest1 @ 0x2c;
    reg {
        name="ExpectedDigest2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExpectedDigest2 @ 0x30;
    reg {
        name="ExpectedDigest3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExpectedDigest3 @ 0x34;
    reg {
        name="ExpectedDigest4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExpectedDigest4 @ 0x38;
    reg {
        name="ExpectedDigest5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExpectedDigest5 @ 0x3c;
    reg {
        name="ExpectedDigest6";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExpectedDigest6 @ 0x40;
    reg {
        name="ExpectedDigest7";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ExpectedDigest7 @ 0x44;
} Registers_addrmap;


};