addrmap RenesasRA_GPT {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="WriteProtection";
        regwidth=0x20;
            field {
                sw = rw;
            } WP_Register_Write_Disable[0:0];
            field {
                sw = rw;
            } STRWP_CSTRT_Bit_Write_Disable[1:1];
            field {
                sw = rw;
            } STPWP_CSTOP_Bit_Write_Disable[2:2];
            field {
                sw = rw;
            } CLRWP_CCLR_Bit_Write_Disable[3:3];
            field {
                sw = rw;
            } CMNWP_Common_Register_Write_Disable[4:4];
            field {
                sw = rw;
            } PRKEY_GTWP_Key_Code[15:8];
    } WriteProtection @ 0x0;
    reg {
        name="SoftwareStart";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } CSTRT[0:0];
    } SoftwareStart @ 0x4;
    reg {
        name="SoftwareStop";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } CSTOP[0:0];
    } SoftwareStop @ 0x8;
    reg {
        name="SoftwareClear";
        regwidth=0x20;
            field {
                sw = rw;
            } CCLR[13:0];
    } SoftwareClear @ 0xc;
    reg {
        name="StartSourceSelect";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } StartSourceSelect @ 0x10;
    reg {
        name="StopSourceSelect";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } StopSourceSelect @ 0x14;
    reg {
        name="ClearSourceSelect";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } ClearSourceSelect @ 0x18;
    reg {
        name="UpCountSourceSelect";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } UpCountSourceSelect @ 0x1c;
    reg {
        name="DownCountSourceSelect";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } DownCountSourceSelect @ 0x20;
    reg {
        name="InputCaptureSourceSelectA";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } InputCaptureSourceSelectA @ 0x24;
    reg {
        name="InputCaptureSourceSelectB";
        regwidth=0x20;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[31:0];
    } InputCaptureSourceSelectB @ 0x28;
    reg {
        name="TimerControl";
        regwidth=0x20;
            field {
                sw = rw;
            } CST_Count_Start[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } MD_Mode_Select[18:16];
            field {
                sw = rw;
            } TPCS_Timer_Prescaler_Select[26:23];
    } TimerControl @ 0x2c;
    reg {
        name="CountDirectionAndDutySetting";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } UD_Count_Direction_Setting[0:0];
            field {
                sw = rw;
            } UDF_Forcible_Count_Direction_Setting[1:1];
            field {
                sw = rw;
            } OADTY_GTIOCnA_Output_Duty_Setting[17:16];
            field {
                sw = rw;
            } OADTYF_Forcible_GTIOCnA_Output_Duty_Setting[18:18];
            field {
                sw = rw;
            } OADTYR_GTIOCnA_Output_Value_Selecting[19:19];
            field {
                sw = rw;
            } OBDTY_GTIOCnB_Output_Duty_Setting[25:24];
            field {
                sw = rw;
            } OBDTYF_Forcible_GTIOCnB_Output_Duty_Setting[26:26];
            field {
                sw = rw;
            } OBDTYR_GTIOCnB_Output_Value_Selecting[27:27];
    } CountDirectionAndDutySetting @ 0x30;
    reg {
        name="IOControl";
        regwidth=0x20;
            field {
                sw = rw;
            } GTIOA_GTIOCnA_Pin_Function_Select[4:0];
            field {
                sw = rw;
            } OADFLT_GTIOCnA_Pin_Output_Value_Setting_at_the_Count_Stop[6:6];
            field {
                sw = rw;
            } OAHLD_GTIOCnA_Pin_Output_Value_Setting_at_the_Start_Stop_Count[7:7];
            field {
                sw = rw;
            } OAE_GTIOCnA_Pin_Output_Enable[8:8];
            field {
                sw = rw;
            } OADF_GTIOCnA_Pin_Disaable_Value_Setting[9:9];
            field {
                sw = rw;
            } NFAEN_Noise_Filter_A_Enable[13:13];
            field {
                sw = rw;
            } NFCSA_Noise_Filter_A_Sampling_Clock_Select[15:14];
            field {
                sw = rw;
            } GTIOB_GTIOCnB_Pin_Function_Select[20:16];
            field {
                sw = rw;
            } OBDFLT_GTIOCnB_Pin_Output_Value_Setting_at_the_Count_Stop[22:22];
            field {
                sw = rw;
            } OBHLD_GTIOCnB_Pin_Output_Value_Setting_at_the_Start_Stop_Count[23:23];
            field {
                sw = rw;
            } OBE_GTIOCnB_Pin_Output_Enable[24:24];
            field {
                sw = rw;
            } OBDF_GTIOCnB_Pin_Disaable_Value_Setting[25:25];
            field {
                sw = rw;
            } NFBEN_Noise_Filter_B_Enable[29:29];
            field {
                sw = rw;
            } NFCSB_Noise_Filter_B_Sampling_Clock_Select[31:30];
    } IOControl @ 0x34;
    reg {
        name="InterruptOutputSetting";
        regwidth=0x20;
            field {
                sw = rw;
            } ADTRAUEN_GTADTRA_Register_Compare_Match_Up_Counting_A_D_Conversion_Start[16:16];
            field {
                sw = rw;
            } ADTRADEN_GTADTRA_Register_Compare_Match_Down_Counting_A_D_Conversion_Start[17:17];
            field {
                sw = rw;
            } ADTRBUEN_GTADTRB_Register_Compare_Match_Up_Counting_A_D_Conversion_Start[18:18];
            field {
                sw = rw;
            } ADTRBDEN_GTADTRB_Register_Compare_Match_Down_Counting_A_D_Conversion_Start[19:19];
            field {
                sw = rw;
            } GRP_Output_Disable_Source_Select[25:24];
            field {
                sw = rw;
            } GRPABH_Same_Time_Output_Level_High_Disable_Request_Enable[29:29];
            field {
                sw = rw;
            } GRPABL_Same_Time_Output_Level_Low_Disable_Request_Enable[30:30];
    } InterruptOutputSetting @ 0x38;
    reg {
        name="Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Status @ 0x3c;
    reg {
        name="BufferEnable";
        regwidth=0x20;
            field {
                sw = rw;
            } BD0_GTCCR_Buffer_Operation_Disable[0:0];
            field {
                sw = rw;
            } BD1_GTPR_Buffer_Operation_Disable[1:1];
            field {
                sw = rw;
            } BD2_GTAADTRA_GTADTRB_Registers_Buffer_Operation_Disable[2:2];
            field {
                sw = rw;
            } CCRA_GTCCRA_Buffer_Operation[17:16];
            field {
                sw = rw;
            } CCRB_GTCCRB_Buffer_Operation[19:18];
            field {
                sw = rw;
            } PR_GTPR_Buffer_Operation[21:20];
            field {
                sw = rw;
            } CCRSWT_GTCCRA_and_GTCCRB_Forcible_Buffer_Operation[22:22];
            field {
                sw = rw;
            } ADTTA_GTADTRA_Register_Buffer_Transfer_Timing_Select[25:24];
            field {
                sw = rw;
            } ADTDA_GTADTRA_Register_Double_Buffer_Operation[26:26];
            field {
                sw = rw;
            } ADTTB_GTADTRB_Register_Buffer_Transfer_Timing_Select[29:28];
            field {
                sw = rw;
            } ADTDB_GTADTRB_Register_Double_Buffer_Operation[30:30];
    } BufferEnable @ 0x40;
    reg {
        name="Counter";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } GTCNT[31:0];
    } Counter @ 0x48;
    reg {
        name="CompareCaptureA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CompareCaptureA @ 0x4c;
    reg {
        name="CycleSetting";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write, Provider.";
                sw = rw;
            } GTPR[31:0];
    } CycleSetting @ 0x64;
    reg {
        name="CycleSettingBuffer";
        regwidth=0x20;
            field {
                sw = rw;
            } GTPBR[31:0];
    } CycleSettingBuffer @ 0x68;
    reg {
        name="ADConversionStartA";
        regwidth=0x20;
            field {
                sw = rw;
            } GTADTRA[31:0];
    } ADConversionStartA @ 0x70;
    reg {
        name="ADConversionStartBufferA";
        regwidth=0x20;
            field {
                sw = rw;
            } GTADTBRA[31:0];
    } ADConversionStartBufferA @ 0x74;
    reg {
        name="ADConversionStartDoubleBufferA";
        regwidth=0x20;
            field {
                sw = rw;
            } GTADTDBRA[31:0];
    } ADConversionStartDoubleBufferA @ 0x78;
    reg {
        name="ADConversionStartB";
        regwidth=0x20;
            field {
                sw = rw;
            } GTADTRB[31:0];
    } ADConversionStartB @ 0x7c;
    reg {
        name="ADConversionStartBufferB";
        regwidth=0x20;
            field {
                sw = rw;
            } GTADTBRB[31:0];
    } ADConversionStartBufferB @ 0x80;
    reg {
        name="ADConversionStartDoubleBufferB";
        regwidth=0x20;
            field {
                sw = rw;
            } GTADTDBRB[31:0];
    } ADConversionStartDoubleBufferB @ 0x84;
    reg {
        name="DeadTimeControl";
        regwidth=0x20;
            field {
                sw = rw;
            } TDE_Negative_Phase_Waveform_Setting[0:0];
    } DeadTimeControl @ 0x88;
    reg {
        name="DeadTimeValue";
        regwidth=0x20;
            field {
                sw = rw;
            } GTDVU[31:0];
    } DeadTimeValue @ 0x8c;
    reg {
        name="ADConversionStartSignalMonitoring";
        regwidth=0x20;
            field {
                sw = rw;
            } ADSMS0_A_D_Conversion_Start_Request_Signal_Monitor_0_Selection[1:0];
            field {
                sw = rw;
            } ADSMEN0_A_D_Conversion_Start_Request_Signal_Monitor_0_Output_Enabling[8:8];
            field {
                sw = rw;
            } ADSMS1_A_D_Conversion_Start_Request_Signal_Monitor_1_Selection[17:16];
            field {
                sw = rw;
            } ADSMEN1_A_D_Conversion_Start_Request_Signal_Monitor_1_Output_Enabling[24:24];
    } ADConversionStartSignalMonitoring @ 0xa4;
    reg {
        name="InterChannelSetting";
        regwidth=0x20;
            field {
                sw = rw;
            } ICLFA_GTIOCnA_Output_Logical_Operation_Function_Select[2:0];
            field {
                sw = rw;
            } ICLFSELC_Inter_Channel_Signaal_C_Select[9:4];
            field {
                sw = rw;
            } ICLFB_GTIOCnB_Output_Logical_Operation_Function_Select[18:16];
            field {
                sw = rw;
            } ICLFSELD_Inter_Channel_Signal_D_Select[25:20];
    } InterChannelSetting @ 0xb8;
    reg {
        name="PeriodCount";
        regwidth=0x20;
            field {
                sw = rw;
            } PCEN_Period_Count_Function_Enable[0:0];
            field {
                sw = rw;
            } ASTP_Automatic_Stop_Function_Enable[8:8];
            field {
                sw = rw;
            } PCNT_Period_Counter[27:16];
    } PeriodCount @ 0xbc;
    reg {
        name="OperationEnableBitChannelSelect";
        regwidth=0x20;
            field {
                sw = rw;
            } SECSEL[13:0];
    } OperationEnableBitChannelSelect @ 0xd0;
    reg {
        name="OperationEnableBit";
        regwidth=0x20;
            field {
                sw = rw;
            } SBDCE_GTCCR_Register_Buffer_Operation_Simultaneous_Enable[0:0];
            field {
                sw = rw;
            } SBDPE_GTPR_Register_Buffer_Operation_Simultaneous_Enable[1:1];
            field {
                sw = rw;
            } SBDAE_GTADTR_Register_Buffer_Operation_Simultaneous_Enable[2:2];
            field {
                sw = rw;
            } SBDCD_GTCCR_Register_Buffer_Operation_Simultaneous_Disable[8:8];
            field {
                sw = rw;
            } SBDPD_GTPR_Register_Buffer_Operation_Simultaneous_Disable[9:9];
            field {
                sw = rw;
            } SBDAD_GTADTR_Register_Buffer_Operation_Simultaneous_Disable[10:10];
    } OperationEnableBit @ 0xd4;
} ChannelRegisters_addrmap;
addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="OutputPhaseSwitchingControl";
        regwidth=0x20;
            field {
                sw = rw;
            } UF_Input_Phase_Soft_Setting[0:0];
            field {
                sw = rw;
            } VF_Input_Phase_Soft_Setting[1:1];
            field {
                sw = rw;
            } WF_Input_Phase_Soft_Setting[2:2];
            field {
                sw = rw;
            } U_Input_U_Phase_Monitor[4:4];
            field {
                sw = rw;
            } V_Input_V_Phase_Monitor[5:5];
            field {
                sw = rw;
            } W_Input_W_Phase_Monitor[6:6];
            field {
                sw = rw;
            } EN_Output_Phase_Enable[8:8];
            field {
                sw = rw;
            } FB_External_Feedback_Signal_Enable[16:16];
            field {
                sw = rw;
            } P_Positive_Phase_Output_P_Control[17:17];
            field {
                sw = rw;
            } N_Negative_Phase_Output_N_Control[18:18];
            field {
                sw = rw;
            } INV_Output_Phase_Invert_Control[19:19];
            field {
                sw = rw;
            } RV_Output_Phase_Rotation_Direction_Reversal_Control[20:20];
            field {
                sw = rw;
            } ALIGN_Input_Phase_Alignment[21:21];
            field {
                sw = rw;
            } GRP_Output_Disabled_Source_Selection[25:24];
            field {
                sw = rw;
            } GODF_Group_Output_Disable_Function[26:26];
            field {
                sw = rw;
            } NFEN_External_Input_Noise_Filter_Enable[29:29];
            field {
                sw = rw;
            } NFCS_External_Input_Noise_Filter_Clock_Selection[31:30];
    } OutputPhaseSwitchingControl @ 0x0;
} CommonRegisters_addrmap;


};