addrmap MPFS_Sysreg {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Temp0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Temp0 @ 0x0;
    reg {
        name="Temp1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Temp1 @ 0x4;
    reg {
        name="ClockConfigCr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=32'b10000;
            } ClockConfig[31:0];
    } ClockConfigCr @ 0x8;
    reg {
        name="RtcClockCr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=32'b1000001100100;
            } RtcClock[31:0];
    } RtcClockCr @ 0xc;
    reg {
        name="FabricResetCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FabricResetCr @ 0x10;
    reg {
        name="BootFailC";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } BootFail[31:0];
    } BootFailC @ 0x14;
    reg {
        name="MssLowPowerCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssLowPowerCr @ 0x18;
    reg {
        name="ConfigLockCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ConfigLockCr @ 0x1c;
    reg {
        name="ResetSr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ResetSr @ 0x20;
    reg {
        name="DeviceStatus";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=32'b1111100001001;
            } Devicestatus[31:0];
    } DeviceStatus @ 0x24;
    reg {
        name="FabIntenU541";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FabIntenU541 @ 0x40;
    reg {
        name="FabIntenU542";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FabIntenU542 @ 0x44;
    reg {
        name="FabIntenU543";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FabIntenU543 @ 0x48;
    reg {
        name="FabIntenU544";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FabIntenU544 @ 0x4c;
    reg {
        name="FabIntenMisc";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FabIntenMisc @ 0x50;
    reg {
        name="GpioInterruptFabCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GpioInterruptFabCr @ 0x54;
    reg {
        name="ApbbusCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ApbbusCr @ 0x80;
    reg {
        name="SubblkClockCr";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } ENVM[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MAC0[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MAC1[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MMC[3:3];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } TIMER[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MMUART0[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MMUART1[6:6];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MMUART2[7:7];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MMUART3[8:8];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MMUART4[9:9];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } SPI0[10:10];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } SPI1[11:11];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } I2C0[12:12];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } I2C1[13:13];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } CAN0[14:14];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } CAN1[15:15];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } USB[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FPGA[17:17];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } MSRTC[18:18];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } QSPI[19:19];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } GPIO0[20:20];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } GPIO1[21:21];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } GPIO2[22:22];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } DDRC[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FIC0[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FIC1[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FIC2[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } FIC3[27:27];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } ATHENA[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFM[29:29];
    } SubblkClockCr @ 0x84;
    reg {
        name="SoftResetCr";
        regwidth=0x20;
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } ENVM[0:0];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MAC0[1:1];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MAC1[2:2];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MMC[3:3];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } TIMER[4:4];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MMUART0[5:5];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MMUART1[6:6];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MMUART2[7:7];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MMUART3[8:8];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MMUART4[9:9];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } SPI0[10:10];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } SPI1[11:11];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } I2C0[12:12];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } I2C1[13:13];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } CAN0[14:14];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } CAN1[15:15];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } USB[16:16];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } FPGA[17:17];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } MSRTC[18:18];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } QSPI[19:19];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } GPIO0[20:20];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } GPIO1[21:21];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } GPIO2[22:22];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } DDRC[23:23];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } FIC0[24:24];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } FIC1[25:25];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } FIC2[26:26];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } FIC3[27:27];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
                reset=1'b1;
            } ATHENA[28:28];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } CFM[29:29];
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=1'b1;
            } SGMII[30:30];
    } SoftResetCr @ 0x88;
    reg {
        name="AhbaxiCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } AhbaxiCr @ 0x8c;
    reg {
        name="DfiapbCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } DfiapbCr @ 0x98;
    reg {
        name="GpioCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } GpioCr @ 0x9c;
    reg {
        name="Mac0Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Mac0Cr @ 0xa4;
    reg {
        name="Mac1Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Mac1Cr @ 0xa8;
    reg {
        name="UsbCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } UsbCr @ 0xac;
    reg {
        name="MeshCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MeshCr @ 0xb0;
    reg {
        name="MeshSeedCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MeshSeedCr @ 0xb4;
    reg {
        name="EnvmCr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=32'b11111111;
            } Envm[31:0];
    } EnvmCr @ 0xb8;
    reg {
        name="ReservedBc";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } ReservedBc @ 0xbc;
    reg {
        name="QosPeripheralCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } QosPeripheralCr @ 0xc0;
    reg {
        name="QosCplexioCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } QosCplexioCr @ 0xc4;
    reg {
        name="QosCplexddrCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } QosCplexddrCr @ 0xc8;
    reg {
        name="MpuViolationSr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MpuViolation[31:0];
    } MpuViolationSr @ 0xf0;
    reg {
        name="MpuViolationIntenCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MpuViolationIntenCr @ 0xf4;
    reg {
        name="SwFailAddr0Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SwFailAddr0Cr @ 0xf8;
    reg {
        name="SwFailAddr1Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SwFailAddr1Cr @ 0xfc;
    reg {
        name="EdacSr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Edac[31:0];
    } EdacSr @ 0x100;
    reg {
        name="EdacIntenCr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EdacInten[31:0];
    } EdacIntenCr @ 0x104;
    reg {
        name="EdacCntMmc";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EdacCntMmc[31:0];
    } EdacCntMmc @ 0x108;
    reg {
        name="EdacCntDdrc";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EdacCntDrdc[31:0];
    } EdacCntDdrc @ 0x10c;
    reg {
        name="EdacCntMac0";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EdacCntMac0[31:0];
    } EdacCntMac0 @ 0x110;
    reg {
        name="EdacCntMac1";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EdacCntMac1[31:0];
    } EdacCntMac1 @ 0x114;
    reg {
        name="EdacCntUsb";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EdacCntUsb[31:0];
    } EdacCntUsb @ 0x118;
    reg {
        name="EdacCntCan0";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EdacCntCan0[31:0];
    } EdacCntCan0 @ 0x11c;
    reg {
        name="EdacCntCan1";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } EdacCntCan1[31:0];
    } EdacCntCan1 @ 0x120;
    reg {
        name="EdacInjectCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } EdacInjectCr @ 0x124;
    reg {
        name="MaintenanceIntenCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MaintenanceIntenCr @ 0x140;
    reg {
        name="PllStatusIntenCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PllStatusIntenCr @ 0x144;
    reg {
        name="MaintenanceIntSr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } MaintenanceInt[31:0];
    } MaintenanceIntSr @ 0x148;
    reg {
        name="PllStatusSr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
                reset=32'b11100000111;
            } PllStatus[31:0];
    } PllStatusSr @ 0x14c;
    reg {
        name="CfmTimerCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } CfmTimerCr @ 0x150;
    reg {
        name="MiscSr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } Misc[31:0];
    } MiscSr @ 0x154;
    reg {
        name="DLLStatusSr";
        regwidth=0x20;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DLLStatus[31:0];
    } DLLStatusSr @ 0x15c;
    reg {
        name="RamLightsleepCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RamLightsleepCr @ 0x168;
    reg {
        name="RamDeepsleepCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RamDeepsleepCr @ 0x16c;
    reg {
        name="RamShutdownCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } RamShutdownCr @ 0x170;
    reg {
        name="Iomux0Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iomux0Cr @ 0x200;
    reg {
        name="Iomux1Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iomux1Cr @ 0x204;
    reg {
        name="Iomux2Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iomux2Cr @ 0x208;
    reg {
        name="Iomux3Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iomux3Cr @ 0x20c;
    reg {
        name="Iomux4Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iomux4Cr @ 0x210;
    reg {
        name="Iomux5Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iomux5Cr @ 0x214;
    reg {
        name="Iomux6Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Iomux6Cr @ 0x218;
    reg {
        name="MssioBank4CfgCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank4CfgCr @ 0x230;
    reg {
        name="MssioBank4IoCfg0Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank4IoCfg0Cr @ 0x234;
    reg {
        name="MssioBank4IoCfg1Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank4IoCfg1Cr @ 0x238;
    reg {
        name="MssioBank4IoCfg2Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank4IoCfg2Cr @ 0x23c;
    reg {
        name="MssioBank4IoCfg3Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank4IoCfg3Cr @ 0x240;
    reg {
        name="MssioBank4IoCfg4Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank4IoCfg4Cr @ 0x244;
    reg {
        name="MssioBank4IoCfg5Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank4IoCfg5Cr @ 0x248;
    reg {
        name="MssioBank4IoCfg6Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank4IoCfg6Cr @ 0x24c;
    reg {
        name="MssioBank2CfgCr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2CfgCr @ 0x250;
    reg {
        name="MssioBank2IoCfg0Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg0Cr @ 0x254;
    reg {
        name="MssioBank2IoCfg1Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg1Cr @ 0x258;
    reg {
        name="MssioBank2IoCfg2Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg2Cr @ 0x25c;
    reg {
        name="MssioBank2IoCfg3Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg3Cr @ 0x260;
    reg {
        name="MssioBank2IoCfg4Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg4Cr @ 0x264;
    reg {
        name="MssioBank2IoCfg5Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg5Cr @ 0x268;
    reg {
        name="MssioBank2IoCfg6Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg6Cr @ 0x26c;
    reg {
        name="MssioBank2IoCfg7Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg7Cr @ 0x270;
    reg {
        name="MssioBank2IoCfg8Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg8Cr @ 0x274;
    reg {
        name="MssioBank2IoCfg9Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg9Cr @ 0x278;
    reg {
        name="MssioBank2IoCfg10Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg10Cr @ 0x27c;
    reg {
        name="MssioBank2IoCfg11Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssioBank2IoCfg11Cr @ 0x280;
    reg {
        name="MssSpare0Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssSpare0Cr @ 0x2a8;
    reg {
        name="MssSpare1Cr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssSpare1Cr @ 0x2ac;
    reg {
        name="MssSpare0Sr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssSpare0Sr @ 0x2b0;
    reg {
        name="MssSpare1Sr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssSpare1Sr @ 0x2b4;
    reg {
        name="MssSpare2Sr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssSpare2Sr @ 0x2b8;
    reg {
        name="MssSpare3Sr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssSpare3Sr @ 0x2bc;
    reg {
        name="MssSpare4Sr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssSpare4Sr @ 0x2c0;
    reg {
        name="MssSpare5Sr";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MssSpare5Sr @ 0x2c4;
    reg {
        name="SpareRegisterRw";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SpareRegisterRw @ 0x2d0;
    reg {
        name="SpareRegisterW1p";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SpareRegisterW1p @ 0x2d4;
    reg {
        name="SpareRegisterRo";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SpareRegisterRo @ 0x2d8;
    reg {
        name="SparePerimRw";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SparePerimRw @ 0x2dc;
} Registers_addrmap;


};