addrmap IMXRT_PWM {

addrmap {
    desc = "Generated by RenodeModelsAnalyzer";
    reg {
        name="Submodule0Counter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0Counter @ 0x0;
    reg {
        name="Submodule0InitialCount";
        regwidth=0x10;
            field {
                sw = rw;
            } INIT___Initial_Count_Register_Bits[15:0];
    } Submodule0InitialCount @ 0x2;
    reg {
        name="Submodule0Control2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0Control2 @ 0x4;
    reg {
        name="Submodule0Control";
        regwidth=0x10;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DBLEN___Double_Switching_Enable[0:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DBLX___PWMX_Double_Switching_Enable[1:1];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LDMOD___Load_Mode_Select[2:2];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } SPLIT___Split_the_DBLPWM_signal_to_PWMA_and_PWMB[3:3];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } PRSC___Prescaler[6:4];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } COMPMODE___Compare_Mode[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } DT___Deadtime[9:8];
            field {
                sw = rw;
            } FULL___Full_Cycle_Reload[10:10];
            field {
                sw = rw;
            } HALF___Half_Cycle_Reload[11:11];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LDFQ___Load_Frequency[15:12];
    } Submodule0Control @ 0x6;
    reg {
        name="Submodule0Value0";
        regwidth=0x10;
            field {
                sw = rw;
            } VAL0___Value_Register_0[15:0];
    } Submodule0Value0 @ 0xa;
    reg {
        name="Submodule0FractionalValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0FractionalValue1 @ 0xc;
    reg {
        name="Submodule0Value1";
        regwidth=0x10;
            field {
                sw = rw;
            } VAL1___Value_Register_1[15:0];
    } Submodule0Value1 @ 0xe;
    reg {
        name="Submodule0FractionalValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0FractionalValue2 @ 0x10;
    reg {
        name="Submodule0Value2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0Value2 @ 0x12;
    reg {
        name="Submodule0FractionalValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0FractionalValue3 @ 0x14;
    reg {
        name="Submodule0Value3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0Value3 @ 0x16;
    reg {
        name="Submodule0FractionalValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0FractionalValue4 @ 0x18;
    reg {
        name="Submodule0Value4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0Value4 @ 0x1a;
    reg {
        name="Submodule0FractionalValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0FractionalValue5 @ 0x1c;
    reg {
        name="Submodule0Value5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0Value5 @ 0x1e;
    reg {
        name="Submodule0FractionalControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0FractionalControl @ 0x20;
    reg {
        name="Submodule0OutputControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0OutputControl @ 0x22;
    reg {
        name="Submodule0Status";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x10;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CMPF___Compare_Flags[5:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFX0___Capture_Flag_X0[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFX1___Capture_Flag_X1[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFB0___Capture_Flag_B0[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFB1___Capture_Flag_B1[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFA0___Capture_Flag_A0[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CFA1___Capture_Flag_A1[11:11];
            field {
                sw = rw;
                onwrite = woclr;
            } RF___Reload_Flag[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } REF___Reload_Error_Flag[13:13];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } RUF___Registers_Updated_Flag[14:14];
    } Submodule0Status @ 0x24;
    reg {
        name="Submodule0InterruptEnable";
        desc = "This register has the following custom Renode callbacks: Write";
        regwidth=0x10;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CMPIE___Compare_Interrupt_Enables[5:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CX0IE___Capture_X_0_Interrupt_Enable[6:6];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CX1IE___Capture_X_1_Interrupt_Enable[7:7];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CB0IE___Capture_B_0_Interrupt_Enable[8:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CB1IE___Capture_B_1_Interrupt_Enable[9:9];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CA0IE___Capture_A_0_Interrupt_Enable[10:10];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CA1IE___Capture_A_1_Interrupt_Enable[11:11];
            field {
                sw = rw;
            } RIE___Reload_Interrupt_Enable[12:12];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } REIE___Reload_Error_Interrupt_Enable[13:13];
    } Submodule0InterruptEnable @ 0x26;
    reg {
        name="Submodule0DMAEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0DMAEnable @ 0x28;
    reg {
        name="Submodule0OutputTriggerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0OutputTriggerControl @ 0x2a;
    reg {
        name="Submodule0FaultDisableMapping0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0FaultDisableMapping0 @ 0x2c;
    reg {
        name="Submodule0FaultDisableMapping1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0FaultDisableMapping1 @ 0x2e;
    reg {
        name="Submodule0DeadtimeCount0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0DeadtimeCount0 @ 0x30;
    reg {
        name="Submodule0DeadtimeCount1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0DeadtimeCount1 @ 0x32;
    reg {
        name="Submodule0CaptureControlA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureControlA @ 0x34;
    reg {
        name="Submodule0CaptureCompareA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureCompareA @ 0x36;
    reg {
        name="Submodule0CaptureControlB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureControlB @ 0x38;
    reg {
        name="Submodule0CaptureCompareB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureCompareB @ 0x3a;
    reg {
        name="Submodule0CaptureControlX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureControlX @ 0x3c;
    reg {
        name="Submodule0CaptureCompareX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureCompareX @ 0x3e;
    reg {
        name="Submodule0CaptureValue0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue0 @ 0x40;
    reg {
        name="Submodule0CaptureValue0Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue0Cycle @ 0x42;
    reg {
        name="Submodule0CaptureValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue1 @ 0x44;
    reg {
        name="Submodule0CaptureValue1Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue1Cycle @ 0x46;
    reg {
        name="Submodule0CaptureValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue2 @ 0x48;
    reg {
        name="Submodule0CaptureValue2Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue2Cycle @ 0x4a;
    reg {
        name="Submodule0CaptureValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue3 @ 0x4c;
    reg {
        name="Submodule0CaptureValue3Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue3Cycle @ 0x4e;
    reg {
        name="Submodule0CaptureValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue4 @ 0x50;
    reg {
        name="Submodule0CaptureValue4Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue4Cycle @ 0x52;
    reg {
        name="Submodule0CaptureValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue5 @ 0x54;
    reg {
        name="Submodule0CaptureValue5Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule0CaptureValue5Cycle @ 0x56;
    reg {
        name="Submodule1Counter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Counter @ 0x60;
    reg {
        name="Submodule1InitialCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1InitialCount @ 0x62;
    reg {
        name="Submodule1Control2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Control2 @ 0x64;
    reg {
        name="Submodule1Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Control @ 0x66;
    reg {
        name="Submodule1Value0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Value0 @ 0x6a;
    reg {
        name="Submodule1FractionalValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1FractionalValue1 @ 0x6c;
    reg {
        name="Submodule1Value1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Value1 @ 0x6e;
    reg {
        name="Submodule1FractionalValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1FractionalValue2 @ 0x70;
    reg {
        name="Submodule1Value2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Value2 @ 0x72;
    reg {
        name="Submodule1FractionalValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1FractionalValue3 @ 0x74;
    reg {
        name="Submodule1Value3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Value3 @ 0x76;
    reg {
        name="Submodule1FractionalValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1FractionalValue4 @ 0x78;
    reg {
        name="Submodule1Value4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Value4 @ 0x7a;
    reg {
        name="Submodule1FractionalValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1FractionalValue5 @ 0x7c;
    reg {
        name="Submodule1Value5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Value5 @ 0x7e;
    reg {
        name="Submodule1FractionalControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1FractionalControl @ 0x80;
    reg {
        name="Submodule1OutputControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1OutputControl @ 0x82;
    reg {
        name="Submodule1Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1Status @ 0x84;
    reg {
        name="Submodule1InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1InterruptEnable @ 0x86;
    reg {
        name="Submodule1DMAEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1DMAEnable @ 0x88;
    reg {
        name="Submodule1OutputTriggerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1OutputTriggerControl @ 0x8a;
    reg {
        name="Submodule1FaultDisableMapping0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1FaultDisableMapping0 @ 0x8c;
    reg {
        name="Submodule1FaultDisableMapping1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1FaultDisableMapping1 @ 0x8e;
    reg {
        name="Submodule1DeadtimeCount0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1DeadtimeCount0 @ 0x90;
    reg {
        name="Submodule1DeadtimeCount1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1DeadtimeCount1 @ 0x92;
    reg {
        name="Submodule1CaptureControlA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureControlA @ 0x94;
    reg {
        name="Submodule1CaptureCompareA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureCompareA @ 0x96;
    reg {
        name="Submodule1CaptureControlB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureControlB @ 0x98;
    reg {
        name="Submodule1CaptureCompareB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureCompareB @ 0x9a;
    reg {
        name="Submodule1CaptureControlX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureControlX @ 0x9c;
    reg {
        name="Submodule1CaptureCompareX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureCompareX @ 0x9e;
    reg {
        name="Submodule1CaptureValue0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue0 @ 0xa0;
    reg {
        name="Submodule1CaptureValue0Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue0Cycle @ 0xa2;
    reg {
        name="Submodule1CaptureValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue1 @ 0xa4;
    reg {
        name="Submodule1CaptureValue1Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue1Cycle @ 0xa6;
    reg {
        name="Submodule1CaptureValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue2 @ 0xa8;
    reg {
        name="Submodule1CaptureValue2Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue2Cycle @ 0xaa;
    reg {
        name="Submodule1CaptureValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue3 @ 0xac;
    reg {
        name="Submodule1CaptureValue3Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue3Cycle @ 0xae;
    reg {
        name="Submodule1CaptureValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue4 @ 0xb0;
    reg {
        name="Submodule1CaptureValue4Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue4Cycle @ 0xb2;
    reg {
        name="Submodule1CaptureValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue5 @ 0xb4;
    reg {
        name="Submodule1CaptureValue5Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule1CaptureValue5Cycle @ 0xb6;
    reg {
        name="Submodule2Counter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Counter @ 0xc0;
    reg {
        name="Submodule2InitialCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2InitialCount @ 0xc2;
    reg {
        name="Submodule2Control2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Control2 @ 0xc4;
    reg {
        name="Submodule2Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Control @ 0xc6;
    reg {
        name="Submodule2Value0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Value0 @ 0xca;
    reg {
        name="Submodule2FractionalValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2FractionalValue1 @ 0xcc;
    reg {
        name="Submodule2Value1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Value1 @ 0xce;
    reg {
        name="Submodule2FractionalValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2FractionalValue2 @ 0xd0;
    reg {
        name="Submodule2Value2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Value2 @ 0xd2;
    reg {
        name="Submodule2FractionalValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2FractionalValue3 @ 0xd4;
    reg {
        name="Submodule2Value3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Value3 @ 0xd6;
    reg {
        name="Submodule2FractionalValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2FractionalValue4 @ 0xd8;
    reg {
        name="Submodule2Value4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Value4 @ 0xda;
    reg {
        name="Submodule2FractionalValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2FractionalValue5 @ 0xdc;
    reg {
        name="Submodule2Value5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Value5 @ 0xde;
    reg {
        name="Submodule2FractionalControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2FractionalControl @ 0xe0;
    reg {
        name="Submodule2OutputControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2OutputControl @ 0xe2;
    reg {
        name="Submodule2Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2Status @ 0xe4;
    reg {
        name="Submodule2InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2InterruptEnable @ 0xe6;
    reg {
        name="Submodule2DMAEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2DMAEnable @ 0xe8;
    reg {
        name="Submodule2OutputTriggerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2OutputTriggerControl @ 0xea;
    reg {
        name="Submodule2FaultDisableMapping0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2FaultDisableMapping0 @ 0xec;
    reg {
        name="Submodule2FaultDisableMapping1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2FaultDisableMapping1 @ 0xee;
    reg {
        name="Submodule2DeadtimeCount0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2DeadtimeCount0 @ 0xf0;
    reg {
        name="Submodule2DeadtimeCount1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2DeadtimeCount1 @ 0xf2;
    reg {
        name="Submodule2CaptureControlA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureControlA @ 0xf4;
    reg {
        name="Submodule2CaptureCompareA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureCompareA @ 0xf6;
    reg {
        name="Submodule2CaptureControlB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureControlB @ 0xf8;
    reg {
        name="Submodule2CaptureCompareB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureCompareB @ 0xfa;
    reg {
        name="Submodule2CaptureControlX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureControlX @ 0xfc;
    reg {
        name="Submodule2CaptureCompareX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureCompareX @ 0xfe;
    reg {
        name="Submodule2CaptureValue0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue0 @ 0x100;
    reg {
        name="Submodule2CaptureValue0Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue0Cycle @ 0x102;
    reg {
        name="Submodule2CaptureValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue1 @ 0x104;
    reg {
        name="Submodule2CaptureValue1Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue1Cycle @ 0x106;
    reg {
        name="Submodule2CaptureValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue2 @ 0x108;
    reg {
        name="Submodule2CaptureValue2Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue2Cycle @ 0x10a;
    reg {
        name="Submodule2CaptureValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue3 @ 0x10c;
    reg {
        name="Submodule2CaptureValue3Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue3Cycle @ 0x10e;
    reg {
        name="Submodule2CaptureValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue4 @ 0x110;
    reg {
        name="Submodule2CaptureValue4Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue4Cycle @ 0x112;
    reg {
        name="Submodule2CaptureValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue5 @ 0x114;
    reg {
        name="Submodule2CaptureValue5Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule2CaptureValue5Cycle @ 0x116;
    reg {
        name="Submodule3Counter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Counter @ 0x120;
    reg {
        name="Submodule3InitialCount";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3InitialCount @ 0x122;
    reg {
        name="Submodule3Control2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Control2 @ 0x124;
    reg {
        name="Submodule3Control";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Control @ 0x126;
    reg {
        name="Submodule3Value0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Value0 @ 0x12a;
    reg {
        name="Submodule3FractionalValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3FractionalValue1 @ 0x12c;
    reg {
        name="Submodule3Value1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Value1 @ 0x12e;
    reg {
        name="Submodule3FractionalValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3FractionalValue2 @ 0x130;
    reg {
        name="Submodule3Value2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Value2 @ 0x132;
    reg {
        name="Submodule3FractionalValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3FractionalValue3 @ 0x134;
    reg {
        name="Submodule3Value3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Value3 @ 0x136;
    reg {
        name="Submodule3FractionalValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3FractionalValue4 @ 0x138;
    reg {
        name="Submodule3Value4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Value4 @ 0x13a;
    reg {
        name="Submodule3FractionalValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3FractionalValue5 @ 0x13c;
    reg {
        name="Submodule3Value5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Value5 @ 0x13e;
    reg {
        name="Submodule3FractionalControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3FractionalControl @ 0x140;
    reg {
        name="Submodule3OutputControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3OutputControl @ 0x142;
    reg {
        name="Submodule3Status";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3Status @ 0x144;
    reg {
        name="Submodule3InterruptEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3InterruptEnable @ 0x146;
    reg {
        name="Submodule3DMAEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3DMAEnable @ 0x148;
    reg {
        name="Submodule3OutputTriggerControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3OutputTriggerControl @ 0x14a;
    reg {
        name="Submodule3FaultDisableMapping0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3FaultDisableMapping0 @ 0x14c;
    reg {
        name="Submodule3FaultDisableMapping1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3FaultDisableMapping1 @ 0x14e;
    reg {
        name="Submodule3DeadtimeCount0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3DeadtimeCount0 @ 0x150;
    reg {
        name="Submodule3DeadtimeCount1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3DeadtimeCount1 @ 0x152;
    reg {
        name="Submodule3CaptureControlA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureControlA @ 0x154;
    reg {
        name="Submodule3CaptureCompareA";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureCompareA @ 0x156;
    reg {
        name="Submodule3CaptureControlB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureControlB @ 0x158;
    reg {
        name="Submodule3CaptureCompareB";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureCompareB @ 0x15a;
    reg {
        name="Submodule3CaptureControlX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureControlX @ 0x15c;
    reg {
        name="Submodule3CaptureCompareX";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureCompareX @ 0x15e;
    reg {
        name="Submodule3CaptureValue0";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue0 @ 0x160;
    reg {
        name="Submodule3CaptureValue0Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue0Cycle @ 0x162;
    reg {
        name="Submodule3CaptureValue1";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue1 @ 0x164;
    reg {
        name="Submodule3CaptureValue1Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue1Cycle @ 0x166;
    reg {
        name="Submodule3CaptureValue2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue2 @ 0x168;
    reg {
        name="Submodule3CaptureValue2Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue2Cycle @ 0x16a;
    reg {
        name="Submodule3CaptureValue3";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue3 @ 0x16c;
    reg {
        name="Submodule3CaptureValue3Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue3Cycle @ 0x16e;
    reg {
        name="Submodule3CaptureValue4";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue4 @ 0x170;
    reg {
        name="Submodule3CaptureValue4Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue4Cycle @ 0x172;
    reg {
        name="Submodule3CaptureValue5";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue5 @ 0x174;
    reg {
        name="Submodule3CaptureValue5Cycle";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Submodule3CaptureValue5Cycle @ 0x176;
    reg {
        name="OutputEnable";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } OutputEnable @ 0x180;
    reg {
        name="Mask";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } Mask @ 0x182;
    reg {
        name="SoftwareControlledOutput";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } SoftwareControlledOutput @ 0x184;
    reg {
        name="PWMSourceSelect";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } PWMSourceSelect @ 0x186;
    reg {
        name="MasterControl";
        regwidth=0x10;
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } LDOK___Load_Okay[3:0];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } CLDOK___Clear_Load_Okay[7:4];
            field {
                desc = "This field has the following custom Renode callbacks: Write.";
                sw = rw;
            } RUN___Run[11:8];
            field {
                desc = "The field is a Tag.";
                sw = rw;
            } IPOL___Current_Polarity[15:12];
    } MasterControl @ 0x188;
    reg {
        name="MasterControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } MasterControl2 @ 0x18a;
    reg {
        name="FaultControl";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FaultControl @ 0x18c;
    reg {
        name="FaultStatus";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FaultStatus @ 0x18e;
    reg {
        name="FaultFilter";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FaultFilter @ 0x190;
    reg {
        name="FaultTest";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FaultTest @ 0x192;
    reg {
        name="FaultControl2";
        desc = "Could not determine register's width, guessed 8 bits.";
        regwidth=0x8;
            field {
                desc = "This is a dummy r/w field, generated just to show the register in specs";
                sw = rw;
            } DUMMY[7:0];
    } FaultControl2 @ 0x194;
} Registers_addrmap;


};